MipsSEInstrInfo.cpp revision c713e996d305df99cc7fc58c9d8dc1f5fa00518d 
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/TargetRegistry.h"
23
24using namespace llvm;
25
26MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
27  : MipsInstrInfo(tm,
28                  tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
29    RI(*tm.getSubtargetImpl(), *this),
30    IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
31
32const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
33  return RI;
34}
35
36/// isLoadFromStackSlot - If the specified machine instruction is a direct
37/// load from a stack slot, return the virtual or physical register number of
38/// the destination along with the FrameIndex of the loaded stack slot.  If
39/// not, return 0.  This predicate must return 0 if the instruction has
40/// any side effects other than loading from the stack slot.
41unsigned MipsSEInstrInfo::
42isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
43{
44  unsigned Opc = MI->getOpcode();
45
46  if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
47      (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
48      (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
49      (Opc == Mips::LDC164_P8)) {
50    if ((MI->getOperand(1).isFI()) && // is a stack slot
51        (MI->getOperand(2).isImm()) &&  // the imm is zero
52        (isZeroImm(MI->getOperand(2)))) {
53      FrameIndex = MI->getOperand(1).getIndex();
54      return MI->getOperand(0).getReg();
55    }
56  }
57
58  return 0;
59}
60
61/// isStoreToStackSlot - If the specified machine instruction is a direct
62/// store to a stack slot, return the virtual or physical register number of
63/// the source reg along with the FrameIndex of the loaded stack slot.  If
64/// not, return 0.  This predicate must return 0 if the instruction has
65/// any side effects other than storing to the stack slot.
66unsigned MipsSEInstrInfo::
67isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68{
69  unsigned Opc = MI->getOpcode();
70
71  if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
72      (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
73      (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
74      (Opc == Mips::SDC164_P8)) {
75    if ((MI->getOperand(1).isFI()) && // is a stack slot
76        (MI->getOperand(2).isImm()) &&  // the imm is zero
77        (isZeroImm(MI->getOperand(2)))) {
78      FrameIndex = MI->getOperand(1).getIndex();
79      return MI->getOperand(0).getReg();
80    }
81  }
82  return 0;
83}
84
85void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
86                                  MachineBasicBlock::iterator I, DebugLoc DL,
87                                  unsigned DestReg, unsigned SrcReg,
88                                  bool KillSrc) const {
89  unsigned Opc = 0, ZeroReg = 0;
90
91  if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
92    if (Mips::CPURegsRegClass.contains(SrcReg))
93      Opc = Mips::OR, ZeroReg = Mips::ZERO;
94    else if (Mips::CCRRegClass.contains(SrcReg))
95      Opc = Mips::CFC1;
96    else if (Mips::FGR32RegClass.contains(SrcReg))
97      Opc = Mips::MFC1;
98    else if (SrcReg == Mips::HI)
99      Opc = Mips::MFHI, SrcReg = 0;
100    else if (SrcReg == Mips::LO)
101      Opc = Mips::MFLO, SrcReg = 0;
102  }
103  else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
104    if (Mips::CCRRegClass.contains(DestReg))
105      Opc = Mips::CTC1;
106    else if (Mips::FGR32RegClass.contains(DestReg))
107      Opc = Mips::MTC1;
108    else if (DestReg == Mips::HI)
109      Opc = Mips::MTHI, DestReg = 0;
110    else if (DestReg == Mips::LO)
111      Opc = Mips::MTLO, DestReg = 0;
112  }
113  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
114    Opc = Mips::FMOV_S;
115  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
116    Opc = Mips::FMOV_D32;
117  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
118    Opc = Mips::FMOV_D64;
119  else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
120    Opc = Mips::MOVCCRToCCR;
121  else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
122    if (Mips::CPU64RegsRegClass.contains(SrcReg))
123      Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
124    else if (SrcReg == Mips::HI64)
125      Opc = Mips::MFHI64, SrcReg = 0;
126    else if (SrcReg == Mips::LO64)
127      Opc = Mips::MFLO64, SrcReg = 0;
128    else if (Mips::FGR64RegClass.contains(SrcReg))
129      Opc = Mips::DMFC1;
130  }
131  else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
132    if (DestReg == Mips::HI64)
133      Opc = Mips::MTHI64, DestReg = 0;
134    else if (DestReg == Mips::LO64)
135      Opc = Mips::MTLO64, DestReg = 0;
136    else if (Mips::FGR64RegClass.contains(DestReg))
137      Opc = Mips::DMTC1;
138  }
139
140  assert(Opc && "Cannot copy registers");
141
142  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
143
144  if (DestReg)
145    MIB.addReg(DestReg, RegState::Define);
146
147  if (SrcReg)
148    MIB.addReg(SrcReg, getKillRegState(KillSrc));
149
150  if (ZeroReg)
151    MIB.addReg(ZeroReg);
152}
153
154void MipsSEInstrInfo::
155storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
156                unsigned SrcReg, bool isKill, int FI,
157                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
158                int64_t Offset) const {
159  DebugLoc DL;
160  if (I != MBB.end()) DL = I->getDebugLoc();
161  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
162
163  unsigned Opc = 0;
164
165  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
166    Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
167  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
168    Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
169  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
170    Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
171  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
172    Opc = Mips::SDC1;
173  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
174    Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
175
176  assert(Opc && "Register class not handled!");
177  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
178    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
179}
180
181void MipsSEInstrInfo::
182loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
183                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
184                 const TargetRegisterInfo *TRI, int64_t Offset) const {
185  DebugLoc DL;
186  if (I != MBB.end()) DL = I->getDebugLoc();
187  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
188  unsigned Opc = 0;
189
190  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
191    Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
192  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
193    Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
194  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
195    Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
196  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
197    Opc = Mips::LDC1;
198  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
199    Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
200
201  assert(Opc && "Register class not handled!");
202  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
203    .addMemOperand(MMO);
204}
205
206bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
207  MachineBasicBlock &MBB = *MI->getParent();
208
209  switch(MI->getDesc().getOpcode()) {
210  default:
211    return false;
212  case Mips::RetRA:
213    ExpandRetRA(MBB, MI, Mips::RET);
214    break;
215  case Mips::BuildPairF64:
216    ExpandBuildPairF64(MBB, MI);
217    break;
218  case Mips::ExtractElementF64:
219    ExpandExtractElementF64(MBB, MI);
220    break;
221  case Mips::MIPSeh_return32:
222  case Mips::MIPSeh_return64:
223    ExpandEhReturn(MBB, MI);
224    break;
225  }
226
227  MBB.erase(MI);
228  return true;
229}
230
231/// GetOppositeBranchOpc - Return the inverse of the specified
232/// opcode, e.g. turning BEQ to BNE.
233unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
234  switch (Opc) {
235  default:           llvm_unreachable("Illegal opcode!");
236  case Mips::BEQ:    return Mips::BNE;
237  case Mips::BNE:    return Mips::BEQ;
238  case Mips::BGTZ:   return Mips::BLEZ;
239  case Mips::BGEZ:   return Mips::BLTZ;
240  case Mips::BLTZ:   return Mips::BGEZ;
241  case Mips::BLEZ:   return Mips::BGTZ;
242  case Mips::BEQ64:  return Mips::BNE64;
243  case Mips::BNE64:  return Mips::BEQ64;
244  case Mips::BGTZ64: return Mips::BLEZ64;
245  case Mips::BGEZ64: return Mips::BLTZ64;
246  case Mips::BLTZ64: return Mips::BGEZ64;
247  case Mips::BLEZ64: return Mips::BGTZ64;
248  case Mips::BC1T:   return Mips::BC1F;
249  case Mips::BC1F:   return Mips::BC1T;
250  }
251}
252
253/// Adjust SP by Amount bytes.
254void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
255                                     MachineBasicBlock &MBB,
256                                     MachineBasicBlock::iterator I) const {
257  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
258  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
259  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
260  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
261
262  if (isInt<16>(Amount))// addi sp, sp, amount
263    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
264  else { // Expand immediate that doesn't fit in 16-bit.
265    unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
266    BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
267  }
268}
269
270/// This function generates the sequence of instructions needed to get the
271/// result of adding register REG and immediate IMM.
272unsigned
273MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
274                               MachineBasicBlock::iterator II, DebugLoc DL,
275                               unsigned *NewImm) const {
276  MipsAnalyzeImmediate AnalyzeImm;
277  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
278  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
279  unsigned Size = STI.isABI_N64() ? 64 : 32;
280  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
281  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
282  const TargetRegisterClass *RC = STI.isABI_N64() ?
283    &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
284  bool LastInstrIsADDiu = NewImm;
285
286  const MipsAnalyzeImmediate::InstSeq &Seq =
287    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
288  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
289
290  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
291
292  // The first instruction can be a LUi, which is different from other
293  // instructions (ADDiu, ORI and SLL) in that it does not have a register
294  // operand.
295  unsigned Reg = RegInfo.createVirtualRegister(RC);
296
297  if (Inst->Opc == LUi)
298    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
299  else
300    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
301      .addImm(SignExtend64<16>(Inst->ImmOpnd));
302
303  // Build the remaining instructions in Seq.
304  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
305    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
306      .addImm(SignExtend64<16>(Inst->ImmOpnd));
307
308  if (LastInstrIsADDiu)
309    *NewImm = Inst->ImmOpnd;
310
311  return Reg;
312}
313
314unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
315  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
316          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
317          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
318          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
319          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
320          Opc == Mips::J) ?
321         Opc : 0;
322}
323
324void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
325                                MachineBasicBlock::iterator I,
326                                unsigned Opc) const {
327  BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
328}
329
330void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
331                                          MachineBasicBlock::iterator I) const {
332  unsigned DstReg = I->getOperand(0).getReg();
333  unsigned SrcReg = I->getOperand(1).getReg();
334  unsigned N = I->getOperand(2).getImm();
335  const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
336  DebugLoc dl = I->getDebugLoc();
337
338  assert(N < 2 && "Invalid immediate");
339  unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
340  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
341
342  BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
343}
344
345void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
346                                       MachineBasicBlock::iterator I) const {
347  unsigned DstReg = I->getOperand(0).getReg();
348  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
349  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
350  DebugLoc dl = I->getDebugLoc();
351  const TargetRegisterInfo &TRI = getRegisterInfo();
352
353  // mtc1 Lo, $fp
354  // mtc1 Hi, $fp + 1
355  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
356    .addReg(LoReg);
357  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
358    .addReg(HiReg);
359}
360
361void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB,
362                                     MachineBasicBlock::iterator I) const {
363  // This pseudo instruction is generated as part of the lowering of
364  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
365  // indirect jump to TargetReg
366  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
367  unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
368  unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR;
369  unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
370  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
371  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
372  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
373  unsigned OffsetReg = I->getOperand(0).getReg();
374  unsigned TargetReg = I->getOperand(1).getReg();
375
376  // or   $ra, $v0, $zero
377  // addu $sp, $sp, $v1
378  // jr   $ra
379  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
380      .addReg(TargetReg).addReg(ZERO);
381  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
382      .addReg(SP).addReg(OffsetReg);
383  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
384}
385
386const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
387  return new MipsSEInstrInfo(TM);
388}
389