NVPTXRegisterInfo.cpp revision 37ed9c199ca639565f6ce88105f9e39e898d82d0 
1//===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the NVPTX implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "NVPTXRegisterInfo.h"
15#include "NVPTX.h"
16#include "NVPTXSubtarget.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/MC/MachineLocation.h"
22#include "llvm/Target/TargetInstrInfo.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "nvptx-reg-info"
27
28namespace llvm {
29std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30  if (RC == &NVPTX::Float32RegsRegClass) {
31    return ".f32";
32  }
33  if (RC == &NVPTX::Float64RegsRegClass) {
34    return ".f64";
35  } else if (RC == &NVPTX::Int64RegsRegClass) {
36    return ".s64";
37  } else if (RC == &NVPTX::Int32RegsRegClass) {
38    return ".s32";
39  } else if (RC == &NVPTX::Int16RegsRegClass) {
40    return ".s16";
41  } else if (RC == &NVPTX::Int1RegsRegClass) {
42    return ".pred";
43  } else if (RC == &NVPTX::SpecialRegsRegClass) {
44    return "!Special!";
45  } else {
46    return "INTERNAL";
47  }
48  return "";
49}
50
51std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
52  if (RC == &NVPTX::Float32RegsRegClass) {
53    return "%f";
54  }
55  if (RC == &NVPTX::Float64RegsRegClass) {
56    return "%fd";
57  } else if (RC == &NVPTX::Int64RegsRegClass) {
58    return "%rd";
59  } else if (RC == &NVPTX::Int32RegsRegClass) {
60    return "%r";
61  } else if (RC == &NVPTX::Int16RegsRegClass) {
62    return "%rs";
63  } else if (RC == &NVPTX::Int1RegsRegClass) {
64    return "%p";
65  } else if (RC == &NVPTX::SpecialRegsRegClass) {
66    return "!Special!";
67  } else {
68    return "INTERNAL";
69  }
70  return "";
71}
72}
73
74NVPTXRegisterInfo::NVPTXRegisterInfo(const NVPTXSubtarget &st)
75    : NVPTXGenRegisterInfo(0), Is64Bit(st.is64Bit()) {}
76
77#define GET_REGINFO_TARGET_DESC
78#include "NVPTXGenRegisterInfo.inc"
79
80/// NVPTX Callee Saved Registers
81const MCPhysReg *
82NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
83  static const MCPhysReg CalleeSavedRegs[] = { 0 };
84  return CalleeSavedRegs;
85}
86
87BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
88  BitVector Reserved(getNumRegs());
89  return Reserved;
90}
91
92void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
93                                            int SPAdj, unsigned FIOperandNum,
94                                            RegScavenger *RS) const {
95  assert(SPAdj == 0 && "Unexpected");
96
97  MachineInstr &MI = *II;
98  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
99
100  MachineFunction &MF = *MI.getParent()->getParent();
101  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
102               MI.getOperand(FIOperandNum + 1).getImm();
103
104  // Using I0 as the frame pointer
105  MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
106  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
107}
108
109unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
110  return NVPTX::VRFrame;
111}
112