Name | Date | Size | |
---|---|---|---|
.. | 23-Aug-2016 | 4 KiB | |
AsmParser/ | 23-Aug-2016 | 4 KiB | |
CMakeLists.txt | 23-Aug-2016 | 1 KiB | |
DelaySlotFiller.cpp | 23-Aug-2016 | 14.3 KiB | |
Disassembler/ | 23-Aug-2016 | 4 KiB | |
InstPrinter/ | 23-Aug-2016 | 4 KiB | |
LLVMBuild.txt | 23-Aug-2016 | 1 KiB | |
Makefile | 23-Aug-2016 | 798 | |
MCTargetDesc/ | 23-Aug-2016 | 4 KiB | |
README.txt | 23-Aug-2016 | 1.5 KiB | |
Sparc.h | 23-Aug-2016 | 4.3 KiB | |
Sparc.td | 23-Aug-2016 | 4 KiB | |
SparcAsmPrinter.cpp | 23-Aug-2016 | 16.3 KiB | |
SparcCallingConv.td | 23-Aug-2016 | 5.6 KiB | |
SparcFrameLowering.cpp | 23-Aug-2016 | 13.2 KiB | |
SparcFrameLowering.h | 23-Aug-2016 | 2.4 KiB | |
SparcInstr64Bit.td | 23-Aug-2016 | 23.3 KiB | |
SparcInstrAliases.td | 23-Aug-2016 | 19.1 KiB | |
SparcInstrFormats.td | 23-Aug-2016 | 9.1 KiB | |
SparcInstrInfo.cpp | 23-Aug-2016 | 16.2 KiB | |
SparcInstrInfo.h | 23-Aug-2016 | 3.8 KiB | |
SparcInstrInfo.td | 23-Aug-2016 | 57 KiB | |
SparcInstrVIS.td | 23-Aug-2016 | 11.1 KiB | |
SparcISelDAGToDAG.cpp | 23-Aug-2016 | 14.6 KiB | |
SparcISelLowering.cpp | 23-Aug-2016 | 132 KiB | |
SparcISelLowering.h | 23-Aug-2016 | 8.6 KiB | |
SparcMachineFunctionInfo.cpp | 23-Aug-2016 | 448 | |
SparcMachineFunctionInfo.h | 23-Aug-2016 | 1.9 KiB | |
SparcMCInstLower.cpp | 23-Aug-2016 | 3.3 KiB | |
SparcRegisterInfo.cpp | 23-Aug-2016 | 8.2 KiB | |
SparcRegisterInfo.h | 23-Aug-2016 | 1.8 KiB | |
SparcRegisterInfo.td | 23-Aug-2016 | 11.5 KiB | |
SparcSubtarget.cpp | 23-Aug-2016 | 2.8 KiB | |
SparcSubtarget.h | 23-Aug-2016 | 3 KiB | |
SparcTargetMachine.cpp | 23-Aug-2016 | 4.5 KiB | |
SparcTargetMachine.h | 23-Aug-2016 | 2.6 KiB | |
SparcTargetObjectFile.cpp | 23-Aug-2016 | 1.6 KiB | |
SparcTargetObjectFile.h | 23-Aug-2016 | 1,014 | |
SparcTargetStreamer.h | 23-Aug-2016 | 1.5 KiB | |
TargetInfo/ | 23-Aug-2016 | 4 KiB |
README.txt
1 2To-do 3----- 4 5* Keep the address of the constant pool in a register instead of forming its 6 address all of the time. 7* We can fold small constant offsets into the %hi/%lo references to constant 8 pool addresses as well. 9* When in V9 mode, register allocate %icc[0-3]. 10* Add support for isel'ing UMUL_LOHI instead of marking it as Expand. 11* Emit the 'Branch on Integer Register with Prediction' instructions. It's 12 not clear how to write a pattern for this though: 13 14float %t1(int %a, int* %p) { 15 %C = seteq int %a, 0 16 br bool %C, label %T, label %F 17T: 18 store int 123, int* %p 19 br label %F 20F: 21 ret float undef 22} 23 24codegens to this: 25 26t1: 27 save -96, %o6, %o6 281) subcc %i0, 0, %l0 291) bne .LBBt1_2 ! F 30 nop 31.LBBt1_1: ! T 32 or %g0, 123, %l0 33 st %l0, [%i1] 34.LBBt1_2: ! F 35 restore %g0, %g0, %g0 36 retl 37 nop 38 391) should be replaced with a brz in V9 mode. 40 41* Same as above, but emit conditional move on register zero (p192) in V9 42 mode. Testcase: 43 44int %t1(int %a, int %b) { 45 %C = seteq int %a, 0 46 %D = select bool %C, int %a, int %b 47 ret int %D 48} 49 50* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 51 with the Y register, if they are faster. 52 53* Codegen bswap(load)/store(bswap) -> load/store ASI 54 55* Implement frame pointer elimination, e.g. eliminate save/restore for 56 leaf fns. 57* Fill delay slots 58 59* Use %g0 directly to materialize 0. No instruction is required. 60