SparcISelLowering.cpp revision 9468a9b6beed640eca64274c8dcc5aed3b94450b 
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24using namespace llvm;
25
26
27//===----------------------------------------------------------------------===//
28// Calling Convention Implementation
29//===----------------------------------------------------------------------===//
30
31#include "SparcGenCallingConv.inc"
32
33static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
34  // CCValAssign - represent the assignment of the return value to locations.
35  SmallVector<CCValAssign, 16> RVLocs;
36  unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
37  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
38
39  // CCState - Info about the registers and stack slot.
40  CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
41
42  // Analize return values of ISD::RET
43  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
44
45  // If this is the first return lowered for this function, add the regs to the
46  // liveout set for the function.
47  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
48    for (unsigned i = 0; i != RVLocs.size(); ++i)
49      if (RVLocs[i].isRegLoc())
50        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
51  }
52
53  SDValue Chain = Op.getOperand(0);
54  SDValue Flag;
55
56  // Copy the result values into the output registers.
57  for (unsigned i = 0; i != RVLocs.size(); ++i) {
58    CCValAssign &VA = RVLocs[i];
59    assert(VA.isRegLoc() && "Can only return in registers!");
60
61    // ISD::RET => ret chain, (regnum1,val1), ...
62    // So i*2+1 index only the regnums.
63    Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
64
65    // Guarantee that all emitted copies are stuck together with flags.
66    Flag = Chain.getValue(1);
67  }
68
69  if (Flag.getNode())
70    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
71  return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
72}
73
74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
75/// either one or two GPRs, including FP values.  TODO: we should pass FP values
76/// in FP registers for fastcc functions.
77void
78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
79                                    SmallVectorImpl<SDValue> &ArgValues) {
80  MachineFunction &MF = DAG.getMachineFunction();
81  MachineRegisterInfo &RegInfo = MF.getRegInfo();
82
83  static const unsigned ArgRegs[] = {
84    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85  };
86
87  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
88  unsigned ArgOffset = 68;
89
90  SDValue Root = DAG.getRoot();
91  std::vector<SDValue> OutChains;
92
93  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
94    MVT ObjectVT = getValueType(I->getType());
95
96    switch (ObjectVT.getSimpleVT()) {
97    default: assert(0 && "Unhandled argument type!");
98    case MVT::i1:
99    case MVT::i8:
100    case MVT::i16:
101    case MVT::i32:
102      if (I->use_empty()) {                // Argument is dead.
103        if (CurArgReg < ArgRegEnd) ++CurArgReg;
104        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
105      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
106        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
107        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
108        SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
109        if (ObjectVT != MVT::i32) {
110          unsigned AssertOp = ISD::AssertSext;
111          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
112                            DAG.getValueType(ObjectVT));
113          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
114        }
115        ArgValues.push_back(Arg);
116      } else {
117        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
118        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
119        SDValue Load;
120        if (ObjectVT == MVT::i32) {
121          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
122        } else {
123          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
124
125          // Sparc is big endian, so add an offset based on the ObjectVT.
126          unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
127          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
128                              DAG.getConstant(Offset, MVT::i32));
129          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
130                                NULL, 0, ObjectVT);
131          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
132        }
133        ArgValues.push_back(Load);
134      }
135
136      ArgOffset += 4;
137      break;
138    case MVT::f32:
139      if (I->use_empty()) {                // Argument is dead.
140        if (CurArgReg < ArgRegEnd) ++CurArgReg;
141        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
142      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
143        // FP value is passed in an integer register.
144        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
145        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
146        SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
147
148        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
149        ArgValues.push_back(Arg);
150      } else {
151        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
152        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
153        SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
154        ArgValues.push_back(Load);
155      }
156      ArgOffset += 4;
157      break;
158
159    case MVT::i64:
160    case MVT::f64:
161      if (I->use_empty()) {                // Argument is dead.
162        if (CurArgReg < ArgRegEnd) ++CurArgReg;
163        if (CurArgReg < ArgRegEnd) ++CurArgReg;
164        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
165      } else {
166        SDValue HiVal;
167        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
168          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
169          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
170          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
171        } else {
172          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
173          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
174          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
175        }
176
177        SDValue LoVal;
178        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
179          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
180          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
181          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
182        } else {
183          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
184          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
185          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
186        }
187
188        // Compose the two halves together into an i64 unit.
189        SDValue WholeValue =
190          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
191
192        // If we want a double, do a bit convert.
193        if (ObjectVT == MVT::f64)
194          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
195
196        ArgValues.push_back(WholeValue);
197      }
198      ArgOffset += 8;
199      break;
200    }
201  }
202
203  // Store remaining ArgRegs to the stack if this is a varargs function.
204  if (F.isVarArg()) {
205    // Remember the vararg offset for the va_start implementation.
206    VarArgsFrameOffset = ArgOffset;
207
208    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
209      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
210      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
211      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
212
213      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
214      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
215
216      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
217      ArgOffset += 4;
218    }
219  }
220
221  if (!OutChains.empty())
222    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
223                            &OutChains[0], OutChains.size()));
224}
225
226static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
227  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
228  unsigned CallingConv = TheCall->getCallingConv();
229  SDValue Chain = TheCall->getChain();
230  SDValue Callee = TheCall->getCallee();
231  bool isVarArg = TheCall->isVarArg();
232
233#if 0
234  // Analyze operands of the call, assigning locations to each operand.
235  SmallVector<CCValAssign, 16> ArgLocs;
236  CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
237  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
238
239  // Get the size of the outgoing arguments stack space requirement.
240  unsigned ArgsSize = CCInfo.getNextStackOffset();
241  // FIXME: We can't use this until f64 is known to take two GPRs.
242#else
243  (void)CC_Sparc32;
244
245  // Count the size of the outgoing arguments.
246  unsigned ArgsSize = 0;
247  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
248    switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
249      default: assert(0 && "Unknown value type!");
250      case MVT::i1:
251      case MVT::i8:
252      case MVT::i16:
253      case MVT::i32:
254      case MVT::f32:
255        ArgsSize += 4;
256        break;
257      case MVT::i64:
258      case MVT::f64:
259        ArgsSize += 8;
260        break;
261    }
262  }
263  if (ArgsSize > 4*6)
264    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
265  else
266    ArgsSize = 0;
267#endif
268
269  // Keep stack frames 8-byte aligned.
270  ArgsSize = (ArgsSize+7) & ~7;
271
272  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize));
273
274  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
275  SmallVector<SDValue, 8> MemOpChains;
276
277#if 0
278  // Walk the register/memloc assignments, inserting copies/loads.
279  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
280    CCValAssign &VA = ArgLocs[i];
281
282    // Arguments start after the 5 first operands of ISD::CALL
283    SDValue Arg = TheCall->getArg(i);
284
285    // Promote the value if needed.
286    switch (VA.getLocInfo()) {
287    default: assert(0 && "Unknown loc info!");
288    case CCValAssign::Full: break;
289    case CCValAssign::SExt:
290      Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
291      break;
292    case CCValAssign::ZExt:
293      Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
294      break;
295    case CCValAssign::AExt:
296      Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
297      break;
298    }
299
300    // Arguments that can be passed on register must be kept at
301    // RegsToPass vector
302    if (VA.isRegLoc()) {
303      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
304      continue;
305    }
306
307    assert(VA.isMemLoc());
308
309    // Create a store off the stack pointer for this argument.
310    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
311    // FIXME: VERIFY THAT 68 IS RIGHT.
312    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
313    PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
314    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
315  }
316
317#else
318  static const unsigned ArgRegs[] = {
319    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
320  };
321  unsigned ArgOffset = 68;
322
323  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
324    SDValue Val = TheCall->getArg(i);
325    MVT ObjectVT = Val.getValueType();
326    SDValue ValToStore(0, 0);
327    unsigned ObjSize;
328    switch (ObjectVT.getSimpleVT()) {
329    default: assert(0 && "Unhandled argument type!");
330    case MVT::i32:
331      ObjSize = 4;
332
333      if (RegsToPass.size() >= 6) {
334        ValToStore = Val;
335      } else {
336        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
337      }
338      break;
339    case MVT::f32:
340      ObjSize = 4;
341      if (RegsToPass.size() >= 6) {
342        ValToStore = Val;
343      } else {
344        // Convert this to a FP value in an int reg.
345        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
346        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
347      }
348      break;
349    case MVT::f64:
350      ObjSize = 8;
351      // Otherwise, convert this to a FP value in int regs.
352      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
353      // FALL THROUGH
354    case MVT::i64:
355      ObjSize = 8;
356      if (RegsToPass.size() >= 6) {
357        ValToStore = Val;    // Whole thing is passed in memory.
358        break;
359      }
360
361      // Split the value into top and bottom part.  Top part goes in a reg.
362      SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
363                                 DAG.getConstant(1, MVT::i32));
364      SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
365                                 DAG.getConstant(0, MVT::i32));
366      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
367
368      if (RegsToPass.size() >= 6) {
369        ValToStore = Lo;
370        ArgOffset += 4;
371        ObjSize = 4;
372      } else {
373        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
374      }
375      break;
376    }
377
378    if (ValToStore.getNode()) {
379      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
380      SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
381      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
382      MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
383    }
384    ArgOffset += ObjSize;
385  }
386#endif
387
388  // Emit all stores, make sure the occur before any copies into physregs.
389  if (!MemOpChains.empty())
390    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
391                        &MemOpChains[0], MemOpChains.size());
392
393  // Build a sequence of copy-to-reg nodes chained together with token
394  // chain and flag operands which copy the outgoing args into registers.
395  // The InFlag in necessary since all emited instructions must be
396  // stuck together.
397  SDValue InFlag;
398  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
399    unsigned Reg = RegsToPass[i].first;
400    // Remap I0->I7 -> O0->O7.
401    if (Reg >= SP::I0 && Reg <= SP::I7)
402      Reg = Reg-SP::I0+SP::O0;
403
404    Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag);
405    InFlag = Chain.getValue(1);
406  }
407
408  // If the callee is a GlobalAddress node (quite common, every direct call is)
409  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
410  // Likewise Symbol -> TargetSymbol.
411  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
412    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
413  else if (SymbolSDNode *S = dyn_cast<SymbolSDNode>(Callee))
414    Callee = DAG.getTargetSymbol(S->getSymbol(), MVT::i32, S->getLinkage());
415
416  std::vector<MVT> NodeTys;
417  NodeTys.push_back(MVT::Other);   // Returns a chain
418  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
419  SDValue Ops[] = { Chain, Callee, InFlag };
420  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
421  InFlag = Chain.getValue(1);
422
423  Chain = DAG.getCALLSEQ_END(Chain,
424                             DAG.getConstant(ArgsSize, MVT::i32),
425                             DAG.getConstant(0, MVT::i32), InFlag);
426  InFlag = Chain.getValue(1);
427
428  // Assign locations to each value returned by this call.
429  SmallVector<CCValAssign, 16> RVLocs;
430  CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
431
432  RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
433  SmallVector<SDValue, 8> ResultVals;
434
435  // Copy all of the result registers out of their specified physreg.
436  for (unsigned i = 0; i != RVLocs.size(); ++i) {
437    unsigned Reg = RVLocs[i].getLocReg();
438
439    // Remap I0->I7 -> O0->O7.
440    if (Reg >= SP::I0 && Reg <= SP::I7)
441      Reg = Reg-SP::I0+SP::O0;
442
443    Chain = DAG.getCopyFromReg(Chain, Reg,
444                               RVLocs[i].getValVT(), InFlag).getValue(1);
445    InFlag = Chain.getValue(2);
446    ResultVals.push_back(Chain.getValue(0));
447  }
448
449  ResultVals.push_back(Chain);
450
451  // Merge everything together with a MERGE_VALUES node.
452  return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
453                            ResultVals.size());
454}
455
456
457
458//===----------------------------------------------------------------------===//
459// TargetLowering Implementation
460//===----------------------------------------------------------------------===//
461
462/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
463/// condition.
464static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
465  switch (CC) {
466  default: assert(0 && "Unknown integer condition code!");
467  case ISD::SETEQ:  return SPCC::ICC_E;
468  case ISD::SETNE:  return SPCC::ICC_NE;
469  case ISD::SETLT:  return SPCC::ICC_L;
470  case ISD::SETGT:  return SPCC::ICC_G;
471  case ISD::SETLE:  return SPCC::ICC_LE;
472  case ISD::SETGE:  return SPCC::ICC_GE;
473  case ISD::SETULT: return SPCC::ICC_CS;
474  case ISD::SETULE: return SPCC::ICC_LEU;
475  case ISD::SETUGT: return SPCC::ICC_GU;
476  case ISD::SETUGE: return SPCC::ICC_CC;
477  }
478}
479
480/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
481/// FCC condition.
482static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
483  switch (CC) {
484  default: assert(0 && "Unknown fp condition code!");
485  case ISD::SETEQ:
486  case ISD::SETOEQ: return SPCC::FCC_E;
487  case ISD::SETNE:
488  case ISD::SETUNE: return SPCC::FCC_NE;
489  case ISD::SETLT:
490  case ISD::SETOLT: return SPCC::FCC_L;
491  case ISD::SETGT:
492  case ISD::SETOGT: return SPCC::FCC_G;
493  case ISD::SETLE:
494  case ISD::SETOLE: return SPCC::FCC_LE;
495  case ISD::SETGE:
496  case ISD::SETOGE: return SPCC::FCC_GE;
497  case ISD::SETULT: return SPCC::FCC_UL;
498  case ISD::SETULE: return SPCC::FCC_ULE;
499  case ISD::SETUGT: return SPCC::FCC_UG;
500  case ISD::SETUGE: return SPCC::FCC_UGE;
501  case ISD::SETUO:  return SPCC::FCC_U;
502  case ISD::SETO:   return SPCC::FCC_O;
503  case ISD::SETONE: return SPCC::FCC_LG;
504  case ISD::SETUEQ: return SPCC::FCC_UE;
505  }
506}
507
508
509SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
510  : TargetLowering(TM) {
511
512  // Set up the register classes.
513  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
514  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
515  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
516
517  // Turn FP extload into load/fextend
518  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
519  // Sparc doesn't have i1 sign extending load
520  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
521  // Turn FP truncstore into trunc + store.
522  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
523
524  // Custom legalize GlobalAddress nodes into LO/HI parts.
525  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
526  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
527  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
528
529  // Sparc doesn't have sext_inreg, replace them with shl/sra
530  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
531  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
532  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
533
534  // Sparc has no REM or DIVREM operations.
535  setOperationAction(ISD::UREM, MVT::i32, Expand);
536  setOperationAction(ISD::SREM, MVT::i32, Expand);
537  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
538  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
539
540  // Custom expand fp<->sint
541  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
542  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
543
544  // Expand fp<->uint
545  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
546  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
547
548  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
549  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
550
551  // Sparc has no select or setcc: expand to SELECT_CC.
552  setOperationAction(ISD::SELECT, MVT::i32, Expand);
553  setOperationAction(ISD::SELECT, MVT::f32, Expand);
554  setOperationAction(ISD::SELECT, MVT::f64, Expand);
555  setOperationAction(ISD::SETCC, MVT::i32, Expand);
556  setOperationAction(ISD::SETCC, MVT::f32, Expand);
557  setOperationAction(ISD::SETCC, MVT::f64, Expand);
558
559  // Sparc doesn't have BRCOND either, it has BR_CC.
560  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
561  setOperationAction(ISD::BRIND, MVT::Other, Expand);
562  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
563  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
564  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
565  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
566
567  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
568  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
569  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
570
571  // SPARC has no intrinsics for these particular operations.
572  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
573
574  setOperationAction(ISD::FSIN , MVT::f64, Expand);
575  setOperationAction(ISD::FCOS , MVT::f64, Expand);
576  setOperationAction(ISD::FREM , MVT::f64, Expand);
577  setOperationAction(ISD::FSIN , MVT::f32, Expand);
578  setOperationAction(ISD::FCOS , MVT::f32, Expand);
579  setOperationAction(ISD::FREM , MVT::f32, Expand);
580  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
581  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
582  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
583  setOperationAction(ISD::ROTL , MVT::i32, Expand);
584  setOperationAction(ISD::ROTR , MVT::i32, Expand);
585  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
586  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
587  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
588  setOperationAction(ISD::FPOW , MVT::f64, Expand);
589  setOperationAction(ISD::FPOW , MVT::f32, Expand);
590  setOperationAction(ISD::FLOG , MVT::f64, Expand);
591  setOperationAction(ISD::FLOG , MVT::f32, Expand);
592  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
593  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
594  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
595  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
596  setOperationAction(ISD::FEXP , MVT::f64, Expand);
597  setOperationAction(ISD::FEXP , MVT::f32, Expand);
598  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
599  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
600
601  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
602  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
603  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
604
605  // FIXME: Sparc provides these multiplies, but we don't have them yet.
606  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
607
608  // We don't have line number support yet.
609  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
610  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
611  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
612  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
613
614  // RET must be custom lowered, to meet ABI requirements
615  setOperationAction(ISD::RET               , MVT::Other, Custom);
616
617  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
618  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
619  // VAARG needs to be lowered to not do unaligned accesses for doubles.
620  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
621
622  // Use the default implementation.
623  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
624  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
625  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
626  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
627  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
628
629  // No debug info support yet.
630  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
631  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
632  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
633  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
634
635  setStackPointerRegisterToSaveRestore(SP::O6);
636
637  if (TM.getSubtarget<SparcSubtarget>().isV9())
638    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
639
640  computeRegisterProperties();
641}
642
643const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
644  switch (Opcode) {
645  default: return 0;
646  case SPISD::CMPICC:     return "SPISD::CMPICC";
647  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
648  case SPISD::BRICC:      return "SPISD::BRICC";
649  case SPISD::BRFCC:      return "SPISD::BRFCC";
650  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
651  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
652  case SPISD::Hi:         return "SPISD::Hi";
653  case SPISD::Lo:         return "SPISD::Lo";
654  case SPISD::FTOI:       return "SPISD::FTOI";
655  case SPISD::ITOF:       return "SPISD::ITOF";
656  case SPISD::CALL:       return "SPISD::CALL";
657  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
658  }
659}
660
661/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
662/// be zero. Op is expected to be a target specific node. Used by DAG
663/// combiner.
664void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
665                                                         const APInt &Mask,
666                                                         APInt &KnownZero,
667                                                         APInt &KnownOne,
668                                                         const SelectionDAG &DAG,
669                                                         unsigned Depth) const {
670  APInt KnownZero2, KnownOne2;
671  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
672
673  switch (Op.getOpcode()) {
674  default: break;
675  case SPISD::SELECT_ICC:
676  case SPISD::SELECT_FCC:
677    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
678                          Depth+1);
679    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
680                          Depth+1);
681    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
682    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
683
684    // Only known if known in both the LHS and RHS.
685    KnownOne &= KnownOne2;
686    KnownZero &= KnownZero2;
687    break;
688  }
689}
690
691// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
692// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
693static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
694                             ISD::CondCode CC, unsigned &SPCC) {
695  if (isa<ConstantSDNode>(RHS) &&
696      cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
697      CC == ISD::SETNE &&
698      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
699        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
700       (LHS.getOpcode() == SPISD::SELECT_FCC &&
701        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
702      isa<ConstantSDNode>(LHS.getOperand(0)) &&
703      isa<ConstantSDNode>(LHS.getOperand(1)) &&
704      cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
705      cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
706    SDValue CMPCC = LHS.getOperand(3);
707    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
708    LHS = CMPCC.getOperand(0);
709    RHS = CMPCC.getOperand(1);
710  }
711}
712
713static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
714  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
715  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
716  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
717  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
718  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
719}
720
721static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
722  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
723  Constant *C = N->getConstVal();
724  SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
725  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
726  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
727  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
728}
729
730static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
731  // Convert the fp value to integer in an FP register.
732  assert(Op.getValueType() == MVT::i32);
733  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
734  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
735}
736
737static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
738  assert(Op.getOperand(0).getValueType() == MVT::i32);
739  SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
740  // Convert the int value to FP in an FP register.
741  return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
742}
743
744static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
745  SDValue Chain = Op.getOperand(0);
746  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
747  SDValue LHS = Op.getOperand(2);
748  SDValue RHS = Op.getOperand(3);
749  SDValue Dest = Op.getOperand(4);
750  unsigned Opc, SPCC = ~0U;
751
752  // If this is a br_cc of a "setcc", and if the setcc got lowered into
753  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
754  LookThroughSetCC(LHS, RHS, CC, SPCC);
755
756  // Get the condition flag.
757  SDValue CompareFlag;
758  if (LHS.getValueType() == MVT::i32) {
759    std::vector<MVT> VTs;
760    VTs.push_back(MVT::i32);
761    VTs.push_back(MVT::Flag);
762    SDValue Ops[2] = { LHS, RHS };
763    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
764    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
765    Opc = SPISD::BRICC;
766  } else {
767    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
768    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
769    Opc = SPISD::BRFCC;
770  }
771  return DAG.getNode(Opc, MVT::Other, Chain, Dest,
772                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
773}
774
775static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
776  SDValue LHS = Op.getOperand(0);
777  SDValue RHS = Op.getOperand(1);
778  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
779  SDValue TrueVal = Op.getOperand(2);
780  SDValue FalseVal = Op.getOperand(3);
781  unsigned Opc, SPCC = ~0U;
782
783  // If this is a select_cc of a "setcc", and if the setcc got lowered into
784  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
785  LookThroughSetCC(LHS, RHS, CC, SPCC);
786
787  SDValue CompareFlag;
788  if (LHS.getValueType() == MVT::i32) {
789    std::vector<MVT> VTs;
790    VTs.push_back(LHS.getValueType());   // subcc returns a value
791    VTs.push_back(MVT::Flag);
792    SDValue Ops[2] = { LHS, RHS };
793    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
794    Opc = SPISD::SELECT_ICC;
795    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
796  } else {
797    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
798    Opc = SPISD::SELECT_FCC;
799    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
800  }
801  return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
802                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
803}
804
805static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
806                              SparcTargetLowering &TLI) {
807  // vastart just stores the address of the VarArgsFrameIndex slot into the
808  // memory location argument.
809  SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
810                                 DAG.getRegister(SP::I6, MVT::i32),
811                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
812                                                 MVT::i32));
813  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
814  return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
815}
816
817static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
818  SDNode *Node = Op.getNode();
819  MVT VT = Node->getValueType(0);
820  SDValue InChain = Node->getOperand(0);
821  SDValue VAListPtr = Node->getOperand(1);
822  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
823  SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
824  // Increment the pointer, VAList, to the next vaarg
825  SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
826                                  DAG.getConstant(VT.getSizeInBits()/8,
827                                                  MVT::i32));
828  // Store the incremented VAList to the legalized pointer
829  InChain = DAG.getStore(VAList.getValue(1), NextPtr,
830                         VAListPtr, SV, 0);
831  // Load the actual argument out of the pointer VAList, unless this is an
832  // f64 load.
833  if (VT != MVT::f64)
834    return DAG.getLoad(VT, InChain, VAList, NULL, 0);
835
836  // Otherwise, load it as i64, then do a bitconvert.
837  SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
838
839  // Bit-Convert the value to f64.
840  SDValue Ops[2] = {
841    DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
842    V.getValue(1)
843  };
844  return DAG.getMergeValues(Ops, 2);
845}
846
847static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
848  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
849  SDValue Size  = Op.getOperand(1);  // Legalize the size.
850
851  unsigned SPReg = SP::O6;
852  SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
853  SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
854  Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
855
856  // The resultant pointer is actually 16 words from the bottom of the stack,
857  // to provide a register spill area.
858  SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
859                                 DAG.getConstant(96, MVT::i32));
860  SDValue Ops[2] = { NewVal, Chain };
861  return DAG.getMergeValues(Ops, 2);
862}
863
864
865SDValue SparcTargetLowering::
866LowerOperation(SDValue Op, SelectionDAG &DAG) {
867  switch (Op.getOpcode()) {
868  default: assert(0 && "Should not custom lower this!");
869  // Frame & Return address.  Currently unimplemented
870  case ISD::RETURNADDR: return SDValue();
871  case ISD::FRAMEADDR:  return SDValue();
872  case ISD::GlobalTLSAddress:
873    assert(0 && "TLS not implemented for Sparc.");
874  case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
875  case ISD::ConstantPool:       return LowerCONSTANTPOOL(Op, DAG);
876  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
877  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
878  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
879  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
880  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
881  case ISD::VAARG:              return LowerVAARG(Op, DAG);
882  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
883  case ISD::CALL:               return LowerCALL(Op, DAG);
884  case ISD::RET:                return LowerRET(Op, DAG);
885  }
886}
887
888MachineBasicBlock *
889SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
890                                                 MachineBasicBlock *BB) {
891  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
892  unsigned BROpcode;
893  unsigned CC;
894  // Figure out the conditional branch opcode to use for this select_cc.
895  switch (MI->getOpcode()) {
896  default: assert(0 && "Unknown SELECT_CC!");
897  case SP::SELECT_CC_Int_ICC:
898  case SP::SELECT_CC_FP_ICC:
899  case SP::SELECT_CC_DFP_ICC:
900    BROpcode = SP::BCOND;
901    break;
902  case SP::SELECT_CC_Int_FCC:
903  case SP::SELECT_CC_FP_FCC:
904  case SP::SELECT_CC_DFP_FCC:
905    BROpcode = SP::FBCOND;
906    break;
907  }
908
909  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
910
911  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
912  // control-flow pattern.  The incoming instruction knows the destination vreg
913  // to set, the condition code register to branch on, the true/false values to
914  // select between, and a branch opcode to use.
915  const BasicBlock *LLVM_BB = BB->getBasicBlock();
916  MachineFunction::iterator It = BB;
917  ++It;
918
919  //  thisMBB:
920  //  ...
921  //   TrueVal = ...
922  //   [f]bCC copy1MBB
923  //   fallthrough --> copy0MBB
924  MachineBasicBlock *thisMBB = BB;
925  MachineFunction *F = BB->getParent();
926  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
927  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
928  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
929  F->insert(It, copy0MBB);
930  F->insert(It, sinkMBB);
931  // Update machine-CFG edges by transferring all successors of the current
932  // block to the new block which will contain the Phi node for the select.
933  sinkMBB->transferSuccessors(BB);
934  // Next, add the true and fallthrough blocks as its successors.
935  BB->addSuccessor(copy0MBB);
936  BB->addSuccessor(sinkMBB);
937
938  //  copy0MBB:
939  //   %FalseValue = ...
940  //   # fallthrough to sinkMBB
941  BB = copy0MBB;
942
943  // Update machine-CFG edges
944  BB->addSuccessor(sinkMBB);
945
946  //  sinkMBB:
947  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
948  //  ...
949  BB = sinkMBB;
950  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
951    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
952    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
953
954  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
955  return BB;
956}
957
958