X86Subtarget.h revision 922d314e8f9f0d8e447c055485a2969ee9cf2dd2 
1//=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/CallingConv.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  enum X86ProcFamilyEnum {
53    Others, IntelAtom
54  };
55
56  /// X86ProcFamily - X86 processor family: Intel Atom, and others
57  X86ProcFamilyEnum X86ProcFamily;
58
59  /// PICStyle - Which PIC style to use
60  ///
61  PICStyles::Style PICStyle;
62
63  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
64  /// none supported.
65  X86SSEEnum X86SSELevel;
66
67  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
68  ///
69  X863DNowEnum X863DNowLevel;
70
71  /// HasCMov - True if this processor has conditional move instructions
72  /// (generally pentium pro+).
73  bool HasCMov;
74
75  /// HasX86_64 - True if the processor supports X86-64 instructions.
76  ///
77  bool HasX86_64;
78
79  /// HasPOPCNT - True if the processor supports POPCNT.
80  bool HasPOPCNT;
81
82  /// HasSSE4A - True if the processor supports SSE4A instructions.
83  bool HasSSE4A;
84
85  /// HasAES - Target has AES instructions
86  bool HasAES;
87
88  /// HasCLMUL - Target has carry-less multiplication
89  bool HasCLMUL;
90
91  /// HasFMA3 - Target has 3-operand fused multiply-add
92  bool HasFMA3;
93
94  /// HasFMA4 - Target has 4-operand fused multiply-add
95  bool HasFMA4;
96
97  /// HasXOP - Target has XOP instructions
98  bool HasXOP;
99
100  /// HasMOVBE - True if the processor has the MOVBE instruction.
101  bool HasMOVBE;
102
103  /// HasRDRAND - True if the processor has the RDRAND instruction.
104  bool HasRDRAND;
105
106  /// HasF16C - Processor has 16-bit floating point conversion instructions.
107  bool HasF16C;
108
109  /// HasFSGSBase - Processor has FS/GS base insturctions.
110  bool HasFSGSBase;
111
112  /// HasLZCNT - Processor has LZCNT instruction.
113  bool HasLZCNT;
114
115  /// HasBMI - Processor has BMI1 instructions.
116  bool HasBMI;
117
118  /// HasBMI2 - Processor has BMI2 instructions.
119  bool HasBMI2;
120
121  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
122  bool IsBTMemSlow;
123
124  /// IsUAMemFast - True if unaligned memory access is fast.
125  bool IsUAMemFast;
126
127  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
128  /// operands. This may require setting a feature bit in the processor.
129  bool HasVectorUAMem;
130
131  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
132  /// this is true for most x86-64 chips, but not the first AMD chips.
133  bool HasCmpxchg16b;
134
135  /// PostRAScheduler - True if using post-register-allocation scheduler.
136  bool PostRAScheduler;
137
138  /// stackAlignment - The minimum alignment known to hold of the stack frame on
139  /// entry to the function and which must be maintained by every function.
140  unsigned stackAlignment;
141
142  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
143  ///
144  unsigned MaxInlineSizeThreshold;
145
146  /// TargetTriple - What processor and OS we're targeting.
147  Triple TargetTriple;
148
149  /// Instruction itineraries for scheduling
150  InstrItineraryData InstrItins;
151
152private:
153  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
154  bool In64BitMode;
155
156public:
157
158  /// This constructor initializes the data members to match that
159  /// of the specified triple.
160  ///
161  X86Subtarget(const std::string &TT, const std::string &CPU,
162               const std::string &FS,
163               unsigned StackAlignOverride, bool is64Bit);
164
165  /// getStackAlignment - Returns the minimum alignment known to hold of the
166  /// stack frame on entry to the function and which must be maintained by every
167  /// function for this subtarget.
168  unsigned getStackAlignment() const { return stackAlignment; }
169
170  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
171  /// that still makes it profitable to inline the call.
172  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
173
174  /// ParseSubtargetFeatures - Parses features string setting specified
175  /// subtarget options.  Definition of function is auto generated by tblgen.
176  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
177
178  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
179  /// instruction.
180  void AutoDetectSubtargetFeatures();
181
182  bool is64Bit() const { return In64BitMode; }
183
184  PICStyles::Style getPICStyle() const { return PICStyle; }
185  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
186
187  bool hasCMov() const { return HasCMov; }
188  bool hasMMX() const { return X86SSELevel >= MMX; }
189  bool hasSSE1() const { return X86SSELevel >= SSE1; }
190  bool hasSSE2() const { return X86SSELevel >= SSE2; }
191  bool hasSSE3() const { return X86SSELevel >= SSE3; }
192  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
193  bool hasSSE41() const { return X86SSELevel >= SSE41; }
194  bool hasSSE42() const { return X86SSELevel >= SSE42; }
195  bool hasAVX() const { return X86SSELevel >= AVX; }
196  bool hasAVX2() const { return X86SSELevel >= AVX2; }
197  bool hasSSE4A() const { return HasSSE4A; }
198  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
199  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
200  bool hasPOPCNT() const { return HasPOPCNT; }
201  bool hasAES() const { return HasAES; }
202  bool hasCLMUL() const { return HasCLMUL; }
203  bool hasFMA3() const { return HasFMA3; }
204  bool hasFMA4() const { return HasFMA4; }
205  bool hasXOP() const { return HasXOP; }
206  bool hasMOVBE() const { return HasMOVBE; }
207  bool hasRDRAND() const { return HasRDRAND; }
208  bool hasF16C() const { return HasF16C; }
209  bool hasFSGSBase() const { return HasFSGSBase; }
210  bool hasLZCNT() const { return HasLZCNT; }
211  bool hasBMI() const { return HasBMI; }
212  bool hasBMI2() const { return HasBMI2; }
213  bool isBTMemSlow() const { return IsBTMemSlow; }
214  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
215  bool hasVectorUAMem() const { return HasVectorUAMem; }
216  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
217
218  bool isAtom() const { return X86ProcFamily == IntelAtom; }
219
220  const Triple &getTargetTriple() const { return TargetTriple; }
221
222  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
223  bool isTargetFreeBSD() const {
224    return TargetTriple.getOS() == Triple::FreeBSD;
225  }
226  bool isTargetSolaris() const {
227    return TargetTriple.getOS() == Triple::Solaris;
228  }
229
230  // ELF is a reasonably sane default and the only other X86 targets we
231  // support are Darwin and Windows. Just use "not those".
232  bool isTargetELF() const {
233    return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
234  }
235  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
236  bool isTargetNaCl() const {
237    return TargetTriple.getOS() == Triple::NativeClient;
238  }
239  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
240  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
241
242  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
243  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
244  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
245  bool isTargetCygMing() const {
246    return isTargetMingw() || isTargetCygwin();
247  }
248
249  /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
250  bool isTargetCOFF() const {
251    return isTargetMingw() || isTargetCygwin() || isTargetWindows();
252  }
253
254  bool isTargetWin64() const {
255    // FIXME: x86_64-cygwin has not been released yet.
256    return In64BitMode && (isTargetCygMing() || isTargetWindows());
257  }
258
259  bool isTargetEnvMacho() const {
260    return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
261  }
262
263  bool isTargetWin32() const {
264    return !In64BitMode && (isTargetMingw() || isTargetWindows());
265  }
266
267  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
268  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
269  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
270
271  bool isPICStyleStubPIC() const {
272    return PICStyle == PICStyles::StubPIC;
273  }
274
275  bool isPICStyleStubNoDynamic() const {
276    return PICStyle == PICStyles::StubDynamicNoPIC;
277  }
278  bool isPICStyleStubAny() const {
279    return PICStyle == PICStyles::StubDynamicNoPIC ||
280           PICStyle == PICStyles::StubPIC; }
281
282  /// ClassifyGlobalReference - Classify a global variable reference for the
283  /// current subtarget according to how we should reference it in a non-pcrel
284  /// context.
285  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
286                                        const TargetMachine &TM)const;
287
288  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
289  /// current subtarget according to how we should reference it in a non-pcrel
290  /// context.
291  unsigned char ClassifyBlockAddressReference() const;
292
293  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
294  /// to immediate address.
295  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
296
297  /// This function returns the name of a function which has an interface
298  /// like the non-standard bzero function, if such a function exists on
299  /// the current subtarget and it is considered prefereable over
300  /// memset with zero passed as the second argument. Otherwise it
301  /// returns null.
302  const char *getBZeroEntry() const;
303
304  /// getSpecialAddressLatency - For targets where it is beneficial to
305  /// backschedule instructions that compute addresses, return a value
306  /// indicating the number of scheduling cycles of backscheduling that
307  /// should be attempted.
308  unsigned getSpecialAddressLatency() const;
309
310  /// enablePostRAScheduler - run for Atom optimization.
311  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
312                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
313                             RegClassVector& CriticalPathRCs) const;
314
315  /// getInstrItins = Return the instruction itineraries based on the
316  /// subtarget selection.
317  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
318};
319
320} // End llvm namespace
321
322#endif
323