X86Subtarget.h revision b2b5dc642cbbe781f73b9da83874d4005c50bd8e 
1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/IR/CallingConv.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  enum X86ProcFamilyEnum {
53    Others, IntelAtom
54  };
55
56  /// X86ProcFamily - X86 processor family: Intel Atom, and others
57  X86ProcFamilyEnum X86ProcFamily;
58
59  /// PICStyle - Which PIC style to use
60  ///
61  PICStyles::Style PICStyle;
62
63  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
64  /// none supported.
65  X86SSEEnum X86SSELevel;
66
67  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
68  ///
69  X863DNowEnum X863DNowLevel;
70
71  /// HasCMov - True if this processor has conditional move instructions
72  /// (generally pentium pro+).
73  bool HasCMov;
74
75  /// HasX86_64 - True if the processor supports X86-64 instructions.
76  ///
77  bool HasX86_64;
78
79  /// HasPOPCNT - True if the processor supports POPCNT.
80  bool HasPOPCNT;
81
82  /// HasSSE4A - True if the processor supports SSE4A instructions.
83  bool HasSSE4A;
84
85  /// HasAES - Target has AES instructions
86  bool HasAES;
87
88  /// HasPCLMUL - Target has carry-less multiplication
89  bool HasPCLMUL;
90
91  /// HasFMA - Target has 3-operand fused multiply-add
92  bool HasFMA;
93
94  /// HasFMA4 - Target has 4-operand fused multiply-add
95  bool HasFMA4;
96
97  /// HasXOP - Target has XOP instructions
98  bool HasXOP;
99
100  /// HasMOVBE - True if the processor has the MOVBE instruction.
101  bool HasMOVBE;
102
103  /// HasRDRAND - True if the processor has the RDRAND instruction.
104  bool HasRDRAND;
105
106  /// HasF16C - Processor has 16-bit floating point conversion instructions.
107  bool HasF16C;
108
109  /// HasFSGSBase - Processor has FS/GS base insturctions.
110  bool HasFSGSBase;
111
112  /// HasLZCNT - Processor has LZCNT instruction.
113  bool HasLZCNT;
114
115  /// HasBMI - Processor has BMI1 instructions.
116  bool HasBMI;
117
118  /// HasBMI2 - Processor has BMI2 instructions.
119  bool HasBMI2;
120
121  /// HasRTM - Processor has RTM instructions.
122  bool HasRTM;
123
124  /// HasHLE - Processor has HLE.
125  bool HasHLE;
126
127  /// HasADX - Processor has ADX instructions.
128  bool HasADX;
129
130  /// HasPRFCHW - Processor has PRFCHW instructions.
131  bool HasPRFCHW;
132
133  /// HasRDSEED - Processor has RDSEED instructions.
134  bool HasRDSEED;
135
136  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
137  bool IsBTMemSlow;
138
139  /// IsUAMemFast - True if unaligned memory access is fast.
140  bool IsUAMemFast;
141
142  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
143  /// operands. This may require setting a feature bit in the processor.
144  bool HasVectorUAMem;
145
146  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
147  /// this is true for most x86-64 chips, but not the first AMD chips.
148  bool HasCmpxchg16b;
149
150  /// UseLeaForSP - True if the LEA instruction should be used for adjusting
151  /// the stack pointer. This is an optimization for Intel Atom processors.
152  bool UseLeaForSP;
153
154  /// HasSlowDivide - True if smaller divides are significantly faster than
155  /// full divides and should be used when possible.
156  bool HasSlowDivide;
157
158  /// PostRAScheduler - True if using post-register-allocation scheduler.
159  bool PostRAScheduler;
160
161  /// PadShortFunctions - True if the short functions should be padded to prevent
162  /// a stall when returning too early.
163  bool PadShortFunctions;
164
165  /// CallRegIndirect - True if the Calls with memory reference should be converted
166  /// to a register-based indirect call.
167  bool CallRegIndirect;
168  /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
169  ///             address generation (AG) time.
170  bool LEAUsesAG;
171
172  /// stackAlignment - The minimum alignment known to hold of the stack frame on
173  /// entry to the function and which must be maintained by every function.
174  unsigned stackAlignment;
175
176  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
177  ///
178  unsigned MaxInlineSizeThreshold;
179
180  /// TargetTriple - What processor and OS we're targeting.
181  Triple TargetTriple;
182
183  /// Instruction itineraries for scheduling
184  InstrItineraryData InstrItins;
185
186private:
187  /// StackAlignOverride - Override the stack alignment.
188  unsigned StackAlignOverride;
189
190  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
191  bool In64BitMode;
192
193public:
194  /// This constructor initializes the data members to match that
195  /// of the specified triple.
196  ///
197  X86Subtarget(const std::string &TT, const std::string &CPU,
198               const std::string &FS,
199               unsigned StackAlignOverride, bool is64Bit);
200
201  /// getStackAlignment - Returns the minimum alignment known to hold of the
202  /// stack frame on entry to the function and which must be maintained by every
203  /// function for this subtarget.
204  unsigned getStackAlignment() const { return stackAlignment; }
205
206  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
207  /// that still makes it profitable to inline the call.
208  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
209
210  /// ParseSubtargetFeatures - Parses features string setting specified
211  /// subtarget options.  Definition of function is auto generated by tblgen.
212  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
213
214  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
215  /// instruction.
216  void AutoDetectSubtargetFeatures();
217
218  /// \brief Reset the features for the X86 target.
219  virtual void resetSubtargetFeatures(const MachineFunction *MF);
220private:
221  void initializeEnvironment();
222  void resetSubtargetFeatures(StringRef CPU, StringRef FS);
223public:
224  /// Is this x86_64? (disregarding specific ABI / programming model)
225  bool is64Bit() const {
226    return In64BitMode;
227  }
228
229  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
230  bool isTarget64BitILP32() const {
231    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
232  }
233
234  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
235  bool isTarget64BitLP64() const {
236    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
237  }
238
239  PICStyles::Style getPICStyle() const { return PICStyle; }
240  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
241
242  bool hasCMov() const { return HasCMov; }
243  bool hasMMX() const { return X86SSELevel >= MMX; }
244  bool hasSSE1() const { return X86SSELevel >= SSE1; }
245  bool hasSSE2() const { return X86SSELevel >= SSE2; }
246  bool hasSSE3() const { return X86SSELevel >= SSE3; }
247  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
248  bool hasSSE41() const { return X86SSELevel >= SSE41; }
249  bool hasSSE42() const { return X86SSELevel >= SSE42; }
250  bool hasAVX() const { return X86SSELevel >= AVX; }
251  bool hasAVX2() const { return X86SSELevel >= AVX2; }
252  bool hasFp256() const { return hasAVX(); }
253  bool hasInt256() const { return hasAVX2(); }
254  bool hasSSE4A() const { return HasSSE4A; }
255  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
256  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
257  bool hasPOPCNT() const { return HasPOPCNT; }
258  bool hasAES() const { return HasAES; }
259  bool hasPCLMUL() const { return HasPCLMUL; }
260  bool hasFMA() const { return HasFMA; }
261  // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
262  bool hasFMA4() const { return HasFMA4 && !HasFMA; }
263  bool hasXOP() const { return HasXOP; }
264  bool hasMOVBE() const { return HasMOVBE; }
265  bool hasRDRAND() const { return HasRDRAND; }
266  bool hasF16C() const { return HasF16C; }
267  bool hasFSGSBase() const { return HasFSGSBase; }
268  bool hasLZCNT() const { return HasLZCNT; }
269  bool hasBMI() const { return HasBMI; }
270  bool hasBMI2() const { return HasBMI2; }
271  bool hasRTM() const { return HasRTM; }
272  bool hasHLE() const { return HasHLE; }
273  bool hasADX() const { return HasADX; }
274  bool hasPRFCHW() const { return HasPRFCHW; }
275  bool hasRDSEED() const { return HasRDSEED; }
276  bool isBTMemSlow() const { return IsBTMemSlow; }
277  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
278  bool hasVectorUAMem() const { return HasVectorUAMem; }
279  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
280  bool useLeaForSP() const { return UseLeaForSP; }
281  bool hasSlowDivide() const { return HasSlowDivide; }
282  bool padShortFunctions() const { return PadShortFunctions; }
283  bool callRegIndirect() const { return CallRegIndirect; }
284  bool LEAusesAG() const { return LEAUsesAG; }
285
286  bool isAtom() const { return X86ProcFamily == IntelAtom; }
287
288  const Triple &getTargetTriple() const { return TargetTriple; }
289
290  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
291  bool isTargetFreeBSD() const {
292    return TargetTriple.getOS() == Triple::FreeBSD;
293  }
294  bool isTargetSolaris() const {
295    return TargetTriple.getOS() == Triple::Solaris;
296  }
297  bool isTargetELF() const {
298    return (TargetTriple.getEnvironment() == Triple::ELF ||
299            TargetTriple.isOSBinFormatELF());
300  }
301  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
302  bool isTargetNaCl() const {
303    return TargetTriple.getOS() == Triple::NaCl;
304  }
305  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
306  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
307  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
308  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
309  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
310  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
311  bool isTargetCOFF() const {
312    return (TargetTriple.getEnvironment() != Triple::ELF &&
313            TargetTriple.isOSBinFormatCOFF());
314  }
315  bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
316
317  bool isTargetWin64() const {
318    // FIXME: x86_64-cygwin has not been released yet.
319    return In64BitMode && TargetTriple.isOSWindows();
320  }
321
322  bool isTargetWin32() const {
323    // FIXME: Cygwin is included for isTargetWin64 -- should it be included
324    // here too?
325    return !In64BitMode && (isTargetMingw() || isTargetWindows());
326  }
327
328  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
329  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
330  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
331
332  bool isPICStyleStubPIC() const {
333    return PICStyle == PICStyles::StubPIC;
334  }
335
336  bool isPICStyleStubNoDynamic() const {
337    return PICStyle == PICStyles::StubDynamicNoPIC;
338  }
339  bool isPICStyleStubAny() const {
340    return PICStyle == PICStyles::StubDynamicNoPIC ||
341           PICStyle == PICStyles::StubPIC; }
342
343  /// ClassifyGlobalReference - Classify a global variable reference for the
344  /// current subtarget according to how we should reference it in a non-pcrel
345  /// context.
346  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
347                                        const TargetMachine &TM)const;
348
349  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
350  /// current subtarget according to how we should reference it in a non-pcrel
351  /// context.
352  unsigned char ClassifyBlockAddressReference() const;
353
354  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
355  /// to immediate address.
356  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
357
358  /// This function returns the name of a function which has an interface
359  /// like the non-standard bzero function, if such a function exists on
360  /// the current subtarget and it is considered prefereable over
361  /// memset with zero passed as the second argument. Otherwise it
362  /// returns null.
363  const char *getBZeroEntry() const;
364
365  /// This function returns true if the target has sincos() routine in its
366  /// compiler runtime or math libraries.
367  bool hasSinCos() const;
368
369  /// enablePostRAScheduler - run for Atom optimization.
370  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
371                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
372                             RegClassVector& CriticalPathRCs) const;
373
374  bool postRAScheduler() const { return PostRAScheduler; }
375
376  /// getInstrItins = Return the instruction itineraries based on the
377  /// subtarget selection.
378  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
379};
380
381} // End llvm namespace
382
383#endif
384