X86Subtarget.h revision c6d59954d8b4bc63aa8e6333d902a3fffc774189 
1//=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/CallingConv.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  /// PICStyle - Which PIC style to use
53  ///
54  PICStyles::Style PICStyle;
55
56  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
57  /// none supported.
58  X86SSEEnum X86SSELevel;
59
60  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
61  ///
62  X863DNowEnum X863DNowLevel;
63
64  /// HasCMov - True if this processor has conditional move instructions
65  /// (generally pentium pro+).
66  bool HasCMov;
67
68  /// HasX86_64 - True if the processor supports X86-64 instructions.
69  ///
70  bool HasX86_64;
71
72  /// HasPOPCNT - True if the processor supports POPCNT.
73  bool HasPOPCNT;
74
75  /// HasSSE4A - True if the processor supports SSE4A instructions.
76  bool HasSSE4A;
77
78  /// HasAES - Target has AES instructions
79  bool HasAES;
80
81  /// HasCLMUL - Target has carry-less multiplication
82  bool HasCLMUL;
83
84  /// HasFMA3 - Target has 3-operand fused multiply-add
85  bool HasFMA3;
86
87  /// HasFMA4 - Target has 4-operand fused multiply-add
88  bool HasFMA4;
89
90  /// HasXOP - Target has XOP instructions
91  bool HasXOP;
92
93  /// HasMOVBE - True if the processor has the MOVBE instruction.
94  bool HasMOVBE;
95
96  /// HasRDRAND - True if the processor has the RDRAND instruction.
97  bool HasRDRAND;
98
99  /// HasF16C - Processor has 16-bit floating point conversion instructions.
100  bool HasF16C;
101
102  /// HasFSGSBase - Processor has FS/GS base insturctions.
103  bool HasFSGSBase;
104
105  /// HasLZCNT - Processor has LZCNT instruction.
106  bool HasLZCNT;
107
108  /// HasBMI - Processor has BMI1 instructions.
109  bool HasBMI;
110
111  /// HasBMI2 - Processor has BMI2 instructions.
112  bool HasBMI2;
113
114  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
115  bool IsBTMemSlow;
116
117  /// IsUAMemFast - True if unaligned memory access is fast.
118  bool IsUAMemFast;
119
120  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
121  /// operands. This may require setting a feature bit in the processor.
122  bool HasVectorUAMem;
123
124  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
125  /// this is true for most x86-64 chips, but not the first AMD chips.
126  bool HasCmpxchg16b;
127
128  /// stackAlignment - The minimum alignment known to hold of the stack frame on
129  /// entry to the function and which must be maintained by every function.
130  unsigned stackAlignment;
131
132  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
133  ///
134  unsigned MaxInlineSizeThreshold;
135
136  /// TargetTriple - What processor and OS we're targeting.
137  Triple TargetTriple;
138
139private:
140  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
141  bool In64BitMode;
142
143public:
144
145  /// This constructor initializes the data members to match that
146  /// of the specified triple.
147  ///
148  X86Subtarget(const std::string &TT, const std::string &CPU,
149               const std::string &FS,
150               unsigned StackAlignOverride, bool is64Bit);
151
152  /// getStackAlignment - Returns the minimum alignment known to hold of the
153  /// stack frame on entry to the function and which must be maintained by every
154  /// function for this subtarget.
155  unsigned getStackAlignment() const { return stackAlignment; }
156
157  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
158  /// that still makes it profitable to inline the call.
159  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
160
161  /// ParseSubtargetFeatures - Parses features string setting specified
162  /// subtarget options.  Definition of function is auto generated by tblgen.
163  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
164
165  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
166  /// instruction.
167  void AutoDetectSubtargetFeatures();
168
169  bool is64Bit() const { return In64BitMode; }
170
171  PICStyles::Style getPICStyle() const { return PICStyle; }
172  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
173
174  bool hasCMov() const { return HasCMov; }
175  bool hasMMX() const { return X86SSELevel >= MMX; }
176  bool hasSSE1() const { return X86SSELevel >= SSE1; }
177  bool hasSSE2() const { return X86SSELevel >= SSE2; }
178  bool hasSSE3() const { return X86SSELevel >= SSE3; }
179  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
180  bool hasSSE41() const { return X86SSELevel >= SSE41; }
181  bool hasSSE42() const { return X86SSELevel >= SSE42; }
182  bool hasSSE4A() const { return HasSSE4A; }
183  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
184  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
185  bool hasPOPCNT() const { return HasPOPCNT; }
186  bool hasAVX() const { return X86SSELevel >= AVX; }
187  bool hasAVX2() const { return X86SSELevel >= AVX2; }
188  bool hasXMM() const { return X86SSELevel >= SSE1; }
189  bool hasXMMInt() const { return X86SSELevel >= SSE2; }
190  bool hasSSE3orAVX() const { return X86SSELevel >= SSE3; }
191  bool hasSSSE3orAVX() const { return X86SSELevel >= SSSE3; }
192  bool hasSSE41orAVX() const { return X86SSELevel >= SSE41; }
193  bool hasSSE42orAVX() const { return X86SSELevel >= SSE42; }
194  bool hasAES() const { return HasAES; }
195  bool hasCLMUL() const { return HasCLMUL; }
196  bool hasFMA3() const { return HasFMA3; }
197  bool hasFMA4() const { return HasFMA4; }
198  bool hasXOP() const { return HasXOP; }
199  bool hasMOVBE() const { return HasMOVBE; }
200  bool hasRDRAND() const { return HasRDRAND; }
201  bool hasF16C() const { return HasF16C; }
202  bool hasFSGSBase() const { return HasFSGSBase; }
203  bool hasLZCNT() const { return HasLZCNT; }
204  bool hasBMI() const { return HasBMI; }
205  bool hasBMI2() const { return HasBMI2; }
206  bool isBTMemSlow() const { return IsBTMemSlow; }
207  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
208  bool hasVectorUAMem() const { return HasVectorUAMem; }
209  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
210
211  const Triple &getTargetTriple() const { return TargetTriple; }
212
213  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
214  bool isTargetFreeBSD() const {
215    return TargetTriple.getOS() == Triple::FreeBSD;
216  }
217  bool isTargetSolaris() const {
218    return TargetTriple.getOS() == Triple::Solaris;
219  }
220
221  // ELF is a reasonably sane default and the only other X86 targets we
222  // support are Darwin and Windows. Just use "not those".
223  bool isTargetELF() const {
224    return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
225  }
226  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
227  bool isTargetNaCl() const {
228    return TargetTriple.getOS() == Triple::NativeClient;
229  }
230  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
231  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
232
233  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
234  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
235  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
236  bool isTargetCygMing() const {
237    return isTargetMingw() || isTargetCygwin();
238  }
239
240  /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
241  bool isTargetCOFF() const {
242    return isTargetMingw() || isTargetCygwin() || isTargetWindows();
243  }
244
245  bool isTargetWin64() const {
246    // FIXME: x86_64-cygwin has not been released yet.
247    return In64BitMode && (isTargetCygMing() || isTargetWindows());
248  }
249
250  bool isTargetEnvMacho() const {
251    return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
252  }
253
254  bool isTargetWin32() const {
255    return !In64BitMode && (isTargetMingw() || isTargetWindows());
256  }
257
258  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
259  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
260  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
261
262  bool isPICStyleStubPIC() const {
263    return PICStyle == PICStyles::StubPIC;
264  }
265
266  bool isPICStyleStubNoDynamic() const {
267    return PICStyle == PICStyles::StubDynamicNoPIC;
268  }
269  bool isPICStyleStubAny() const {
270    return PICStyle == PICStyles::StubDynamicNoPIC ||
271           PICStyle == PICStyles::StubPIC; }
272
273  /// ClassifyGlobalReference - Classify a global variable reference for the
274  /// current subtarget according to how we should reference it in a non-pcrel
275  /// context.
276  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
277                                        const TargetMachine &TM)const;
278
279  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
280  /// current subtarget according to how we should reference it in a non-pcrel
281  /// context.
282  unsigned char ClassifyBlockAddressReference() const;
283
284  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
285  /// to immediate address.
286  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
287
288  /// This function returns the name of a function which has an interface
289  /// like the non-standard bzero function, if such a function exists on
290  /// the current subtarget and it is considered prefereable over
291  /// memset with zero passed as the second argument. Otherwise it
292  /// returns null.
293  const char *getBZeroEntry() const;
294
295  /// getSpecialAddressLatency - For targets where it is beneficial to
296  /// backschedule instructions that compute addresses, return a value
297  /// indicating the number of scheduling cycles of backscheduling that
298  /// should be attempted.
299  unsigned getSpecialAddressLatency() const;
300};
301
302} // End llvm namespace
303
304#endif
305