X86Subtarget.h revision e7b05504faa86a5c0b80a62ddb60cbb0cf163d5d 
1//=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/CallingConv.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  /// PICStyle - Which PIC style to use
53  ///
54  PICStyles::Style PICStyle;
55
56  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
57  /// none supported.
58  X86SSEEnum X86SSELevel;
59
60  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
61  ///
62  X863DNowEnum X863DNowLevel;
63
64  /// HasCMov - True if this processor has conditional move instructions
65  /// (generally pentium pro+).
66  bool HasCMov;
67
68  /// HasX86_64 - True if the processor supports X86-64 instructions.
69  ///
70  bool HasX86_64;
71
72  /// HasPOPCNT - True if the processor supports POPCNT.
73  bool HasPOPCNT;
74
75  /// HasSSE4A - True if the processor supports SSE4A instructions.
76  bool HasSSE4A;
77
78  /// HasAVX - Target has AVX instructions
79  bool HasAVX;
80
81  /// HasAVX2 - Target has AVX2 instructions
82  bool HasAVX2;
83
84  /// HasAES - Target has AES instructions
85  bool HasAES;
86
87  /// HasCLMUL - Target has carry-less multiplication
88  bool HasCLMUL;
89
90  /// HasFMA3 - Target has 3-operand fused multiply-add
91  bool HasFMA3;
92
93  /// HasFMA4 - Target has 4-operand fused multiply-add
94  bool HasFMA4;
95
96  /// HasMOVBE - True if the processor has the MOVBE instruction.
97  bool HasMOVBE;
98
99  /// HasRDRAND - True if the processor has the RDRAND instruction.
100  bool HasRDRAND;
101
102  /// HasF16C - Processor has 16-bit floating point conversion instructions.
103  bool HasF16C;
104
105  /// HasFSGSBase - Processor has FS/GS base insturctions.
106  bool HasFSGSBase;
107
108  /// HasLZCNT - Processor has LZCNT instruction.
109  bool HasLZCNT;
110
111  /// HasBMI - Processor has BMI1 instructions.
112  bool HasBMI;
113
114  /// HasBMI2 - Processor has BMI2 instructions.
115  bool HasBMI2;
116
117  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
118  bool IsBTMemSlow;
119
120  /// IsUAMemFast - True if unaligned memory access is fast.
121  bool IsUAMemFast;
122
123  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
124  /// operands. This may require setting a feature bit in the processor.
125  bool HasVectorUAMem;
126
127  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
128  /// this is true for most x86-64 chips, but not the first AMD chips.
129  bool HasCmpxchg16b;
130
131  /// stackAlignment - The minimum alignment known to hold of the stack frame on
132  /// entry to the function and which must be maintained by every function.
133  unsigned stackAlignment;
134
135  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
136  ///
137  unsigned MaxInlineSizeThreshold;
138
139  /// TargetTriple - What processor and OS we're targeting.
140  Triple TargetTriple;
141
142private:
143  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
144  bool In64BitMode;
145
146public:
147
148  /// This constructor initializes the data members to match that
149  /// of the specified triple.
150  ///
151  X86Subtarget(const std::string &TT, const std::string &CPU,
152               const std::string &FS,
153               unsigned StackAlignOverride, bool is64Bit);
154
155  /// getStackAlignment - Returns the minimum alignment known to hold of the
156  /// stack frame on entry to the function and which must be maintained by every
157  /// function for this subtarget.
158  unsigned getStackAlignment() const { return stackAlignment; }
159
160  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
161  /// that still makes it profitable to inline the call.
162  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
163
164  /// ParseSubtargetFeatures - Parses features string setting specified
165  /// subtarget options.  Definition of function is auto generated by tblgen.
166  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
167
168  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
169  /// instruction.
170  void AutoDetectSubtargetFeatures();
171
172  bool is64Bit() const { return In64BitMode; }
173
174  PICStyles::Style getPICStyle() const { return PICStyle; }
175  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
176
177  bool hasCMov() const { return HasCMov; }
178  bool hasMMX() const { return X86SSELevel >= MMX; }
179  bool hasSSE1() const { return X86SSELevel >= SSE1; }
180  bool hasSSE2() const { return X86SSELevel >= SSE2; }
181  bool hasSSE3() const { return X86SSELevel >= SSE3; }
182  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
183  bool hasSSE41() const { return X86SSELevel >= SSE41; }
184  bool hasSSE42() const { return X86SSELevel >= SSE42; }
185  bool hasSSE4A() const { return HasSSE4A; }
186  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
187  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
188  bool hasPOPCNT() const { return HasPOPCNT; }
189  bool hasAVX() const { return HasAVX; }
190  bool hasAVX2() const { return HasAVX2; }
191  bool hasXMM() const { return hasSSE1() || hasAVX(); }
192  bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
193  bool hasAES() const { return HasAES; }
194  bool hasCLMUL() const { return HasCLMUL; }
195  bool hasFMA3() const { return HasFMA3; }
196  bool hasFMA4() const { return HasFMA4; }
197  bool hasMOVBE() const { return HasMOVBE; }
198  bool hasRDRAND() const { return HasRDRAND; }
199  bool hasF16C() const { return HasF16C; }
200  bool hasFSGSBase() const { return HasFSGSBase; }
201  bool hasLZCNT() const { return HasLZCNT; }
202  bool hasBMI() const { return HasBMI; }
203  bool hasBMI2() const { return HasBMI2; }
204  bool isBTMemSlow() const { return IsBTMemSlow; }
205  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
206  bool hasVectorUAMem() const { return HasVectorUAMem; }
207  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
208
209  const Triple &getTargetTriple() const { return TargetTriple; }
210
211  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
212  bool isTargetFreeBSD() const {
213    return TargetTriple.getOS() == Triple::FreeBSD;
214  }
215  bool isTargetSolaris() const {
216    return TargetTriple.getOS() == Triple::Solaris;
217  }
218
219  // ELF is a reasonably sane default and the only other X86 targets we
220  // support are Darwin and Windows. Just use "not those".
221  bool isTargetELF() const {
222    return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
223  }
224  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
225  bool isTargetNaCl() const {
226    return TargetTriple.getOS() == Triple::NativeClient;
227  }
228  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
229  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
230
231  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
232  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
233  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
234  bool isTargetCygMing() const {
235    return isTargetMingw() || isTargetCygwin();
236  }
237
238  /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
239  bool isTargetCOFF() const {
240    return isTargetMingw() || isTargetCygwin() || isTargetWindows();
241  }
242
243  bool isTargetWin64() const {
244    // FIXME: x86_64-cygwin has not been released yet.
245    return In64BitMode && (isTargetCygMing() || isTargetWindows());
246  }
247
248  bool isTargetEnvMacho() const {
249    return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
250  }
251
252  bool isTargetWin32() const {
253    return !In64BitMode && (isTargetMingw() || isTargetWindows());
254  }
255
256  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
257  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
258  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
259
260  bool isPICStyleStubPIC() const {
261    return PICStyle == PICStyles::StubPIC;
262  }
263
264  bool isPICStyleStubNoDynamic() const {
265    return PICStyle == PICStyles::StubDynamicNoPIC;
266  }
267  bool isPICStyleStubAny() const {
268    return PICStyle == PICStyles::StubDynamicNoPIC ||
269           PICStyle == PICStyles::StubPIC; }
270
271  /// ClassifyGlobalReference - Classify a global variable reference for the
272  /// current subtarget according to how we should reference it in a non-pcrel
273  /// context.
274  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
275                                        const TargetMachine &TM)const;
276
277  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
278  /// current subtarget according to how we should reference it in a non-pcrel
279  /// context.
280  unsigned char ClassifyBlockAddressReference() const;
281
282  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
283  /// to immediate address.
284  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
285
286  /// This function returns the name of a function which has an interface
287  /// like the non-standard bzero function, if such a function exists on
288  /// the current subtarget and it is considered prefereable over
289  /// memset with zero passed as the second argument. Otherwise it
290  /// returns null.
291  const char *getBZeroEntry() const;
292
293  /// getSpecialAddressLatency - For targets where it is beneficial to
294  /// backschedule instructions that compute addresses, return a value
295  /// indicating the number of scheduling cycles of backscheduling that
296  /// should be attempted.
297  unsigned getSpecialAddressLatency() const;
298};
299
300} // End llvm namespace
301
302#endif
303