XCoreRegisterInfo.cpp revision dac237e18209b697a8ba122d0ddd9cad4dfba1f8 
1//===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreRegisterInfo.h"
15#include "XCoreMachineFunctionInfo.h"
16#include "XCore.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/Target/TargetFrameInfo.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/Target/TargetInstrInfo.h"
28#include "llvm/Type.h"
29#include "llvm/Function.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35
36using namespace llvm;
37
38XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39  : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
40    TII(tii) {
41}
42
43// helper functions
44static inline bool isImmUs(unsigned val) {
45  return val <= 11;
46}
47
48static inline bool isImmU6(unsigned val) {
49  return val < (1 << 6);
50}
51
52static inline bool isImmU16(unsigned val) {
53  return val < (1 << 16);
54}
55
56static const unsigned XCore_ArgRegs[] = {
57  XCore::R0, XCore::R1, XCore::R2, XCore::R3
58};
59
60const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
61{
62  return XCore_ArgRegs;
63}
64
65unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
66{
67  return array_lengthof(XCore_ArgRegs);
68}
69
70bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF)
71{
72  const MachineFrameInfo *MFI = MF.getFrameInfo();
73  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
74  return (MMI && MMI->hasDebugInfo()) ||
75          !MF.getFunction()->doesNotThrow() ||
76          UnwindTablesMandatory;
77}
78
79const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
80                                                                         const {
81  static const unsigned CalleeSavedRegs[] = {
82    XCore::R4, XCore::R5, XCore::R6, XCore::R7,
83    XCore::R8, XCore::R9, XCore::R10, XCore::LR,
84    0
85  };
86  return CalleeSavedRegs;
87}
88
89const TargetRegisterClass* const*
90XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
91  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
92    XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
93    XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
94    XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
95    XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
96    0
97  };
98  return CalleeSavedRegClasses;
99}
100
101BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
102  BitVector Reserved(getNumRegs());
103  Reserved.set(XCore::CP);
104  Reserved.set(XCore::DP);
105  Reserved.set(XCore::SP);
106  Reserved.set(XCore::LR);
107  if (hasFP(MF)) {
108    Reserved.set(XCore::R10);
109  }
110  return Reserved;
111}
112
113bool
114XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
115  // TODO can we estimate stack size?
116  return hasFP(MF);
117}
118
119bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
120  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
121}
122
123// This function eliminates ADJCALLSTACKDOWN,
124// ADJCALLSTACKUP pseudo instructions
125void XCoreRegisterInfo::
126eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
127                              MachineBasicBlock::iterator I) const {
128  if (!hasReservedCallFrame(MF)) {
129    // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
130    // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
131    MachineInstr *Old = I;
132    uint64_t Amount = Old->getOperand(0).getImm();
133    if (Amount != 0) {
134      // We need to keep the stack aligned properly.  To do this, we round the
135      // amount of space needed for the outgoing arguments up to the next
136      // alignment boundary.
137      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
138      Amount = (Amount+Align-1)/Align*Align;
139
140      assert(Amount%4 == 0);
141      Amount /= 4;
142
143      bool isU6 = isImmU6(Amount);
144
145      if (!isU6 && !isImmU16(Amount)) {
146        // FIX could emit multiple instructions in this case.
147#ifndef NDEBUG
148        cerr << "eliminateCallFramePseudoInstr size too big: "
149             << Amount << "\n";
150#endif
151        llvm_unreachable();
152      }
153
154      MachineInstr *New;
155      if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
156        int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
157        New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
158          .addImm(Amount);
159      } else {
160        assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
161        int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
162        New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
163          .addImm(Amount);
164      }
165
166      // Replace the pseudo instruction with a new instruction...
167      MBB.insert(I, New);
168    }
169  }
170
171  MBB.erase(I);
172}
173
174void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
175                                            int SPAdj, RegScavenger *RS) const {
176  assert(SPAdj == 0 && "Unexpected");
177  MachineInstr &MI = *II;
178  DebugLoc dl = MI.getDebugLoc();
179  unsigned i = 0;
180
181  while (!MI.getOperand(i).isFI()) {
182    ++i;
183    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
184  }
185
186  MachineOperand &FrameOp = MI.getOperand(i);
187  int FrameIndex = FrameOp.getIndex();
188
189  MachineFunction &MF = *MI.getParent()->getParent();
190  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
191  int StackSize = MF.getFrameInfo()->getStackSize();
192
193  #ifndef NDEBUG
194  DOUT << "\nFunction         : " << MF.getFunction()->getName() << "\n";
195  DOUT << "<--------->\n";
196  MI.print(DOUT);
197  DOUT << "FrameIndex         : " << FrameIndex << "\n";
198  DOUT << "FrameOffset        : " << Offset << "\n";
199  DOUT << "StackSize          : " << StackSize << "\n";
200  #endif
201
202  Offset += StackSize;
203
204  // fold constant into offset.
205  Offset += MI.getOperand(i + 1).getImm();
206  MI.getOperand(i + 1).ChangeToImmediate(0);
207
208  assert(Offset%4 == 0 && "Misaligned stack offset");
209
210  #ifndef NDEBUG
211  DOUT << "Offset             : " << Offset << "\n";
212  DOUT << "<--------->\n";
213  #endif
214
215  Offset/=4;
216
217  bool FP = hasFP(MF);
218
219  unsigned Reg = MI.getOperand(0).getReg();
220  bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
221
222  assert(XCore::GRRegsRegisterClass->contains(Reg) &&
223         "Unexpected register operand");
224
225  MachineBasicBlock &MBB = *MI.getParent();
226
227  if (FP) {
228    bool isUs = isImmUs(Offset);
229    unsigned FramePtr = XCore::R10;
230
231    MachineInstr *New = 0;
232    if (!isUs) {
233      if (!RS) {
234        std::string msg;
235        raw_string_ostream Msg(msg);
236        Msg << "eliminateFrameIndex Frame size too big: " << Offset;
237        llvm_report_error(Msg.str());
238      }
239      unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
240                                                 SPAdj);
241      loadConstant(MBB, II, ScratchReg, Offset, dl);
242      switch (MI.getOpcode()) {
243      case XCore::LDWFI:
244        New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
245              .addReg(FramePtr)
246              .addReg(ScratchReg, RegState::Kill);
247        break;
248      case XCore::STWFI:
249        New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
250              .addReg(Reg, getKillRegState(isKill))
251              .addReg(FramePtr)
252              .addReg(ScratchReg, RegState::Kill);
253        break;
254      case XCore::LDAWFI:
255        New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
256              .addReg(FramePtr)
257              .addReg(ScratchReg, RegState::Kill);
258        break;
259      default:
260        assert(0 && "Unexpected Opcode\n");
261      }
262    } else {
263      switch (MI.getOpcode()) {
264      case XCore::LDWFI:
265        New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
266              .addReg(FramePtr)
267              .addImm(Offset);
268        break;
269      case XCore::STWFI:
270        New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
271              .addReg(Reg, getKillRegState(isKill))
272              .addReg(FramePtr)
273              .addImm(Offset);
274        break;
275      case XCore::LDAWFI:
276        New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
277              .addReg(FramePtr)
278              .addImm(Offset);
279        break;
280      default:
281        assert(0 && "Unexpected Opcode\n");
282      }
283    }
284  } else {
285    bool isU6 = isImmU6(Offset);
286    if (!isU6 && !isImmU16(Offset)) {
287      std::string msg;
288      raw_string_ostream Msg(msg);
289      Msg << "eliminateFrameIndex Frame size too big: " << Offset;
290      llvm_report_error(Msg.str());
291    }
292
293    switch (MI.getOpcode()) {
294    int NewOpcode;
295    case XCore::LDWFI:
296      NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
297      BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
298            .addImm(Offset);
299      break;
300    case XCore::STWFI:
301      NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
302      BuildMI(MBB, II, dl, TII.get(NewOpcode))
303            .addReg(Reg, getKillRegState(isKill))
304            .addImm(Offset);
305      break;
306    case XCore::LDAWFI:
307      NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
308      BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
309            .addImm(Offset);
310      break;
311    default:
312      assert(0 && "Unexpected Opcode\n");
313    }
314  }
315  // Erase old instruction.
316  MBB.erase(II);
317}
318
319void
320XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
321                                                      RegScavenger *RS) const {
322  MachineFrameInfo *MFI = MF.getFrameInfo();
323  bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
324  const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
325  XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
326  if (LRUsed) {
327    MF.getRegInfo().setPhysRegUnused(XCore::LR);
328
329    bool isVarArg = MF.getFunction()->isVarArg();
330    int FrameIdx;
331    if (! isVarArg) {
332      // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
333      FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0);
334    } else {
335      FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
336    }
337    XFI->setUsesLR(FrameIdx);
338    XFI->setLRSpillSlot(FrameIdx);
339  }
340  if (requiresRegisterScavenging(MF)) {
341    // Reserve a slot close to SP or frame pointer.
342    RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
343                                                RC->getAlignment()));
344  }
345  if (hasFP(MF)) {
346    // A callee save register is used to hold the FP.
347    // This needs saving / restoring in the epilogue / prologue.
348    XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
349                        RC->getAlignment()));
350  }
351}
352
353void XCoreRegisterInfo::
354processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
355
356}
357
358void XCoreRegisterInfo::
359loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
360            unsigned DstReg, int64_t Value, DebugLoc dl) const {
361  // TODO use mkmsk if possible.
362  if (!isImmU16(Value)) {
363    // TODO use constant pool.
364    std::string msg;
365    raw_string_ostream Msg(msg);
366    Msg << "loadConstant value too big " << Value;
367    llvm_report_error(Msg.str());
368  }
369  int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
370  BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
371}
372
373void XCoreRegisterInfo::
374storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
375                  unsigned SrcReg, int Offset, DebugLoc dl) const {
376  assert(Offset%4 == 0 && "Misaligned stack offset");
377  Offset/=4;
378  bool isU6 = isImmU6(Offset);
379  if (!isU6 && !isImmU16(Offset)) {
380    std::string msg;
381    raw_string_ostream Msg(msg);
382    Msg << "storeToStack offset too big " << Offset;
383    llvm_report_error(Msg.str());
384  }
385  int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
386  BuildMI(MBB, I, dl, TII.get(Opcode))
387    .addReg(SrcReg)
388    .addImm(Offset);
389}
390
391void XCoreRegisterInfo::
392loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
393                  unsigned DstReg, int Offset, DebugLoc dl) const {
394  assert(Offset%4 == 0 && "Misaligned stack offset");
395  Offset/=4;
396  bool isU6 = isImmU6(Offset);
397  if (!isU6 && !isImmU16(Offset)) {
398    std::string msg;
399    raw_string_ostream Msg(msg);
400    Msg << "loadFromStack offset too big " << Offset;
401    llvm_report_error(Msg.str());
402  }
403  int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
404  BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
405    .addImm(Offset);
406}
407
408void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
409  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
410  MachineBasicBlock::iterator MBBI = MBB.begin();
411  MachineFrameInfo *MFI = MF.getFrameInfo();
412  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
413  XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
414  DebugLoc dl = (MBBI != MBB.end() ?
415                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
416
417  bool FP = hasFP(MF);
418
419  // Work out frame sizes.
420  int FrameSize = MFI->getStackSize();
421
422  assert(FrameSize%4 == 0 && "Misaligned frame size");
423
424  FrameSize/=4;
425
426  bool isU6 = isImmU6(FrameSize);
427
428  if (!isU6 && !isImmU16(FrameSize)) {
429    // FIXME could emit multiple instructions.
430    std::string msg;
431    raw_string_ostream Msg(msg);
432    Msg << "emitPrologue Frame size too big: " << FrameSize;
433    llvm_report_error(Msg.str());
434  }
435  bool emitFrameMoves = needsFrameMoves(MF);
436
437  // Do we need to allocate space on the stack?
438  if (FrameSize) {
439    bool saveLR = XFI->getUsesLR();
440    bool LRSavedOnEntry = false;
441    int Opcode;
442    if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
443      Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
444      MBB.addLiveIn(XCore::LR);
445      saveLR = false;
446      LRSavedOnEntry = true;
447    } else {
448      Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
449    }
450    BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
451
452    if (emitFrameMoves) {
453      std::vector<MachineMove> &Moves = MMI->getFrameMoves();
454
455      // Show update of SP.
456      unsigned FrameLabelId = MMI->NextLabelID();
457      BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
458
459      MachineLocation SPDst(MachineLocation::VirtualFP);
460      MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
461      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
462
463      if (LRSavedOnEntry) {
464        MachineLocation CSDst(MachineLocation::VirtualFP, 0);
465        MachineLocation CSSrc(XCore::LR);
466        Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
467      }
468    }
469    if (saveLR) {
470      int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
471      storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
472      MBB.addLiveIn(XCore::LR);
473
474      if (emitFrameMoves) {
475        unsigned SaveLRLabelId = MMI->NextLabelID();
476        BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
477        MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
478        MachineLocation CSSrc(XCore::LR);
479        MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
480                                                   CSDst, CSSrc));
481      }
482    }
483  }
484
485  if (FP) {
486    // Save R10 to the stack.
487    int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
488    storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
489    // R10 is live-in. It is killed at the spill.
490    MBB.addLiveIn(XCore::R10);
491    if (emitFrameMoves) {
492      unsigned SaveR10LabelId = MMI->NextLabelID();
493      BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
494      MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
495      MachineLocation CSSrc(XCore::R10);
496      MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
497                                                 CSDst, CSSrc));
498    }
499    // Set the FP from the SP.
500    unsigned FramePtr = XCore::R10;
501    BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
502      .addImm(0);
503    if (emitFrameMoves) {
504      // Show FP is now valid.
505      unsigned FrameLabelId = MMI->NextLabelID();
506      BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
507      MachineLocation SPDst(FramePtr);
508      MachineLocation SPSrc(MachineLocation::VirtualFP);
509      MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
510    }
511  }
512
513  if (emitFrameMoves) {
514    // Frame moves for callee saved.
515    std::vector<MachineMove> &Moves = MMI->getFrameMoves();
516    std::vector<std::pair<unsigned, CalleeSavedInfo> >&SpillLabels =
517        XFI->getSpillLabels();
518    for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
519      unsigned SpillLabel = SpillLabels[I].first;
520      CalleeSavedInfo &CSI = SpillLabels[I].second;
521      int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
522      unsigned Reg = CSI.getReg();
523      MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
524      MachineLocation CSSrc(Reg);
525      Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
526    }
527  }
528}
529
530void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
531                                     MachineBasicBlock &MBB) const {
532  MachineFrameInfo *MFI            = MF.getFrameInfo();
533  MachineBasicBlock::iterator MBBI = prior(MBB.end());
534  DebugLoc dl = MBBI->getDebugLoc();
535
536  bool FP = hasFP(MF);
537
538  if (FP) {
539    // Restore the stack pointer.
540    unsigned FramePtr = XCore::R10;
541    BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
542      .addReg(FramePtr);
543  }
544
545  // Work out frame sizes.
546  int FrameSize = MFI->getStackSize();
547
548  assert(FrameSize%4 == 0 && "Misaligned frame size");
549
550  FrameSize/=4;
551
552  bool isU6 = isImmU6(FrameSize);
553
554  if (!isU6 && !isImmU16(FrameSize)) {
555    // FIXME could emit multiple instructions.
556    std::string msg;
557    raw_string_ostream Msg(msg);
558    Msg << "emitEpilogue Frame size too big: " << FrameSize;
559    llvm_report_error(Msg.str());
560  }
561
562  if (FrameSize) {
563    XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
564
565    if (FP) {
566      // Restore R10
567      int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
568      FPSpillOffset += FrameSize*4;
569      loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
570    }
571    bool restoreLR = XFI->getUsesLR();
572    if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
573      int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
574      LRSpillOffset += FrameSize*4;
575      loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
576      restoreLR = false;
577    }
578    if (restoreLR) {
579      // Fold prologue into return instruction
580      assert(MBBI->getOpcode() == XCore::RETSP_u6
581        || MBBI->getOpcode() == XCore::RETSP_lu6);
582      int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
583      BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
584      MBB.erase(MBBI);
585    } else {
586      int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
587      BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
588    }
589  }
590}
591
592int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
593  return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
594}
595
596unsigned XCoreRegisterInfo::getFrameRegister(MachineFunction &MF) const {
597  bool FP = hasFP(MF);
598
599  return FP ? XCore::R10 : XCore::SP;
600}
601
602unsigned XCoreRegisterInfo::getRARegister() const {
603  return XCore::LR;
604}
605
606void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
607                                                                         const {
608  // Initial state of the frame pointer is SP.
609  MachineLocation Dst(MachineLocation::VirtualFP);
610  MachineLocation Src(XCore::SP, 0);
611  Moves.push_back(MachineMove(0, Dst, Src));
612}
613
614#include "XCoreGenRegisterInfo.inc"
615
616