DAGISelMatcherGen.cpp revision 02f73585f7d018ea3ddcda88c8273ee4e5ea4de3
1//===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "DAGISelMatcher.h" 11#include "CodeGenDAGPatterns.h" 12#include "Record.h" 13#include "llvm/ADT/SmallVector.h" 14#include "llvm/ADT/StringMap.h" 15#include <utility> 16using namespace llvm; 17 18 19/// getRegisterValueType - Look up and return the ValueType of the specified 20/// register. If the register is a member of multiple register classes which 21/// have different associated types, return MVT::Other. 22static MVT::SimpleValueType getRegisterValueType(Record *R, 23 const CodeGenTarget &T) { 24 bool FoundRC = false; 25 MVT::SimpleValueType VT = MVT::Other; 26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses(); 27 std::vector<Record*>::const_iterator Element; 28 29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) { 30 const CodeGenRegisterClass &RC = RCs[rc]; 31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R)) 32 continue; 33 34 if (!FoundRC) { 35 FoundRC = true; 36 VT = RC.getValueTypeNum(0); 37 continue; 38 } 39 40 // In multiple RC's. If the Types of the RC's do not agree, return 41 // MVT::Other. The target is responsible for handling this. 42 if (VT != RC.getValueTypeNum(0)) 43 // FIXME2: when does this happen? Abort? 44 return MVT::Other; 45 } 46 return VT; 47} 48 49 50namespace { 51 class MatcherGen { 52 const PatternToMatch &Pattern; 53 const CodeGenDAGPatterns &CGP; 54 55 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts 56 /// out with all of the types removed. This allows us to insert type checks 57 /// as we scan the tree. 58 TreePatternNode *PatWithNoTypes; 59 60 /// VariableMap - A map from variable names ('$dst') to the recorded operand 61 /// number that they were captured as. These are biased by 1 to make 62 /// insertion easier. 63 StringMap<unsigned> VariableMap; 64 65 /// NextRecordedOperandNo - As we emit opcodes to record matched values in 66 /// the RecordedNodes array, this keeps track of which slot will be next to 67 /// record into. 68 unsigned NextRecordedOperandNo; 69 70 /// MatchedChainNodes - This maintains the position in the recorded nodes 71 /// array of all of the recorded input nodes that have chains. 72 SmallVector<unsigned, 2> MatchedChainNodes; 73 74 /// MatchedFlagResultNodes - This maintains the position in the recorded 75 /// nodes array of all of the recorded input nodes that have flag results. 76 SmallVector<unsigned, 2> MatchedFlagResultNodes; 77 78 /// PhysRegInputs - List list has an entry for each explicitly specified 79 /// physreg input to the pattern. The first elt is the Register node, the 80 /// second is the recorded slot number the input pattern match saved it in. 81 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs; 82 83 /// EmittedMergeInputChains - For nodes that match patterns involving 84 /// chains, is set to true if we emitted the "MergeInputChains" operation. 85 bool EmittedMergeInputChains; 86 87 /// Matcher - This is the top level of the generated matcher, the result. 88 MatcherNode *Matcher; 89 90 /// CurPredicate - As we emit matcher nodes, this points to the latest check 91 /// which should have future checks stuck into its Next position. 92 MatcherNode *CurPredicate; 93 public: 94 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp); 95 96 ~MatcherGen() { 97 delete PatWithNoTypes; 98 } 99 100 void EmitMatcherCode(); 101 void EmitResultCode(); 102 103 MatcherNode *GetMatcher() const { return Matcher; } 104 MatcherNode *GetCurPredicate() const { return CurPredicate; } 105 private: 106 void AddMatcherNode(MatcherNode *NewNode); 107 void InferPossibleTypes(); 108 109 // Matcher Generation. 110 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes); 111 void EmitLeafMatchCode(const TreePatternNode *N); 112 void EmitOperatorMatchCode(const TreePatternNode *N, 113 TreePatternNode *NodeNoTypes); 114 115 // Result Code Generation. 116 unsigned getNamedArgumentSlot(StringRef Name) { 117 unsigned VarMapEntry = VariableMap[Name]; 118 assert(VarMapEntry != 0 && 119 "Variable referenced but not defined and not caught earlier!"); 120 return VarMapEntry-1; 121 } 122 123 /// GetInstPatternNode - Get the pattern for an instruction. 124 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins, 125 const TreePatternNode *N); 126 127 void EmitResultOperand(const TreePatternNode *N, 128 SmallVectorImpl<unsigned> &ResultOps); 129 void EmitResultOfNamedOperand(const TreePatternNode *N, 130 SmallVectorImpl<unsigned> &ResultOps); 131 void EmitResultLeafAsOperand(const TreePatternNode *N, 132 SmallVectorImpl<unsigned> &ResultOps); 133 void EmitResultInstructionAsOperand(const TreePatternNode *N, 134 SmallVectorImpl<unsigned> &ResultOps); 135 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N, 136 SmallVectorImpl<unsigned> &ResultOps); 137 }; 138 139} // end anon namespace. 140 141MatcherGen::MatcherGen(const PatternToMatch &pattern, 142 const CodeGenDAGPatterns &cgp) 143: Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0), 144 EmittedMergeInputChains(false), Matcher(0), CurPredicate(0) { 145 // We need to produce the matcher tree for the patterns source pattern. To do 146 // this we need to match the structure as well as the types. To do the type 147 // matching, we want to figure out the fewest number of type checks we need to 148 // emit. For example, if there is only one integer type supported by a 149 // target, there should be no type comparisons at all for integer patterns! 150 // 151 // To figure out the fewest number of type checks needed, clone the pattern, 152 // remove the types, then perform type inference on the pattern as a whole. 153 // If there are unresolved types, emit an explicit check for those types, 154 // apply the type to the tree, then rerun type inference. Iterate until all 155 // types are resolved. 156 // 157 PatWithNoTypes = Pattern.getSrcPattern()->clone(); 158 PatWithNoTypes->RemoveAllTypes(); 159 160 // If there are types that are manifestly known, infer them. 161 InferPossibleTypes(); 162} 163 164/// InferPossibleTypes - As we emit the pattern, we end up generating type 165/// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we 166/// want to propagate implied types as far throughout the tree as possible so 167/// that we avoid doing redundant type checks. This does the type propagation. 168void MatcherGen::InferPossibleTypes() { 169 // TP - Get *SOME* tree pattern, we don't care which. It is only used for 170 // diagnostics, which we know are impossible at this point. 171 TreePattern &TP = *CGP.pf_begin()->second; 172 173 try { 174 bool MadeChange = true; 175 while (MadeChange) 176 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP, 177 true/*Ignore reg constraints*/); 178 } catch (...) { 179 errs() << "Type constraint application shouldn't fail!"; 180 abort(); 181 } 182} 183 184 185/// AddMatcherNode - Add a matcher node to the current graph we're building. 186void MatcherGen::AddMatcherNode(MatcherNode *NewNode) { 187 if (CurPredicate != 0) 188 CurPredicate->setNext(NewNode); 189 else 190 Matcher = NewNode; 191 CurPredicate = NewNode; 192} 193 194 195//===----------------------------------------------------------------------===// 196// Pattern Match Generation 197//===----------------------------------------------------------------------===// 198 199/// EmitLeafMatchCode - Generate matching code for leaf nodes. 200void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) { 201 assert(N->isLeaf() && "Not a leaf?"); 202 203 // If there are node predicates for this node, generate their checks. 204 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i) 205 AddMatcherNode(new CheckPredicateMatcherNode(N->getPredicateFns()[i])); 206 207 // Direct match against an integer constant. 208 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) 209 return AddMatcherNode(new CheckIntegerMatcherNode(II->getValue())); 210 211 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue()); 212 if (DI == 0) { 213 errs() << "Unknown leaf kind: " << *DI << "\n"; 214 abort(); 215 } 216 217 Record *LeafRec = DI->getDef(); 218 if (// Handle register references. Nothing to do here, they always match. 219 LeafRec->isSubClassOf("RegisterClass") || 220 LeafRec->isSubClassOf("PointerLikeRegClass") || 221 // Place holder for SRCVALUE nodes. Nothing to do here. 222 LeafRec->getName() == "srcvalue") 223 return; 224 225 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to 226 // record the register 227 if (LeafRec->isSubClassOf("Register")) { 228 AddMatcherNode(new RecordMatcherNode("physreg input "+LeafRec->getName())); 229 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++)); 230 return; 231 } 232 233 if (LeafRec->isSubClassOf("ValueType")) 234 return AddMatcherNode(new CheckValueTypeMatcherNode(LeafRec->getName())); 235 236 if (LeafRec->isSubClassOf("CondCode")) 237 return AddMatcherNode(new CheckCondCodeMatcherNode(LeafRec->getName())); 238 239 if (LeafRec->isSubClassOf("ComplexPattern")) { 240 // We can't model ComplexPattern uses that don't have their name taken yet. 241 // The OPC_CheckComplexPattern operation implicitly records the results. 242 if (N->getName().empty()) { 243 errs() << "We expect complex pattern uses to have names: " << *N << "\n"; 244 exit(1); 245 } 246 247 // Handle complex pattern. 248 const ComplexPattern &CP = CGP.getComplexPattern(LeafRec); 249 250 // If we're at the root of the pattern, we have to check that the opcode 251 // is a one of the ones requested to be matched. 252 if (N == Pattern.getSrcPattern()) { 253 const std::vector<Record*> &OpNodes = CP.getRootNodes(); 254 if (OpNodes.size() == 1) { 255 StringRef OpName = CGP.getSDNodeInfo(OpNodes[0]).getEnumName(); 256 AddMatcherNode(new CheckOpcodeMatcherNode(OpName)); 257 } else if (!OpNodes.empty()) { 258 SmallVector<StringRef, 4> OpNames; 259 for (unsigned i = 0, e = OpNodes.size(); i != e; i++) 260 OpNames.push_back(CGP.getSDNodeInfo(OpNodes[i]).getEnumName()); 261 AddMatcherNode(new CheckMultiOpcodeMatcherNode(OpNames.data(), 262 OpNames.size())); 263 } 264 } 265 266 // Emit a CheckComplexPat operation, which does the match (aborting if it 267 // fails) and pushes the matched operands onto the recorded nodes list. 268 AddMatcherNode(new CheckComplexPatMatcherNode(CP)); 269 270 // Record the right number of operands. 271 NextRecordedOperandNo += CP.getNumOperands(); 272 if (CP.hasProperty(SDNPHasChain)) 273 ++NextRecordedOperandNo; // Chained node operand. 274 275 // If the complex pattern has a chain, then we need to keep track of the 276 // fact that we just recorded a chain input. The chain input will be 277 // matched as the last operand of the predicate if it was successful. 278 if (CP.hasProperty(SDNPHasChain)) { 279 // It is the last operand recorded. 280 assert(NextRecordedOperandNo > 1 && 281 "Should have recorded input/result chains at least!"); 282 MatchedChainNodes.push_back(NextRecordedOperandNo-1); 283 284 // If we need to check chains, do so, see comment for 285 // "NodeHasProperty(SDNPHasChain" below. 286 if (MatchedChainNodes.size() > 1) { 287 // FIXME2: This is broken, we should eliminate this nonsense completely, 288 // but we want to produce the same selections that the old matcher does 289 // for now. 290 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2]; 291 AddMatcherNode(new CheckChainCompatibleMatcherNode(PrevOp)); 292 } 293 } 294 295 // TODO: Complex patterns can't have output flags, if they did, we'd want 296 // to record them. 297 return; 298 } 299 300 errs() << "Unknown leaf kind: " << *N << "\n"; 301 abort(); 302} 303 304void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N, 305 TreePatternNode *NodeNoTypes) { 306 assert(!N->isLeaf() && "Not an operator?"); 307 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator()); 308 309 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is 310 // a constant without a predicate fn that has more that one bit set, handle 311 // this as a special case. This is usually for targets that have special 312 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit 313 // handling stuff). Using these instructions is often far more efficient 314 // than materializing the constant. Unfortunately, both the instcombiner 315 // and the dag combiner can often infer that bits are dead, and thus drop 316 // them from the mask in the dag. For example, it might turn 'AND X, 255' 317 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks 318 // to handle this. 319 if ((N->getOperator()->getName() == "and" || 320 N->getOperator()->getName() == "or") && 321 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() && 322 N->getPredicateFns().empty()) { 323 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) { 324 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits. 325 if (N->getOperator()->getName() == "and") 326 AddMatcherNode(new CheckAndImmMatcherNode(II->getValue())); 327 else 328 AddMatcherNode(new CheckOrImmMatcherNode(II->getValue())); 329 330 // Match the LHS of the AND as appropriate. 331 AddMatcherNode(new MoveChildMatcherNode(0)); 332 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0)); 333 AddMatcherNode(new MoveParentMatcherNode()); 334 return; 335 } 336 } 337 } 338 339 // Check that the current opcode lines up. 340 AddMatcherNode(new CheckOpcodeMatcherNode(CInfo.getEnumName())); 341 342 // If there are node predicates for this node, generate their checks. 343 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i) 344 AddMatcherNode(new CheckPredicateMatcherNode(N->getPredicateFns()[i])); 345 346 347 // If this node has memory references (i.e. is a load or store), tell the 348 // interpreter to capture them in the memref array. 349 if (N->NodeHasProperty(SDNPMemOperand, CGP)) 350 AddMatcherNode(new RecordMemRefMatcherNode()); 351 352 // If this node has a chain, then the chain is operand #0 is the SDNode, and 353 // the child numbers of the node are all offset by one. 354 unsigned OpNo = 0; 355 if (N->NodeHasProperty(SDNPHasChain, CGP)) { 356 // Record the node and remember it in our chained nodes list. 357 AddMatcherNode(new RecordMatcherNode("'" + N->getOperator()->getName() + 358 "' chained node")); 359 // Remember all of the input chains our pattern will match. 360 MatchedChainNodes.push_back(NextRecordedOperandNo++); 361 362 // If this is the second (e.g. indbr(load) or store(add(load))) or third 363 // input chain (e.g. (store (add (load, load))) from msp430) we need to make 364 // sure that folding the chain won't induce cycles in the DAG. This could 365 // happen if there were an intermediate node between the indbr and load, for 366 // example. 367 if (MatchedChainNodes.size() > 1) { 368 // FIXME2: This is broken, we should eliminate this nonsense completely, 369 // but we want to produce the same selections that the old matcher does 370 // for now. 371 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2]; 372 AddMatcherNode(new CheckChainCompatibleMatcherNode(PrevOp)); 373 } 374 375 // Don't look at the input chain when matching the tree pattern to the 376 // SDNode. 377 OpNo = 1; 378 379 // If this node is not the root and the subtree underneath it produces a 380 // chain, then the result of matching the node is also produce a chain. 381 // Beyond that, this means that we're also folding (at least) the root node 382 // into the node that produce the chain (for example, matching 383 // "(add reg, (load ptr))" as a add_with_memory on X86). This is 384 // problematic, if the 'reg' node also uses the load (say, its chain). 385 // Graphically: 386 // 387 // [LD] 388 // ^ ^ 389 // | \ DAG's like cheese. 390 // / | 391 // / [YY] 392 // | ^ 393 // [XX]--/ 394 // 395 // It would be invalid to fold XX and LD. In this case, folding the two 396 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG' 397 // To prevent this, we emit a dynamic check for legality before allowing 398 // this to be folded. 399 // 400 const TreePatternNode *Root = Pattern.getSrcPattern(); 401 if (N != Root) { // Not the root of the pattern. 402 // If there is a node between the root and this node, then we definitely 403 // need to emit the check. 404 bool NeedCheck = !Root->hasChild(N); 405 406 // If it *is* an immediate child of the root, we can still need a check if 407 // the root SDNode has multiple inputs. For us, this means that it is an 408 // intrinsic, has multiple operands, or has other inputs like chain or 409 // flag). 410 if (!NeedCheck) { 411 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator()); 412 NeedCheck = 413 Root->getOperator() == CGP.get_intrinsic_void_sdnode() || 414 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() || 415 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() || 416 PInfo.getNumOperands() > 1 || 417 PInfo.hasProperty(SDNPHasChain) || 418 PInfo.hasProperty(SDNPInFlag) || 419 PInfo.hasProperty(SDNPOptInFlag); 420 } 421 422 if (NeedCheck) 423 AddMatcherNode(new CheckFoldableChainNodeMatcherNode()); 424 } 425 } 426 427 // If this node has an output flag and isn't the root, remember it. 428 if (N->NodeHasProperty(SDNPOutFlag, CGP) && 429 N != Pattern.getSrcPattern()) { 430 // TODO: This redundantly records nodes with both flags and chains. 431 432 // Record the node and remember it in our chained nodes list. 433 AddMatcherNode(new RecordMatcherNode("'" + N->getOperator()->getName() + 434 "' flag output node")); 435 // Remember all of the nodes with output flags our pattern will match. 436 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++); 437 } 438 439 // If this node is known to have an input flag or if it *might* have an input 440 // flag, capture it as the flag input of the pattern. 441 if (N->NodeHasProperty(SDNPOptInFlag, CGP) || 442 N->NodeHasProperty(SDNPInFlag, CGP)) 443 AddMatcherNode(new CaptureFlagInputMatcherNode()); 444 445 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) { 446 // Get the code suitable for matching this child. Move to the child, check 447 // it then move back to the parent. 448 AddMatcherNode(new MoveChildMatcherNode(OpNo)); 449 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i)); 450 AddMatcherNode(new MoveParentMatcherNode()); 451 } 452} 453 454 455void MatcherGen::EmitMatchCode(const TreePatternNode *N, 456 TreePatternNode *NodeNoTypes) { 457 // If N and NodeNoTypes don't agree on a type, then this is a case where we 458 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and 459 // reinfer any correlated types. 460 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) { 461 AddMatcherNode(new CheckTypeMatcherNode(N->getTypeNum(0))); 462 NodeNoTypes->setTypes(N->getExtTypes()); 463 InferPossibleTypes(); 464 } 465 466 // If this node has a name associated with it, capture it in VariableMap. If 467 // we already saw this in the pattern, emit code to verify dagness. 468 if (!N->getName().empty()) { 469 unsigned &VarMapEntry = VariableMap[N->getName()]; 470 if (VarMapEntry == 0) { 471 // If it is a named node, we must emit a 'Record' opcode. 472 VarMapEntry = ++NextRecordedOperandNo; 473 AddMatcherNode(new RecordMatcherNode("$" + N->getName())); 474 } else { 475 // If we get here, this is a second reference to a specific name. Since 476 // we already have checked that the first reference is valid, we don't 477 // have to recursively match it, just check that it's the same as the 478 // previously named thing. 479 AddMatcherNode(new CheckSameMatcherNode(VarMapEntry-1)); 480 return; 481 } 482 } 483 484 if (N->isLeaf()) 485 EmitLeafMatchCode(N); 486 else 487 EmitOperatorMatchCode(N, NodeNoTypes); 488} 489 490void MatcherGen::EmitMatcherCode() { 491 // If the pattern has a predicate on it (e.g. only enabled when a subtarget 492 // feature is around, do the check). 493 if (!Pattern.getPredicateCheck().empty()) 494 AddMatcherNode(new 495 CheckPatternPredicateMatcherNode(Pattern.getPredicateCheck())); 496 497 // Emit the matcher for the pattern structure and types. 498 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes); 499} 500 501 502//===----------------------------------------------------------------------===// 503// Node Result Generation 504//===----------------------------------------------------------------------===// 505 506void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N, 507 SmallVectorImpl<unsigned> &ResultOps){ 508 assert(!N->getName().empty() && "Operand not named!"); 509 510 unsigned SlotNo = getNamedArgumentSlot(N->getName()); 511 512 // A reference to a complex pattern gets all of the results of the complex 513 // pattern's match. 514 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) { 515 // The first slot entry is the node itself, the subsequent entries are the 516 // matched values. 517 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) 518 ResultOps.push_back(SlotNo+i+1); 519 return; 520 } 521 522 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target 523 // version of the immediate so that it doesn't get selected due to some other 524 // node use. 525 if (!N->isLeaf()) { 526 StringRef OperatorName = N->getOperator()->getName(); 527 if (OperatorName == "imm" || OperatorName == "fpimm") { 528 AddMatcherNode(new EmitConvertToTargetMatcherNode(SlotNo)); 529 ResultOps.push_back(NextRecordedOperandNo++); 530 return; 531 } 532 } 533 534 ResultOps.push_back(SlotNo); 535} 536 537void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N, 538 SmallVectorImpl<unsigned> &ResultOps) { 539 assert(N->isLeaf() && "Must be a leaf"); 540 541 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) { 542 AddMatcherNode(new EmitIntegerMatcherNode(II->getValue(),N->getTypeNum(0))); 543 ResultOps.push_back(NextRecordedOperandNo++); 544 return; 545 } 546 547 // If this is an explicit register reference, handle it. 548 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) { 549 if (DI->getDef()->isSubClassOf("Register")) { 550 AddMatcherNode(new EmitRegisterMatcherNode(DI->getDef(), 551 N->getTypeNum(0))); 552 ResultOps.push_back(NextRecordedOperandNo++); 553 return; 554 } 555 556 if (DI->getDef()->getName() == "zero_reg") { 557 AddMatcherNode(new EmitRegisterMatcherNode(0, N->getTypeNum(0))); 558 ResultOps.push_back(NextRecordedOperandNo++); 559 return; 560 } 561 562 // Handle a reference to a register class. This is used 563 // in COPY_TO_SUBREG instructions. 564 if (DI->getDef()->isSubClassOf("RegisterClass")) { 565 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID"; 566 AddMatcherNode(new EmitStringIntegerMatcherNode(Value, MVT::i32)); 567 ResultOps.push_back(NextRecordedOperandNo++); 568 return; 569 } 570 } 571 572 errs() << "unhandled leaf node: \n"; 573 N->dump(); 574} 575 576/// GetInstPatternNode - Get the pattern for an instruction. 577/// 578const TreePatternNode *MatcherGen:: 579GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) { 580 const TreePattern *InstPat = Inst.getPattern(); 581 582 // FIXME2?: Assume actual pattern comes before "implicit". 583 TreePatternNode *InstPatNode; 584 if (InstPat) 585 InstPatNode = InstPat->getTree(0); 586 else if (/*isRoot*/ N == Pattern.getDstPattern()) 587 InstPatNode = Pattern.getSrcPattern(); 588 else 589 return 0; 590 591 if (InstPatNode && !InstPatNode->isLeaf() && 592 InstPatNode->getOperator()->getName() == "set") 593 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1); 594 595 return InstPatNode; 596} 597 598void MatcherGen:: 599EmitResultInstructionAsOperand(const TreePatternNode *N, 600 SmallVectorImpl<unsigned> &OutputOps) { 601 Record *Op = N->getOperator(); 602 const CodeGenTarget &CGT = CGP.getTargetInfo(); 603 CodeGenInstruction &II = CGT.getInstruction(Op->getName()); 604 const DAGInstruction &Inst = CGP.getInstruction(Op); 605 606 // If we can, get the pattern for the instruction we're generating. We derive 607 // a variety of information from this pattern, such as whether it has a chain. 608 // 609 // FIXME2: This is extremely dubious for several reasons, not the least of 610 // which it gives special status to instructions with patterns that Pat<> 611 // nodes can't duplicate. 612 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N); 613 614 // NodeHasChain - Whether the instruction node we're creating takes chains. 615 bool NodeHasChain = InstPatNode && 616 InstPatNode->TreeHasProperty(SDNPHasChain, CGP); 617 618 bool isRoot = N == Pattern.getDstPattern(); 619 620 // TreeHasOutFlag - True if this tree has a flag. 621 bool TreeHasInFlag = false, TreeHasOutFlag = false; 622 if (isRoot) { 623 const TreePatternNode *SrcPat = Pattern.getSrcPattern(); 624 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) || 625 SrcPat->TreeHasProperty(SDNPInFlag, CGP); 626 627 // FIXME2: this is checking the entire pattern, not just the node in 628 // question, doing this just for the root seems like a total hack. 629 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP); 630 } 631 632 // NumResults - This is the number of results produced by the instruction in 633 // the "outs" list. 634 unsigned NumResults = Inst.getNumResults(); 635 636 // Loop over all of the operands of the instruction pattern, emitting code 637 // to fill them all in. The node 'N' usually has number children equal to 638 // the number of input operands of the instruction. However, in cases 639 // where there are predicate operands for an instruction, we need to fill 640 // in the 'execute always' values. Match up the node operands to the 641 // instruction operands to do this. 642 SmallVector<unsigned, 8> InstOps; 643 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size(); 644 InstOpNo != e; ++InstOpNo) { 645 646 // Determine what to emit for this operand. 647 Record *OperandNode = II.OperandList[InstOpNo].Rec; 648 if ((OperandNode->isSubClassOf("PredicateOperand") || 649 OperandNode->isSubClassOf("OptionalDefOperand")) && 650 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) { 651 // This is a predicate or optional def operand; emit the 652 // 'default ops' operands. 653 const DAGDefaultOperand &DefaultOp = 654 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec); 655 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i) 656 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps); 657 continue; 658 } 659 660 // Otherwise this is a normal operand or a predicate operand without 661 // 'execute always'; emit it. 662 EmitResultOperand(N->getChild(ChildNo), InstOps); 663 ++ChildNo; 664 } 665 666 // Nodes that match patterns with (potentially multiple) chain inputs have to 667 // merge them together into a token factor. 668 if (NodeHasChain && !EmittedMergeInputChains) { 669 // FIXME2: Move this out of emitresult to a top level place. 670 assert(!MatchedChainNodes.empty() && 671 "How can this node have chain if no inputs do?"); 672 // Otherwise, we have to emit an operation to merge the input chains and 673 // set this as the current input chain. 674 AddMatcherNode(new EmitMergeInputChainsMatcherNode 675 (MatchedChainNodes.data(), MatchedChainNodes.size())); 676 EmittedMergeInputChains = true; 677 } 678 679 // If this node has an input flag or explicitly specified input physregs, we 680 // need to add chained and flagged copyfromreg nodes and materialize the flag 681 // input. 682 if (isRoot && !PhysRegInputs.empty()) { 683 // Emit all of the CopyToReg nodes for the input physical registers. These 684 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src). 685 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i) 686 AddMatcherNode(new EmitCopyToRegMatcherNode(PhysRegInputs[i].second, 687 PhysRegInputs[i].first)); 688 // Even if the node has no other flag inputs, the resultant node must be 689 // flagged to the CopyFromReg nodes we just generated. 690 TreeHasInFlag = true; 691 } 692 693 // Result order: node results, chain, flags 694 695 // Determine the result types. 696 SmallVector<MVT::SimpleValueType, 4> ResultVTs; 697 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) { 698 // FIXME2: If the node has multiple results, we should add them. For now, 699 // preserve existing behavior?! 700 ResultVTs.push_back(N->getTypeNum(0)); 701 } 702 703 704 // If this is the root instruction of a pattern that has physical registers in 705 // its result pattern, add output VTs for them. For example, X86 has: 706 // (set AL, (mul ...)) 707 // This also handles implicit results like: 708 // (implicit EFLAGS) 709 if (isRoot && Pattern.getDstRegs().size() != 0) { 710 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) 711 if (Pattern.getDstRegs()[i]->isSubClassOf("Register")) 712 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT)); 713 } 714 if (NodeHasChain) 715 ResultVTs.push_back(MVT::Other); 716 if (TreeHasOutFlag) 717 ResultVTs.push_back(MVT::Flag); 718 719 // FIXME2: Instead of using the isVariadic flag on the instruction, we should 720 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic 721 // property should be inferred from this when an instruction has a pattern. 722 int NumFixedArityOperands = -1; 723 if (isRoot && II.isVariadic) 724 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren(); 725 726 // If this is the root node and any of the nodes matched nodes in the input 727 // pattern have MemRefs in them, have the interpreter collect them and plop 728 // them onto this node. 729 // 730 // FIXME3: This is actively incorrect for result patterns where the root of 731 // the pattern is not the memory reference and is also incorrect when the 732 // result pattern has multiple memory-referencing instructions. For example, 733 // in the X86 backend, this pattern causes the memrefs to get attached to the 734 // CVTSS2SDrr instead of the MOVSSrm: 735 // 736 // def : Pat<(extloadf32 addr:$src), 737 // (CVTSS2SDrr (MOVSSrm addr:$src))>; 738 // 739 bool NodeHasMemRefs = 740 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP); 741 742 // FIXME: Eventually add a SelectNodeTo form. It works if the new node has a 743 // superset of the results of the old node, in the same places. E.g. turning 744 // (add (load)) -> add32rm is ok because result #0 is the result and result #1 745 // is new. 746 AddMatcherNode(new EmitNodeMatcherNode(II.Namespace+"::"+II.TheDef->getName(), 747 ResultVTs.data(), ResultVTs.size(), 748 InstOps.data(), InstOps.size(), 749 NodeHasChain, TreeHasInFlag, 750 NodeHasMemRefs,NumFixedArityOperands)); 751 752 // The non-chain and non-flag results of the newly emitted node get recorded. 753 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) { 754 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break; 755 OutputOps.push_back(NextRecordedOperandNo++); 756 } 757 758 // FIXME2: Kill off all the SelectionDAG::SelectNodeTo and getMachineNode 759 // variants. Call MorphNodeTo instead of SelectNodeTo. 760} 761 762void MatcherGen:: 763EmitResultSDNodeXFormAsOperand(const TreePatternNode *N, 764 SmallVectorImpl<unsigned> &ResultOps) { 765 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?"); 766 767 // Emit the operand. 768 SmallVector<unsigned, 8> InputOps; 769 770 // FIXME2: Could easily generalize this to support multiple inputs and outputs 771 // to the SDNodeXForm. For now we just support one input and one output like 772 // the old instruction selector. 773 assert(N->getNumChildren() == 1); 774 EmitResultOperand(N->getChild(0), InputOps); 775 776 // The input currently must have produced exactly one result. 777 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm"); 778 779 AddMatcherNode(new EmitNodeXFormMatcherNode(InputOps[0], N->getOperator())); 780 ResultOps.push_back(NextRecordedOperandNo++); 781} 782 783void MatcherGen::EmitResultOperand(const TreePatternNode *N, 784 SmallVectorImpl<unsigned> &ResultOps) { 785 // This is something selected from the pattern we matched. 786 if (!N->getName().empty()) 787 return EmitResultOfNamedOperand(N, ResultOps); 788 789 if (N->isLeaf()) 790 return EmitResultLeafAsOperand(N, ResultOps); 791 792 Record *OpRec = N->getOperator(); 793 if (OpRec->isSubClassOf("Instruction")) 794 return EmitResultInstructionAsOperand(N, ResultOps); 795 if (OpRec->isSubClassOf("SDNodeXForm")) 796 return EmitResultSDNodeXFormAsOperand(N, ResultOps); 797 errs() << "Unknown result node to emit code for: " << *N << '\n'; 798 throw std::string("Unknown node in result pattern!"); 799} 800 801void MatcherGen::EmitResultCode() { 802 // Codegen the root of the result pattern, capturing the resulting values. 803 SmallVector<unsigned, 8> Ops; 804 EmitResultOperand(Pattern.getDstPattern(), Ops); 805 806 // At this point, we have however many values the result pattern produces. 807 // However, the input pattern might not need all of these. If there are 808 // excess values at the end (such as condition codes etc) just lop them off. 809 // This doesn't need to worry about flags or chains, just explicit results. 810 // 811 // FIXME2: This doesn't work because there is currently no way to get an 812 // accurate count of the # results the source pattern sets. This is because 813 // of the "parallel" construct in X86 land, which looks like this: 814 // 815 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2), 816 // (implicit EFLAGS)), 817 // (AND8rr GR8:$src1, GR8:$src2)>; 818 // 819 // This idiom means to match the two-result node X86and_flag (which is 820 // declared as returning a single result, because we can't match multi-result 821 // nodes yet). In this case, we would have to know that the input has two 822 // results. However, mul8r is modelled exactly the same way, but without 823 // implicit defs included. The fix is to support multiple results directly 824 // and eliminate 'parallel'. 825 // 826 // FIXME2: When this is fixed, we should revert the terrible hack in the 827 // OPC_EmitNode code in the interpreter. 828#if 0 829 const TreePatternNode *Src = Pattern.getSrcPattern(); 830 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0; 831 NumSrcResults += Pattern.getDstRegs().size(); 832 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results"); 833 Ops.resize(NumSrcResults); 834#endif 835 836 // If the matched pattern covers nodes which define a flag result, emit a node 837 // that tells the matcher about them so that it can update their results. 838 if (!MatchedFlagResultNodes.empty()) 839 AddMatcherNode(new MarkFlagResultsMatcherNode(MatchedFlagResultNodes.data(), 840 MatchedFlagResultNodes.size())); 841 842 843 // We know that the resulting pattern has exactly one result/ 844 // FIXME2: why? what about something like (set a,b,c, (complexpat)) 845 // FIXME2: Implicit results should be pushed here I guess? 846 AddMatcherNode(new CompleteMatchMatcherNode(Ops.data(), Ops.size(), Pattern)); 847} 848 849 850MatcherNode *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern, 851 const CodeGenDAGPatterns &CGP) { 852 MatcherGen Gen(Pattern, CGP); 853 854 // Generate the code for the matcher. 855 Gen.EmitMatcherCode(); 856 857 858 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence. 859 // FIXME2: Split result code out to another table, and make the matcher end 860 // with an "Emit <index>" command. This allows result generation stuff to be 861 // shared and factored? 862 863 // If the match succeeds, then we generate Pattern. 864 Gen.EmitResultCode(); 865 866 // Unconditional match. 867 return Gen.GetMatcher(); 868} 869 870 871 872