DAGISelMatcherGen.cpp revision b21ba71045420b4c0dc5f30e85b9b01c9165eb57
1//===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "DAGISelMatcher.h" 11#include "CodeGenDAGPatterns.h" 12#include "Record.h" 13#include "llvm/ADT/SmallVector.h" 14#include "llvm/ADT/StringMap.h" 15#include <utility> 16using namespace llvm; 17 18 19/// getRegisterValueType - Look up and return the ValueType of the specified 20/// register. If the register is a member of multiple register classes which 21/// have different associated types, return MVT::Other. 22static MVT::SimpleValueType getRegisterValueType(Record *R, 23 const CodeGenTarget &T) { 24 bool FoundRC = false; 25 MVT::SimpleValueType VT = MVT::Other; 26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses(); 27 std::vector<Record*>::const_iterator Element; 28 29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) { 30 const CodeGenRegisterClass &RC = RCs[rc]; 31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R)) 32 continue; 33 34 if (!FoundRC) { 35 FoundRC = true; 36 VT = RC.getValueTypeNum(0); 37 continue; 38 } 39 40 // In multiple RC's. If the Types of the RC's do not agree, return 41 // MVT::Other. The target is responsible for handling this. 42 if (VT != RC.getValueTypeNum(0)) 43 // FIXME2: when does this happen? Abort? 44 return MVT::Other; 45 } 46 return VT; 47} 48 49 50namespace { 51 class MatcherGen { 52 const PatternToMatch &Pattern; 53 const CodeGenDAGPatterns &CGP; 54 55 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts 56 /// out with all of the types removed. This allows us to insert type checks 57 /// as we scan the tree. 58 TreePatternNode *PatWithNoTypes; 59 60 /// VariableMap - A map from variable names ('$dst') to the recorded operand 61 /// number that they were captured as. These are biased by 1 to make 62 /// insertion easier. 63 StringMap<unsigned> VariableMap; 64 65 /// NextRecordedOperandNo - As we emit opcodes to record matched values in 66 /// the RecordedNodes array, this keeps track of which slot will be next to 67 /// record into. 68 unsigned NextRecordedOperandNo; 69 70 /// MatchedChainNodes - This maintains the position in the recorded nodes 71 /// array of all of the recorded input nodes that have chains. 72 SmallVector<unsigned, 2> MatchedChainNodes; 73 74 /// MatchedFlagResultNodes - This maintains the position in the recorded 75 /// nodes array of all of the recorded input nodes that have flag results. 76 SmallVector<unsigned, 2> MatchedFlagResultNodes; 77 78 /// PhysRegInputs - List list has an entry for each explicitly specified 79 /// physreg input to the pattern. The first elt is the Register node, the 80 /// second is the recorded slot number the input pattern match saved it in. 81 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs; 82 83 /// EmittedMergeInputChains - For nodes that match patterns involving 84 /// chains, is set to true if we emitted the "MergeInputChains" operation. 85 bool EmittedMergeInputChains; 86 87 /// Matcher - This is the top level of the generated matcher, the result. 88 Matcher *TheMatcher; 89 90 /// CurPredicate - As we emit matcher nodes, this points to the latest check 91 /// which should have future checks stuck into its Next position. 92 Matcher *CurPredicate; 93 public: 94 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp); 95 96 ~MatcherGen() { 97 delete PatWithNoTypes; 98 } 99 100 void EmitMatcherCode(); 101 void EmitResultCode(); 102 103 Matcher *GetMatcher() const { return TheMatcher; } 104 Matcher *GetCurPredicate() const { return CurPredicate; } 105 private: 106 void AddMatcher(Matcher *NewNode); 107 void InferPossibleTypes(); 108 109 // Matcher Generation. 110 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes); 111 void EmitLeafMatchCode(const TreePatternNode *N); 112 void EmitOperatorMatchCode(const TreePatternNode *N, 113 TreePatternNode *NodeNoTypes); 114 115 // Result Code Generation. 116 unsigned getNamedArgumentSlot(StringRef Name) { 117 unsigned VarMapEntry = VariableMap[Name]; 118 assert(VarMapEntry != 0 && 119 "Variable referenced but not defined and not caught earlier!"); 120 return VarMapEntry-1; 121 } 122 123 /// GetInstPatternNode - Get the pattern for an instruction. 124 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins, 125 const TreePatternNode *N); 126 127 void EmitResultOperand(const TreePatternNode *N, 128 SmallVectorImpl<unsigned> &ResultOps); 129 void EmitResultOfNamedOperand(const TreePatternNode *N, 130 SmallVectorImpl<unsigned> &ResultOps); 131 void EmitResultLeafAsOperand(const TreePatternNode *N, 132 SmallVectorImpl<unsigned> &ResultOps); 133 void EmitResultInstructionAsOperand(const TreePatternNode *N, 134 SmallVectorImpl<unsigned> &ResultOps); 135 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N, 136 SmallVectorImpl<unsigned> &ResultOps); 137 }; 138 139} // end anon namespace. 140 141MatcherGen::MatcherGen(const PatternToMatch &pattern, 142 const CodeGenDAGPatterns &cgp) 143: Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0), 144 EmittedMergeInputChains(false), TheMatcher(0), CurPredicate(0) { 145 // We need to produce the matcher tree for the patterns source pattern. To do 146 // this we need to match the structure as well as the types. To do the type 147 // matching, we want to figure out the fewest number of type checks we need to 148 // emit. For example, if there is only one integer type supported by a 149 // target, there should be no type comparisons at all for integer patterns! 150 // 151 // To figure out the fewest number of type checks needed, clone the pattern, 152 // remove the types, then perform type inference on the pattern as a whole. 153 // If there are unresolved types, emit an explicit check for those types, 154 // apply the type to the tree, then rerun type inference. Iterate until all 155 // types are resolved. 156 // 157 PatWithNoTypes = Pattern.getSrcPattern()->clone(); 158 PatWithNoTypes->RemoveAllTypes(); 159 160 // If there are types that are manifestly known, infer them. 161 InferPossibleTypes(); 162} 163 164/// InferPossibleTypes - As we emit the pattern, we end up generating type 165/// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we 166/// want to propagate implied types as far throughout the tree as possible so 167/// that we avoid doing redundant type checks. This does the type propagation. 168void MatcherGen::InferPossibleTypes() { 169 // TP - Get *SOME* tree pattern, we don't care which. It is only used for 170 // diagnostics, which we know are impossible at this point. 171 TreePattern &TP = *CGP.pf_begin()->second; 172 173 try { 174 bool MadeChange = true; 175 while (MadeChange) 176 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP, 177 true/*Ignore reg constraints*/); 178 } catch (...) { 179 errs() << "Type constraint application shouldn't fail!"; 180 abort(); 181 } 182} 183 184 185/// AddMatcher - Add a matcher node to the current graph we're building. 186void MatcherGen::AddMatcher(Matcher *NewNode) { 187 if (CurPredicate != 0) 188 CurPredicate->setNext(NewNode); 189 else 190 TheMatcher = NewNode; 191 CurPredicate = NewNode; 192} 193 194 195//===----------------------------------------------------------------------===// 196// Pattern Match Generation 197//===----------------------------------------------------------------------===// 198 199/// EmitLeafMatchCode - Generate matching code for leaf nodes. 200void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) { 201 assert(N->isLeaf() && "Not a leaf?"); 202 203 // If there are node predicates for this node, generate their checks. 204 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i) 205 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i])); 206 207 // Direct match against an integer constant. 208 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) 209 return AddMatcher(new CheckIntegerMatcher(II->getValue())); 210 211 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue()); 212 if (DI == 0) { 213 errs() << "Unknown leaf kind: " << *DI << "\n"; 214 abort(); 215 } 216 217 Record *LeafRec = DI->getDef(); 218 if (// Handle register references. Nothing to do here, they always match. 219 LeafRec->isSubClassOf("RegisterClass") || 220 LeafRec->isSubClassOf("PointerLikeRegClass") || 221 // Place holder for SRCVALUE nodes. Nothing to do here. 222 LeafRec->getName() == "srcvalue") 223 return; 224 225 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to 226 // record the register 227 if (LeafRec->isSubClassOf("Register")) { 228 AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName())); 229 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++)); 230 return; 231 } 232 233 if (LeafRec->isSubClassOf("ValueType")) 234 return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName())); 235 236 if (LeafRec->isSubClassOf("CondCode")) 237 return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName())); 238 239 if (LeafRec->isSubClassOf("ComplexPattern")) { 240 // We can't model ComplexPattern uses that don't have their name taken yet. 241 // The OPC_CheckComplexPattern operation implicitly records the results. 242 if (N->getName().empty()) { 243 errs() << "We expect complex pattern uses to have names: " << *N << "\n"; 244 exit(1); 245 } 246 247 // Handle complex pattern. 248 const ComplexPattern &CP = CGP.getComplexPattern(LeafRec); 249 250 // If we're at the root of the pattern, we have to check that the opcode 251 // is a one of the ones requested to be matched. 252 if (N == Pattern.getSrcPattern()) { 253 const std::vector<Record*> &OpNodes = CP.getRootNodes(); 254 if (OpNodes.size() == 1) { 255 StringRef OpName = CGP.getSDNodeInfo(OpNodes[0]).getEnumName(); 256 AddMatcher(new CheckOpcodeMatcher(OpName)); 257 } else if (!OpNodes.empty()) { 258 SmallVector<StringRef, 4> OpNames; 259 for (unsigned i = 0, e = OpNodes.size(); i != e; i++) 260 OpNames.push_back(CGP.getSDNodeInfo(OpNodes[i]).getEnumName()); 261 AddMatcher(new CheckMultiOpcodeMatcher(OpNames.data(), 262 OpNames.size())); 263 } 264 } 265 266 // Emit a CheckComplexPat operation, which does the match (aborting if it 267 // fails) and pushes the matched operands onto the recorded nodes list. 268 AddMatcher(new CheckComplexPatMatcher(CP)); 269 270 // Record the right number of operands. 271 NextRecordedOperandNo += CP.getNumOperands(); 272 if (CP.hasProperty(SDNPHasChain)) 273 ++NextRecordedOperandNo; // Chained node operand. 274 275 // If the complex pattern has a chain, then we need to keep track of the 276 // fact that we just recorded a chain input. The chain input will be 277 // matched as the last operand of the predicate if it was successful. 278 if (CP.hasProperty(SDNPHasChain)) { 279 // It is the last operand recorded. 280 assert(NextRecordedOperandNo > 1 && 281 "Should have recorded input/result chains at least!"); 282 MatchedChainNodes.push_back(NextRecordedOperandNo-1); 283 284 // If we need to check chains, do so, see comment for 285 // "NodeHasProperty(SDNPHasChain" below. 286 if (MatchedChainNodes.size() > 1) { 287 // FIXME2: This is broken, we should eliminate this nonsense completely, 288 // but we want to produce the same selections that the old matcher does 289 // for now. 290 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2]; 291 AddMatcher(new CheckChainCompatibleMatcher(PrevOp)); 292 } 293 } 294 295 // TODO: Complex patterns can't have output flags, if they did, we'd want 296 // to record them. 297 return; 298 } 299 300 errs() << "Unknown leaf kind: " << *N << "\n"; 301 abort(); 302} 303 304void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N, 305 TreePatternNode *NodeNoTypes) { 306 assert(!N->isLeaf() && "Not an operator?"); 307 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator()); 308 309 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is 310 // a constant without a predicate fn that has more that one bit set, handle 311 // this as a special case. This is usually for targets that have special 312 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit 313 // handling stuff). Using these instructions is often far more efficient 314 // than materializing the constant. Unfortunately, both the instcombiner 315 // and the dag combiner can often infer that bits are dead, and thus drop 316 // them from the mask in the dag. For example, it might turn 'AND X, 255' 317 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks 318 // to handle this. 319 if ((N->getOperator()->getName() == "and" || 320 N->getOperator()->getName() == "or") && 321 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() && 322 N->getPredicateFns().empty()) { 323 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) { 324 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits. 325 if (N->getOperator()->getName() == "and") 326 AddMatcher(new CheckAndImmMatcher(II->getValue())); 327 else 328 AddMatcher(new CheckOrImmMatcher(II->getValue())); 329 330 // Match the LHS of the AND as appropriate. 331 AddMatcher(new MoveChildMatcher(0)); 332 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0)); 333 AddMatcher(new MoveParentMatcher()); 334 return; 335 } 336 } 337 } 338 339 // Check that the current opcode lines up. 340 AddMatcher(new CheckOpcodeMatcher(CInfo.getEnumName())); 341 342 // If there are node predicates for this node, generate their checks. 343 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i) 344 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i])); 345 346 347 // If this node has memory references (i.e. is a load or store), tell the 348 // interpreter to capture them in the memref array. 349 if (N->NodeHasProperty(SDNPMemOperand, CGP)) 350 AddMatcher(new RecordMemRefMatcher()); 351 352 // If this node has a chain, then the chain is operand #0 is the SDNode, and 353 // the child numbers of the node are all offset by one. 354 unsigned OpNo = 0; 355 if (N->NodeHasProperty(SDNPHasChain, CGP)) { 356 // Record the node and remember it in our chained nodes list. 357 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() + 358 "' chained node")); 359 // Remember all of the input chains our pattern will match. 360 MatchedChainNodes.push_back(NextRecordedOperandNo++); 361 362 // If this is the second (e.g. indbr(load) or store(add(load))) or third 363 // input chain (e.g. (store (add (load, load))) from msp430) we need to make 364 // sure that folding the chain won't induce cycles in the DAG. This could 365 // happen if there were an intermediate node between the indbr and load, for 366 // example. 367 if (MatchedChainNodes.size() > 1) { 368 // FIXME2: This is broken, we should eliminate this nonsense completely, 369 // but we want to produce the same selections that the old matcher does 370 // for now. 371 unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2]; 372 AddMatcher(new CheckChainCompatibleMatcher(PrevOp)); 373 } 374 375 // Don't look at the input chain when matching the tree pattern to the 376 // SDNode. 377 OpNo = 1; 378 379 // If this node is not the root and the subtree underneath it produces a 380 // chain, then the result of matching the node is also produce a chain. 381 // Beyond that, this means that we're also folding (at least) the root node 382 // into the node that produce the chain (for example, matching 383 // "(add reg, (load ptr))" as a add_with_memory on X86). This is 384 // problematic, if the 'reg' node also uses the load (say, its chain). 385 // Graphically: 386 // 387 // [LD] 388 // ^ ^ 389 // | \ DAG's like cheese. 390 // / | 391 // / [YY] 392 // | ^ 393 // [XX]--/ 394 // 395 // It would be invalid to fold XX and LD. In this case, folding the two 396 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG' 397 // To prevent this, we emit a dynamic check for legality before allowing 398 // this to be folded. 399 // 400 const TreePatternNode *Root = Pattern.getSrcPattern(); 401 if (N != Root) { // Not the root of the pattern. 402 // If there is a node between the root and this node, then we definitely 403 // need to emit the check. 404 bool NeedCheck = !Root->hasChild(N); 405 406 // If it *is* an immediate child of the root, we can still need a check if 407 // the root SDNode has multiple inputs. For us, this means that it is an 408 // intrinsic, has multiple operands, or has other inputs like chain or 409 // flag). 410 if (!NeedCheck) { 411 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator()); 412 NeedCheck = 413 Root->getOperator() == CGP.get_intrinsic_void_sdnode() || 414 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() || 415 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() || 416 PInfo.getNumOperands() > 1 || 417 PInfo.hasProperty(SDNPHasChain) || 418 PInfo.hasProperty(SDNPInFlag) || 419 PInfo.hasProperty(SDNPOptInFlag); 420 } 421 422 if (NeedCheck) 423 AddMatcher(new CheckFoldableChainNodeMatcher()); 424 } 425 } 426 427 // If this node has an output flag and isn't the root, remember it. 428 if (N->NodeHasProperty(SDNPOutFlag, CGP) && 429 N != Pattern.getSrcPattern()) { 430 // TODO: This redundantly records nodes with both flags and chains. 431 432 // Record the node and remember it in our chained nodes list. 433 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() + 434 "' flag output node")); 435 // Remember all of the nodes with output flags our pattern will match. 436 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++); 437 } 438 439 // If this node is known to have an input flag or if it *might* have an input 440 // flag, capture it as the flag input of the pattern. 441 if (N->NodeHasProperty(SDNPOptInFlag, CGP) || 442 N->NodeHasProperty(SDNPInFlag, CGP)) 443 AddMatcher(new CaptureFlagInputMatcher()); 444 445 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) { 446 // Get the code suitable for matching this child. Move to the child, check 447 // it then move back to the parent. 448 AddMatcher(new MoveChildMatcher(OpNo)); 449 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i)); 450 AddMatcher(new MoveParentMatcher()); 451 } 452} 453 454 455void MatcherGen::EmitMatchCode(const TreePatternNode *N, 456 TreePatternNode *NodeNoTypes) { 457 // If N and NodeNoTypes don't agree on a type, then this is a case where we 458 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and 459 // reinfer any correlated types. 460 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) { 461 AddMatcher(new CheckTypeMatcher(N->getTypeNum(0))); 462 NodeNoTypes->setTypes(N->getExtTypes()); 463 InferPossibleTypes(); 464 } 465 466 // If this node has a name associated with it, capture it in VariableMap. If 467 // we already saw this in the pattern, emit code to verify dagness. 468 if (!N->getName().empty()) { 469 unsigned &VarMapEntry = VariableMap[N->getName()]; 470 if (VarMapEntry == 0) { 471 // If it is a named node, we must emit a 'Record' opcode. 472 VarMapEntry = ++NextRecordedOperandNo; 473 AddMatcher(new RecordMatcher("$" + N->getName())); 474 } else { 475 // If we get here, this is a second reference to a specific name. Since 476 // we already have checked that the first reference is valid, we don't 477 // have to recursively match it, just check that it's the same as the 478 // previously named thing. 479 AddMatcher(new CheckSameMatcher(VarMapEntry-1)); 480 return; 481 } 482 } 483 484 if (N->isLeaf()) 485 EmitLeafMatchCode(N); 486 else 487 EmitOperatorMatchCode(N, NodeNoTypes); 488} 489 490void MatcherGen::EmitMatcherCode() { 491 // If the pattern has a predicate on it (e.g. only enabled when a subtarget 492 // feature is around, do the check). 493 // FIXME: This should get emitted after the match code below to encourage 494 // sharing. This can't happen until we get an X86ISD::AddrMode node made by 495 // dag combine, eliminating the horrible side-effect-full stuff from 496 // X86's MatchAddress. 497 if (!Pattern.getPredicateCheck().empty()) 498 AddMatcher(new 499 CheckPatternPredicateMatcher(Pattern.getPredicateCheck())); 500 501 // Emit the matcher for the pattern structure and types. 502 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes); 503} 504 505 506//===----------------------------------------------------------------------===// 507// Node Result Generation 508//===----------------------------------------------------------------------===// 509 510void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N, 511 SmallVectorImpl<unsigned> &ResultOps){ 512 assert(!N->getName().empty() && "Operand not named!"); 513 514 unsigned SlotNo = getNamedArgumentSlot(N->getName()); 515 516 // A reference to a complex pattern gets all of the results of the complex 517 // pattern's match. 518 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) { 519 // The first slot entry is the node itself, the subsequent entries are the 520 // matched values. 521 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) 522 ResultOps.push_back(SlotNo+i+1); 523 return; 524 } 525 526 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target 527 // version of the immediate so that it doesn't get selected due to some other 528 // node use. 529 if (!N->isLeaf()) { 530 StringRef OperatorName = N->getOperator()->getName(); 531 if (OperatorName == "imm" || OperatorName == "fpimm") { 532 AddMatcher(new EmitConvertToTargetMatcher(SlotNo)); 533 ResultOps.push_back(NextRecordedOperandNo++); 534 return; 535 } 536 } 537 538 ResultOps.push_back(SlotNo); 539} 540 541void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N, 542 SmallVectorImpl<unsigned> &ResultOps) { 543 assert(N->isLeaf() && "Must be a leaf"); 544 545 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) { 546 AddMatcher(new EmitIntegerMatcher(II->getValue(),N->getTypeNum(0))); 547 ResultOps.push_back(NextRecordedOperandNo++); 548 return; 549 } 550 551 // If this is an explicit register reference, handle it. 552 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) { 553 if (DI->getDef()->isSubClassOf("Register")) { 554 AddMatcher(new EmitRegisterMatcher(DI->getDef(), 555 N->getTypeNum(0))); 556 ResultOps.push_back(NextRecordedOperandNo++); 557 return; 558 } 559 560 if (DI->getDef()->getName() == "zero_reg") { 561 AddMatcher(new EmitRegisterMatcher(0, N->getTypeNum(0))); 562 ResultOps.push_back(NextRecordedOperandNo++); 563 return; 564 } 565 566 // Handle a reference to a register class. This is used 567 // in COPY_TO_SUBREG instructions. 568 if (DI->getDef()->isSubClassOf("RegisterClass")) { 569 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID"; 570 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32)); 571 ResultOps.push_back(NextRecordedOperandNo++); 572 return; 573 } 574 } 575 576 errs() << "unhandled leaf node: \n"; 577 N->dump(); 578} 579 580/// GetInstPatternNode - Get the pattern for an instruction. 581/// 582const TreePatternNode *MatcherGen:: 583GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) { 584 const TreePattern *InstPat = Inst.getPattern(); 585 586 // FIXME2?: Assume actual pattern comes before "implicit". 587 TreePatternNode *InstPatNode; 588 if (InstPat) 589 InstPatNode = InstPat->getTree(0); 590 else if (/*isRoot*/ N == Pattern.getDstPattern()) 591 InstPatNode = Pattern.getSrcPattern(); 592 else 593 return 0; 594 595 if (InstPatNode && !InstPatNode->isLeaf() && 596 InstPatNode->getOperator()->getName() == "set") 597 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1); 598 599 return InstPatNode; 600} 601 602void MatcherGen:: 603EmitResultInstructionAsOperand(const TreePatternNode *N, 604 SmallVectorImpl<unsigned> &OutputOps) { 605 Record *Op = N->getOperator(); 606 const CodeGenTarget &CGT = CGP.getTargetInfo(); 607 CodeGenInstruction &II = CGT.getInstruction(Op->getName()); 608 const DAGInstruction &Inst = CGP.getInstruction(Op); 609 610 // If we can, get the pattern for the instruction we're generating. We derive 611 // a variety of information from this pattern, such as whether it has a chain. 612 // 613 // FIXME2: This is extremely dubious for several reasons, not the least of 614 // which it gives special status to instructions with patterns that Pat<> 615 // nodes can't duplicate. 616 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N); 617 618 // NodeHasChain - Whether the instruction node we're creating takes chains. 619 bool NodeHasChain = InstPatNode && 620 InstPatNode->TreeHasProperty(SDNPHasChain, CGP); 621 622 bool isRoot = N == Pattern.getDstPattern(); 623 624 // TreeHasOutFlag - True if this tree has a flag. 625 bool TreeHasInFlag = false, TreeHasOutFlag = false; 626 if (isRoot) { 627 const TreePatternNode *SrcPat = Pattern.getSrcPattern(); 628 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) || 629 SrcPat->TreeHasProperty(SDNPInFlag, CGP); 630 631 // FIXME2: this is checking the entire pattern, not just the node in 632 // question, doing this just for the root seems like a total hack. 633 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP); 634 } 635 636 // NumResults - This is the number of results produced by the instruction in 637 // the "outs" list. 638 unsigned NumResults = Inst.getNumResults(); 639 640 // Loop over all of the operands of the instruction pattern, emitting code 641 // to fill them all in. The node 'N' usually has number children equal to 642 // the number of input operands of the instruction. However, in cases 643 // where there are predicate operands for an instruction, we need to fill 644 // in the 'execute always' values. Match up the node operands to the 645 // instruction operands to do this. 646 SmallVector<unsigned, 8> InstOps; 647 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size(); 648 InstOpNo != e; ++InstOpNo) { 649 650 // Determine what to emit for this operand. 651 Record *OperandNode = II.OperandList[InstOpNo].Rec; 652 if ((OperandNode->isSubClassOf("PredicateOperand") || 653 OperandNode->isSubClassOf("OptionalDefOperand")) && 654 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) { 655 // This is a predicate or optional def operand; emit the 656 // 'default ops' operands. 657 const DAGDefaultOperand &DefaultOp = 658 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec); 659 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i) 660 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps); 661 continue; 662 } 663 664 // Otherwise this is a normal operand or a predicate operand without 665 // 'execute always'; emit it. 666 EmitResultOperand(N->getChild(ChildNo), InstOps); 667 ++ChildNo; 668 } 669 670 // Nodes that match patterns with (potentially multiple) chain inputs have to 671 // merge them together into a token factor. 672 if (NodeHasChain && !EmittedMergeInputChains) { 673 // FIXME2: Move this out of emitresult to a top level place. 674 assert(!MatchedChainNodes.empty() && 675 "How can this node have chain if no inputs do?"); 676 // Otherwise, we have to emit an operation to merge the input chains and 677 // set this as the current input chain. 678 AddMatcher(new EmitMergeInputChainsMatcher 679 (MatchedChainNodes.data(), MatchedChainNodes.size())); 680 EmittedMergeInputChains = true; 681 } 682 683 // If this node has an input flag or explicitly specified input physregs, we 684 // need to add chained and flagged copyfromreg nodes and materialize the flag 685 // input. 686 if (isRoot && !PhysRegInputs.empty()) { 687 // Emit all of the CopyToReg nodes for the input physical registers. These 688 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src). 689 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i) 690 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second, 691 PhysRegInputs[i].first)); 692 // Even if the node has no other flag inputs, the resultant node must be 693 // flagged to the CopyFromReg nodes we just generated. 694 TreeHasInFlag = true; 695 } 696 697 // Result order: node results, chain, flags 698 699 // Determine the result types. 700 SmallVector<MVT::SimpleValueType, 4> ResultVTs; 701 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) { 702 // FIXME2: If the node has multiple results, we should add them. For now, 703 // preserve existing behavior?! 704 ResultVTs.push_back(N->getTypeNum(0)); 705 } 706 707 708 // If this is the root instruction of a pattern that has physical registers in 709 // its result pattern, add output VTs for them. For example, X86 has: 710 // (set AL, (mul ...)) 711 // This also handles implicit results like: 712 // (implicit EFLAGS) 713 if (isRoot && Pattern.getDstRegs().size() != 0) { 714 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) 715 if (Pattern.getDstRegs()[i]->isSubClassOf("Register")) 716 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT)); 717 } 718 if (NodeHasChain) 719 ResultVTs.push_back(MVT::Other); 720 if (TreeHasOutFlag) 721 ResultVTs.push_back(MVT::Flag); 722 723 // FIXME2: Instead of using the isVariadic flag on the instruction, we should 724 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic 725 // property should be inferred from this when an instruction has a pattern. 726 int NumFixedArityOperands = -1; 727 if (isRoot && II.isVariadic) 728 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren(); 729 730 // If this is the root node and any of the nodes matched nodes in the input 731 // pattern have MemRefs in them, have the interpreter collect them and plop 732 // them onto this node. 733 // 734 // FIXME3: This is actively incorrect for result patterns where the root of 735 // the pattern is not the memory reference and is also incorrect when the 736 // result pattern has multiple memory-referencing instructions. For example, 737 // in the X86 backend, this pattern causes the memrefs to get attached to the 738 // CVTSS2SDrr instead of the MOVSSrm: 739 // 740 // def : Pat<(extloadf32 addr:$src), 741 // (CVTSS2SDrr (MOVSSrm addr:$src))>; 742 // 743 bool NodeHasMemRefs = 744 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP); 745 746 // FIXME: Eventually add a SelectNodeTo form. It works if the new node has a 747 // superset of the results of the old node, in the same places. E.g. turning 748 // (add (load)) -> add32rm is ok because result #0 is the result and result #1 749 // is new. 750 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(), 751 ResultVTs.data(), ResultVTs.size(), 752 InstOps.data(), InstOps.size(), 753 NodeHasChain, TreeHasInFlag, 754 NodeHasMemRefs,NumFixedArityOperands)); 755 756 // The non-chain and non-flag results of the newly emitted node get recorded. 757 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) { 758 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break; 759 OutputOps.push_back(NextRecordedOperandNo++); 760 } 761 762 // FIXME2: Kill off all the SelectionDAG::SelectNodeTo and getMachineNode 763 // variants. Call MorphNodeTo instead of SelectNodeTo. 764} 765 766void MatcherGen:: 767EmitResultSDNodeXFormAsOperand(const TreePatternNode *N, 768 SmallVectorImpl<unsigned> &ResultOps) { 769 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?"); 770 771 // Emit the operand. 772 SmallVector<unsigned, 8> InputOps; 773 774 // FIXME2: Could easily generalize this to support multiple inputs and outputs 775 // to the SDNodeXForm. For now we just support one input and one output like 776 // the old instruction selector. 777 assert(N->getNumChildren() == 1); 778 EmitResultOperand(N->getChild(0), InputOps); 779 780 // The input currently must have produced exactly one result. 781 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm"); 782 783 AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator())); 784 ResultOps.push_back(NextRecordedOperandNo++); 785} 786 787void MatcherGen::EmitResultOperand(const TreePatternNode *N, 788 SmallVectorImpl<unsigned> &ResultOps) { 789 // This is something selected from the pattern we matched. 790 if (!N->getName().empty()) 791 return EmitResultOfNamedOperand(N, ResultOps); 792 793 if (N->isLeaf()) 794 return EmitResultLeafAsOperand(N, ResultOps); 795 796 Record *OpRec = N->getOperator(); 797 if (OpRec->isSubClassOf("Instruction")) 798 return EmitResultInstructionAsOperand(N, ResultOps); 799 if (OpRec->isSubClassOf("SDNodeXForm")) 800 return EmitResultSDNodeXFormAsOperand(N, ResultOps); 801 errs() << "Unknown result node to emit code for: " << *N << '\n'; 802 throw std::string("Unknown node in result pattern!"); 803} 804 805void MatcherGen::EmitResultCode() { 806 // Codegen the root of the result pattern, capturing the resulting values. 807 SmallVector<unsigned, 8> Ops; 808 EmitResultOperand(Pattern.getDstPattern(), Ops); 809 810 // At this point, we have however many values the result pattern produces. 811 // However, the input pattern might not need all of these. If there are 812 // excess values at the end (such as condition codes etc) just lop them off. 813 // This doesn't need to worry about flags or chains, just explicit results. 814 // 815 // FIXME2: This doesn't work because there is currently no way to get an 816 // accurate count of the # results the source pattern sets. This is because 817 // of the "parallel" construct in X86 land, which looks like this: 818 // 819 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2), 820 // (implicit EFLAGS)), 821 // (AND8rr GR8:$src1, GR8:$src2)>; 822 // 823 // This idiom means to match the two-result node X86and_flag (which is 824 // declared as returning a single result, because we can't match multi-result 825 // nodes yet). In this case, we would have to know that the input has two 826 // results. However, mul8r is modelled exactly the same way, but without 827 // implicit defs included. The fix is to support multiple results directly 828 // and eliminate 'parallel'. 829 // 830 // FIXME2: When this is fixed, we should revert the terrible hack in the 831 // OPC_EmitNode code in the interpreter. 832#if 0 833 const TreePatternNode *Src = Pattern.getSrcPattern(); 834 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0; 835 NumSrcResults += Pattern.getDstRegs().size(); 836 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results"); 837 Ops.resize(NumSrcResults); 838#endif 839 840 // If the matched pattern covers nodes which define a flag result, emit a node 841 // that tells the matcher about them so that it can update their results. 842 if (!MatchedFlagResultNodes.empty()) 843 AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(), 844 MatchedFlagResultNodes.size())); 845 846 847 // We know that the resulting pattern has exactly one result/ 848 // FIXME2: why? what about something like (set a,b,c, (complexpat)) 849 // FIXME2: Implicit results should be pushed here I guess? 850 AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern)); 851} 852 853 854Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern, 855 const CodeGenDAGPatterns &CGP) { 856 MatcherGen Gen(Pattern, CGP); 857 858 // Generate the code for the matcher. 859 Gen.EmitMatcherCode(); 860 861 862 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence. 863 // FIXME2: Split result code out to another table, and make the matcher end 864 // with an "Emit <index>" command. This allows result generation stuff to be 865 // shared and factored? 866 867 // If the match succeeds, then we generate Pattern. 868 Gen.EmitResultCode(); 869 870 // Unconditional match. 871 return Gen.GetMatcher(); 872} 873 874 875 876