nv30_state.c revision 36488ed052a18f7eafef1d1c5c18b20ad508b2b7
1#include "pipe/p_state.h" 2#include "pipe/p_defines.h" 3#include "pipe/p_util.h" 4 5#include "nv30_context.h" 6#include "nv30_state.h" 7 8static void * 9nv30_blend_state_create(struct pipe_context *pipe, 10 const struct pipe_blend_state *cso) 11{ 12 struct nv30_blend_state *cb; 13 14 cb = malloc(sizeof(struct nv30_blend_state)); 15 16 cb->b_enable = cso->blend_enable ? 1 : 0; 17 cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) | 18 (nvgl_blend_func(cso->rgb_src_factor))); 19 cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) | 20 (nvgl_blend_func(cso->rgb_dst_factor))); 21 cb->b_eqn = ((nvgl_blend_eqn(cso->alpha_func) << 16) | 22 (nvgl_blend_eqn(cso->rgb_func))); 23 24 cb->l_enable = cso->logicop_enable ? 1 : 0; 25 cb->l_op = nvgl_logicop_func(cso->logicop_func); 26 27 cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) | 28 ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) | 29 ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) | 30 ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0)); 31 32 cb->d_enable = cso->dither ? 1 : 0; 33 34 return (void *)cb; 35} 36 37static void 38nv30_blend_state_bind(struct pipe_context *pipe, void *hwcso) 39{ 40 struct nv30_context *nv30 = nv30_context(pipe); 41 struct nv30_blend_state *cb = hwcso; 42 43 if (!hwcso) { 44 return; 45 } 46 47 BEGIN_RING(rankine, NV34TCL_DITHER_ENABLE, 1); 48 OUT_RING (cb->d_enable); 49 50 BEGIN_RING(rankine, NV34TCL_BLEND_FUNC_ENABLE, 3); 51 OUT_RING (cb->b_enable); 52 OUT_RING (cb->b_srcfunc); 53 OUT_RING (cb->b_dstfunc); 54 BEGIN_RING(rankine, NV34TCL_BLEND_EQUATION, 1); 55 OUT_RING (cb->b_eqn); 56 57 BEGIN_RING(rankine, NV34TCL_COLOR_MASK, 1); 58 OUT_RING (cb->c_mask); 59 60 BEGIN_RING(rankine, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2); 61 OUT_RING (cb->l_enable); 62 OUT_RING (cb->l_op); 63} 64 65static void 66nv30_blend_state_delete(struct pipe_context *pipe, void *hwcso) 67{ 68 free(hwcso); 69} 70 71 72static INLINE unsigned 73wrap_mode(unsigned wrap) { 74 unsigned ret; 75 76 switch (wrap) { 77 case PIPE_TEX_WRAP_REPEAT: 78 ret = NV34TCL_TX_WRAP_S_REPEAT; 79 break; 80 case PIPE_TEX_WRAP_MIRROR_REPEAT: 81 ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT; 82 break; 83 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 84 ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE; 85 break; 86 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 87 ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER; 88 break; 89 case PIPE_TEX_WRAP_CLAMP: 90 ret = NV34TCL_TX_WRAP_S_CLAMP; 91 break; 92/* case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 93 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_EDGE; 94 break; 95 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 96 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_BORDER; 97 break; 98 case PIPE_TEX_WRAP_MIRROR_CLAMP: 99 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP; 100 break;*/ 101 default: 102 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap); 103 ret = NV34TCL_TX_WRAP_S_REPEAT; 104 break; 105 } 106 107 return ret >> NV34TCL_TX_WRAP_S_SHIFT; 108} 109 110static void * 111nv30_sampler_state_create(struct pipe_context *pipe, 112 const struct pipe_sampler_state *cso) 113{ 114 struct nv30_sampler_state *ps; 115 uint32_t filter = 0; 116 117 ps = malloc(sizeof(struct nv30_sampler_state)); 118 119 ps->fmt = 0; 120 if (!cso->normalized_coords) 121 ps->fmt |= NV34TCL_TX_FORMAT_RECT; 122 123 ps->wrap = ((wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) | 124 (wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) | 125 (wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT)); 126 127 ps->en = 0; 128 if (cso->max_anisotropy >= 2.0) { 129 /* no idea, binary driver sets it, works without it.. meh.. */ 130 ps->wrap |= (1 << 5); 131 132/* if (cso->max_anisotropy >= 16.0) { 133 ps->en |= NV34TCL_TX_ENABLE_ANISO_16X; 134 } else 135 if (cso->max_anisotropy >= 12.0) { 136 ps->en |= NV34TCL_TX_ENABLE_ANISO_12X; 137 } else 138 if (cso->max_anisotropy >= 10.0) { 139 ps->en |= NV34TCL_TX_ENABLE_ANISO_10X; 140 } else 141 if (cso->max_anisotropy >= 8.0) { 142 ps->en |= NV34TCL_TX_ENABLE_ANISO_8X; 143 } else 144 if (cso->max_anisotropy >= 6.0) { 145 ps->en |= NV34TCL_TX_ENABLE_ANISO_6X; 146 } else 147 if (cso->max_anisotropy >= 4.0) { 148 ps->en |= NV34TCL_TX_ENABLE_ANISO_4X; 149 } else { 150 ps->en |= NV34TCL_TX_ENABLE_ANISO_2X; 151 }*/ 152 } 153 154 switch (cso->mag_img_filter) { 155 case PIPE_TEX_FILTER_LINEAR: 156 filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR; 157 break; 158 case PIPE_TEX_FILTER_NEAREST: 159 default: 160 filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST; 161 break; 162 } 163 164 switch (cso->min_img_filter) { 165 case PIPE_TEX_FILTER_LINEAR: 166 switch (cso->min_mip_filter) { 167 case PIPE_TEX_MIPFILTER_NEAREST: 168 filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; 169 break; 170 case PIPE_TEX_MIPFILTER_LINEAR: 171 filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; 172 break; 173 case PIPE_TEX_MIPFILTER_NONE: 174 default: 175 filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR; 176 break; 177 } 178 break; 179 case PIPE_TEX_FILTER_NEAREST: 180 default: 181 switch (cso->min_mip_filter) { 182 case PIPE_TEX_MIPFILTER_NEAREST: 183 filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; 184 break; 185 case PIPE_TEX_MIPFILTER_LINEAR: 186 filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; 187 break; 188 case PIPE_TEX_MIPFILTER_NONE: 189 default: 190 filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST; 191 break; 192 } 193 break; 194 } 195 196 ps->filt = filter; 197 198/* if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) { 199 switch (cso->compare_func) { 200 case PIPE_FUNC_NEVER: 201 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NEVER; 202 break; 203 case PIPE_FUNC_GREATER: 204 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GREATER; 205 break; 206 case PIPE_FUNC_EQUAL: 207 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_EQUAL; 208 break; 209 case PIPE_FUNC_GEQUAL: 210 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GEQUAL; 211 break; 212 case PIPE_FUNC_LESS: 213 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LESS; 214 break; 215 case PIPE_FUNC_NOTEQUAL: 216 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NOTEQUAL; 217 break; 218 case PIPE_FUNC_LEQUAL: 219 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LEQUAL; 220 break; 221 case PIPE_FUNC_ALWAYS: 222 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_ALWAYS; 223 break; 224 default: 225 break; 226 } 227 }*/ 228 229 ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) | 230 (float_to_ubyte(cso->border_color[0]) << 16) | 231 (float_to_ubyte(cso->border_color[1]) << 8) | 232 (float_to_ubyte(cso->border_color[2]) << 0)); 233 234 return (void *)ps; 235} 236 237static void 238nv30_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler) 239{ 240 struct nv30_context *nv30 = nv30_context(pipe); 241 unsigned unit; 242 243 if (!sampler) { 244 return; 245 } 246 247 for (unit = 0; unit < nr; unit++) { 248 nv30->tex_sampler[unit] = sampler[unit]; 249 nv30->dirty_samplers |= (1 << unit); 250 } 251} 252 253static void 254nv30_sampler_state_delete(struct pipe_context *pipe, void *hwcso) 255{ 256 free(hwcso); 257} 258 259static void 260nv30_set_sampler_texture(struct pipe_context *pipe, unsigned nr, 261 struct pipe_texture **miptree) 262{ 263 struct nv30_context *nv30 = nv30_context(pipe); 264 unsigned unit; 265 266 for (unit = 0; unit < nr; unit++) { 267 nv30->tex_miptree[unit] = (struct nv30_miptree *)miptree[unit]; 268 nv30->dirty_samplers |= (1 << unit); 269 } 270} 271 272static void * 273nv30_rasterizer_state_create(struct pipe_context *pipe, 274 const struct pipe_rasterizer_state *cso) 275{ 276 struct nv30_rasterizer_state *rs; 277 int i; 278 279 /*XXX: ignored: 280 * light_twoside 281 * offset_cw/ccw -nohw 282 * scissor 283 * point_smooth -nohw 284 * multisample 285 * offset_units / offset_scale 286 */ 287 rs = malloc(sizeof(struct nv30_rasterizer_state)); 288 289 rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01; 290 291 rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff; 292 rs->line_smooth_en = cso->line_smooth ? 1 : 0; 293 rs->line_stipple_en = cso->line_stipple_enable ? 1 : 0; 294 rs->line_stipple = (cso->line_stipple_pattern << 16) | 295 cso->line_stipple_factor; 296 297 rs->point_size = *(uint32_t*)&cso->point_size; 298 299 rs->poly_smooth_en = cso->poly_smooth ? 1 : 0; 300 rs->poly_stipple_en = cso->poly_stipple_enable ? 1 : 0; 301 302 if (cso->front_winding == PIPE_WINDING_CCW) { 303 rs->front_face = NV34TCL_FRONT_FACE_CCW; 304 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw); 305 rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw); 306 } else { 307 rs->front_face = NV34TCL_FRONT_FACE_CW; 308 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw); 309 rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw); 310 } 311 312 switch (cso->cull_mode) { 313 case PIPE_WINDING_CCW: 314 rs->cull_face_en = 1; 315 if (cso->front_winding == PIPE_WINDING_CCW) 316 rs->cull_face = NV34TCL_CULL_FACE_FRONT; 317 else 318 rs->cull_face = NV34TCL_CULL_FACE_BACK; 319 break; 320 case PIPE_WINDING_CW: 321 rs->cull_face_en = 1; 322 if (cso->front_winding == PIPE_WINDING_CW) 323 rs->cull_face = NV34TCL_CULL_FACE_FRONT; 324 else 325 rs->cull_face = NV34TCL_CULL_FACE_BACK; 326 break; 327 case PIPE_WINDING_BOTH: 328 rs->cull_face_en = 1; 329 rs->cull_face = NV34TCL_CULL_FACE_FRONT_AND_BACK; 330 break; 331 case PIPE_WINDING_NONE: 332 default: 333 rs->cull_face_en = 0; 334 rs->cull_face = 0; 335 break; 336 } 337 338 if (cso->point_sprite) { 339 rs->point_sprite = (1 << 0); 340 for (i = 0; i < 8; i++) { 341 if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE) 342 rs->point_sprite |= (1 << (8 + i)); 343 } 344 } else { 345 rs->point_sprite = 0; 346 } 347 348 return (void *)rs; 349} 350 351static void 352nv30_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso) 353{ 354 struct nv30_context *nv30 = nv30_context(pipe); 355 struct nv30_rasterizer_state *rs = hwcso; 356 357 if (!hwcso) { 358 return; 359 } 360 361 BEGIN_RING(rankine, NV34TCL_SHADE_MODEL, 1); 362 OUT_RING (rs->shade_model); 363 364 BEGIN_RING(rankine, NV34TCL_LINE_WIDTH, 2); 365 OUT_RING (rs->line_width); 366 OUT_RING (rs->line_smooth_en); 367 BEGIN_RING(rankine, NV34TCL_LINE_STIPPLE_ENABLE, 2); 368 OUT_RING (rs->line_stipple_en); 369 OUT_RING (rs->line_stipple); 370 371 BEGIN_RING(rankine, NV34TCL_POINT_SIZE, 1); 372 OUT_RING (rs->point_size); 373 374 BEGIN_RING(rankine, NV34TCL_POLYGON_MODE_FRONT, 6); 375 OUT_RING (rs->poly_mode_front); 376 OUT_RING (rs->poly_mode_back); 377 OUT_RING (rs->cull_face); 378 OUT_RING (rs->front_face); 379 OUT_RING (rs->poly_smooth_en); 380 OUT_RING (rs->cull_face_en); 381 382 BEGIN_RING(rankine, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); 383 OUT_RING (rs->poly_stipple_en); 384 385 BEGIN_RING(rankine, NV34TCL_POINT_SPRITE, 1); 386 OUT_RING (rs->point_sprite); 387} 388 389static void 390nv30_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) 391{ 392 free(hwcso); 393} 394 395static void 396nv30_translate_stencil(const struct pipe_depth_stencil_alpha_state *cso, 397 unsigned idx, struct nv30_stencil_push *hw) 398{ 399 hw->enable = cso->stencil[idx].enabled ? 1 : 0; 400 hw->wmask = cso->stencil[idx].write_mask; 401 hw->func = nvgl_comparison_op(cso->stencil[idx].func); 402 hw->ref = cso->stencil[idx].ref_value; 403 hw->vmask = cso->stencil[idx].value_mask; 404 hw->fail = nvgl_stencil_op(cso->stencil[idx].fail_op); 405 hw->zfail = nvgl_stencil_op(cso->stencil[idx].zfail_op); 406 hw->zpass = nvgl_stencil_op(cso->stencil[idx].zpass_op); 407} 408 409static void * 410nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, 411 const struct pipe_depth_stencil_alpha_state *cso) 412{ 413 struct nv30_depth_stencil_alpha_state *hw; 414 415 hw = malloc(sizeof(struct nv30_depth_stencil_alpha_state)); 416 417 hw->depth.func = nvgl_comparison_op(cso->depth.func); 418 hw->depth.write_enable = cso->depth.writemask ? 1 : 0; 419 hw->depth.test_enable = cso->depth.enabled ? 1 : 0; 420 421 nv30_translate_stencil(cso, 0, &hw->stencil.front); 422 nv30_translate_stencil(cso, 1, &hw->stencil.back); 423 424 hw->alpha.enabled = cso->alpha.enabled ? 1 : 0; 425 hw->alpha.func = nvgl_comparison_op(cso->alpha.func); 426 hw->alpha.ref = float_to_ubyte(cso->alpha.ref); 427 428 return (void *)hw; 429} 430 431static void 432nv30_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso) 433{ 434 struct nv30_context *nv30 = nv30_context(pipe); 435 struct nv30_depth_stencil_alpha_state *hw = hwcso; 436 437 if (!hwcso) { 438 return; 439 } 440 441 BEGIN_RING(rankine, NV34TCL_DEPTH_FUNC, 3); 442 OUT_RINGp ((uint32_t *)&hw->depth, 3); 443 BEGIN_RING(rankine, NV34TCL_STENCIL_BACK_ENABLE, 16); 444 OUT_RINGp ((uint32_t *)&hw->stencil.back, 8); 445 OUT_RINGp ((uint32_t *)&hw->stencil.front, 8); 446 BEGIN_RING(rankine, NV34TCL_ALPHA_FUNC_ENABLE, 3); 447 OUT_RINGp ((uint32_t *)&hw->alpha.enabled, 3); 448} 449 450static void 451nv30_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso) 452{ 453 free(hwcso); 454} 455 456static void * 457nv30_vp_state_create(struct pipe_context *pipe, 458 const struct pipe_shader_state *cso) 459{ 460 struct nv30_vertex_program *vp; 461 462 vp = CALLOC(1, sizeof(struct nv30_vertex_program)); 463 vp->pipe = *cso; 464 465 return (void *)vp; 466} 467 468static void 469nv30_vp_state_bind(struct pipe_context *pipe, void *hwcso) 470{ 471 struct nv30_context *nv30 = nv30_context(pipe); 472 struct nv30_vertex_program *vp = hwcso; 473 474 if (!hwcso) { 475 return; 476 } 477 478 nv30->vertprog.current = vp; 479 nv30->dirty |= NV30_NEW_VERTPROG; 480} 481 482static void 483nv30_vp_state_delete(struct pipe_context *pipe, void *hwcso) 484{ 485 struct nv30_context *nv30 = nv30_context(pipe); 486 struct nv30_vertex_program *vp = hwcso; 487 488 nv30_vertprog_destroy(nv30, vp); 489 FREE(vp); 490} 491 492static void * 493nv30_fp_state_create(struct pipe_context *pipe, 494 const struct pipe_shader_state *cso) 495{ 496 struct nv30_fragment_program *fp; 497 498 fp = CALLOC(1, sizeof(struct nv30_fragment_program)); 499 fp->pipe = *cso; 500 501 return (void *)fp; 502} 503 504static void 505nv30_fp_state_bind(struct pipe_context *pipe, void *hwcso) 506{ 507 struct nv30_context *nv30 = nv30_context(pipe); 508 struct nv30_fragment_program *fp = hwcso; 509 510 if (!hwcso) { 511 return; 512 } 513 514 nv30->fragprog.current = fp; 515 nv30->dirty |= NV30_NEW_FRAGPROG; 516} 517 518static void 519nv30_fp_state_delete(struct pipe_context *pipe, void *hwcso) 520{ 521 struct nv30_context *nv30 = nv30_context(pipe); 522 struct nv30_fragment_program *fp = hwcso; 523 524 nv30_fragprog_destroy(nv30, fp); 525 FREE(fp); 526} 527 528static void 529nv30_set_blend_color(struct pipe_context *pipe, 530 const struct pipe_blend_color *bcol) 531{ 532 struct nv30_context *nv30 = nv30_context(pipe); 533 534 BEGIN_RING(rankine, NV34TCL_BLEND_COLOR, 1); 535 OUT_RING ((float_to_ubyte(bcol->color[3]) << 24) | 536 (float_to_ubyte(bcol->color[0]) << 16) | 537 (float_to_ubyte(bcol->color[1]) << 8) | 538 (float_to_ubyte(bcol->color[2]) << 0)); 539} 540 541static void 542nv30_set_clip_state(struct pipe_context *pipe, 543 const struct pipe_clip_state *clip) 544{ 545} 546 547static void 548nv30_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, 549 const struct pipe_constant_buffer *buf ) 550{ 551 struct nv30_context *nv30 = nv30_context(pipe); 552 553 if (shader == PIPE_SHADER_VERTEX) { 554 nv30->vertprog.constant_buf = buf->buffer; 555 nv30->dirty |= NV30_NEW_VERTPROG; 556 } else 557 if (shader == PIPE_SHADER_FRAGMENT) { 558 nv30->fragprog.constant_buf = buf->buffer; 559 nv30->dirty |= NV30_NEW_FRAGPROG; 560 } 561} 562 563static void 564nv30_set_framebuffer_state(struct pipe_context *pipe, 565 const struct pipe_framebuffer_state *fb) 566{ 567 struct nv30_context *nv30 = nv30_context(pipe); 568 569 nv30->framebuffer = *fb; 570 nv30->dirty |= NV30_NEW_FB; 571} 572 573static void 574nv30_set_polygon_stipple(struct pipe_context *pipe, 575 const struct pipe_poly_stipple *stipple) 576{ 577 struct nv30_context *nv30 = nv30_context(pipe); 578 579 BEGIN_RING(rankine, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32); 580 OUT_RINGp ((uint32_t *)stipple->stipple, 32); 581} 582 583static void 584nv30_set_scissor_state(struct pipe_context *pipe, 585 const struct pipe_scissor_state *s) 586{ 587 struct nv30_context *nv30 = nv30_context(pipe); 588 589 BEGIN_RING(rankine, NV34TCL_SCISSOR_HORIZ, 2); 590 OUT_RING (((s->maxx - s->minx) << 16) | s->minx); 591 OUT_RING (((s->maxy - s->miny) << 16) | s->miny); 592} 593 594static void 595nv30_set_viewport_state(struct pipe_context *pipe, 596 const struct pipe_viewport_state *vpt) 597{ 598 struct nv30_context *nv30 = nv30_context(pipe); 599 600 BEGIN_RING(rankine, NV34TCL_VIEWPORT_TRANSLATE_X, 8); 601 OUT_RINGf (vpt->translate[0]); 602 OUT_RINGf (vpt->translate[1]); 603 OUT_RINGf (vpt->translate[2]); 604 OUT_RINGf (vpt->translate[3]); 605 OUT_RINGf (vpt->scale[0]); 606 OUT_RINGf (vpt->scale[1]); 607 OUT_RINGf (vpt->scale[2]); 608 OUT_RINGf (vpt->scale[3]); 609} 610 611static void 612nv30_set_vertex_buffers(struct pipe_context *pipe, unsigned count, 613 const struct pipe_vertex_buffer *vb) 614{ 615 struct nv30_context *nv30 = nv30_context(pipe); 616 617 memcpy(nv30->vtxbuf, vb, sizeof(*vb) * count); 618 nv30->dirty |= NV30_NEW_ARRAYS; 619} 620 621static void 622nv30_set_vertex_elements(struct pipe_context *pipe, unsigned count, 623 const struct pipe_vertex_element *ve) 624{ 625 struct nv30_context *nv30 = nv30_context(pipe); 626 627 memcpy(nv30->vtxelt, ve, sizeof(*ve) * count); 628 nv30->dirty |= NV30_NEW_ARRAYS; 629} 630 631void 632nv30_init_state_functions(struct nv30_context *nv30) 633{ 634 nv30->pipe.create_blend_state = nv30_blend_state_create; 635 nv30->pipe.bind_blend_state = nv30_blend_state_bind; 636 nv30->pipe.delete_blend_state = nv30_blend_state_delete; 637 638 nv30->pipe.create_sampler_state = nv30_sampler_state_create; 639 nv30->pipe.bind_sampler_states = nv30_sampler_state_bind; 640 nv30->pipe.delete_sampler_state = nv30_sampler_state_delete; 641 nv30->pipe.set_sampler_textures = nv30_set_sampler_texture; 642 643 nv30->pipe.create_rasterizer_state = nv30_rasterizer_state_create; 644 nv30->pipe.bind_rasterizer_state = nv30_rasterizer_state_bind; 645 nv30->pipe.delete_rasterizer_state = nv30_rasterizer_state_delete; 646 647 nv30->pipe.create_depth_stencil_alpha_state = 648 nv30_depth_stencil_alpha_state_create; 649 nv30->pipe.bind_depth_stencil_alpha_state = 650 nv30_depth_stencil_alpha_state_bind; 651 nv30->pipe.delete_depth_stencil_alpha_state = 652 nv30_depth_stencil_alpha_state_delete; 653 654 nv30->pipe.create_vs_state = nv30_vp_state_create; 655 nv30->pipe.bind_vs_state = nv30_vp_state_bind; 656 nv30->pipe.delete_vs_state = nv30_vp_state_delete; 657 658 nv30->pipe.create_fs_state = nv30_fp_state_create; 659 nv30->pipe.bind_fs_state = nv30_fp_state_bind; 660 nv30->pipe.delete_fs_state = nv30_fp_state_delete; 661 662 nv30->pipe.set_blend_color = nv30_set_blend_color; 663 nv30->pipe.set_clip_state = nv30_set_clip_state; 664 nv30->pipe.set_constant_buffer = nv30_set_constant_buffer; 665 nv30->pipe.set_framebuffer_state = nv30_set_framebuffer_state; 666 nv30->pipe.set_polygon_stipple = nv30_set_polygon_stipple; 667 nv30->pipe.set_scissor_state = nv30_set_scissor_state; 668 nv30->pipe.set_viewport_state = nv30_set_viewport_state; 669 670 nv30->pipe.set_vertex_buffers = nv30_set_vertex_buffers; 671 nv30->pipe.set_vertex_elements = nv30_set_vertex_elements; 672} 673 674