evergreen_compute_internal.c revision 0ea76916e63f8fc556f5e8f5a46c196d317cd5ad
1/* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * on the rights to use, copy, modify, merge, publish, distribute, sub 6 * license, and/or sell copies of the Software, and to permit persons to whom 7 * the Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice (including the next 10 * paragraph) shall be included in all copies or substantial portions of the 11 * Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: 22 * Adam Rak <adam.rak@streamnovation.com> 23 */ 24 25#include <stdlib.h> 26#include <stdio.h> 27 28#include "pipe/p_defines.h" 29#include "pipe/p_state.h" 30#include "pipe/p_context.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_transfer.h" 34#include "util/u_surface.h" 35#include "util/u_pack_color.h" 36#include "util/u_memory.h" 37#include "util/u_inlines.h" 38#include "util/u_framebuffer.h" 39#include "r600.h" 40#include "r600_resource.h" 41#include "r600_shader.h" 42#include "r600_pipe.h" 43#include "r600_formats.h" 44#include "evergreend.h" 45#include "evergreen_compute_internal.h" 46#include "r600_hw_context_priv.h" 47 48int get_compute_resource_num(void) 49{ 50 int num = 0; 51#define DECL_COMPUTE_RESOURCE(name, n) num += n; 52#include "compute_resource.def" 53#undef DECL_COMPUTE_RESOURCE 54 return num; 55} 56 57void evergreen_emit_raw_value( 58 struct evergreen_compute_resource* res, 59 unsigned value) 60{ 61 res->cs[res->cs_end++] = value; 62} 63 64void evergreen_emit_ctx_value(struct r600_context *ctx, unsigned value) 65{ 66 ctx->cs->buf[ctx->cs->cdw++] = value; 67} 68 69void evergreen_mult_reg_set_( 70 struct evergreen_compute_resource* res, 71 int index, 72 u32* array, 73 int size) 74{ 75 int i = 0; 76 77 evergreen_emit_raw_reg_set(res, index, size / 4); 78 79 for (i = 0; i < size; i+=4) { 80 res->cs[res->cs_end++] = array[i / 4]; 81 } 82} 83 84void evergreen_reg_set( 85 struct evergreen_compute_resource* res, 86 unsigned index, 87 unsigned value) 88{ 89 evergreen_emit_raw_reg_set(res, index, 1); 90 res->cs[res->cs_end++] = value; 91} 92 93struct evergreen_compute_resource* get_empty_res( 94 struct r600_pipe_compute* pipe, 95 enum evergreen_compute_resources res_code, 96 int offset_index) 97{ 98 int code_index = -1; 99 int code_size = -1; 100 101 { 102 int i = 0; 103 #define DECL_COMPUTE_RESOURCE(name, n) if (COMPUTE_RESOURCE_ ## name == res_code) {code_index = i; code_size = n;} i += n; 104 #include "compute_resource.def" 105 #undef DECL_COMPUTE_RESOURCE 106 } 107 108 assert(code_index != -1 && "internal error: resouce index not found"); 109 assert(offset_index < code_size && "internal error: overindexing resource"); 110 111 int index = code_index + offset_index; 112 113 struct evergreen_compute_resource* res = &pipe->resources[index]; 114 115 res->enabled = true; 116 res->bo = NULL; 117 res->cs_end = 0; 118 bzero(&res->do_reloc, sizeof(res->do_reloc)); 119 120 return res; 121} 122 123void evergreen_emit_raw_reg_set( 124 struct evergreen_compute_resource* res, 125 unsigned index, 126 int num) 127{ 128 res->enabled = 1; 129 int cs_end = res->cs_end; 130 131 if (index >= EVERGREEN_CONFIG_REG_OFFSET 132 && index < EVERGREEN_CONFIG_REG_END) { 133 res->cs[cs_end] = PKT3C(PKT3_SET_CONFIG_REG, num, 0); 134 res->cs[cs_end+1] = (index - EVERGREEN_CONFIG_REG_OFFSET) >> 2; 135 } else if (index >= EVERGREEN_CONTEXT_REG_OFFSET 136 && index < EVERGREEN_CONTEXT_REG_END) { 137 res->cs[cs_end] = PKT3C(PKT3_SET_CONTEXT_REG, num, 0); 138 res->cs[cs_end+1] = (index - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; 139 } else if (index >= EVERGREEN_RESOURCE_OFFSET 140 && index < EVERGREEN_RESOURCE_END) { 141 res->cs[cs_end] = PKT3C(PKT3_SET_RESOURCE, num, 0); 142 res->cs[cs_end+1] = (index - EVERGREEN_RESOURCE_OFFSET) >> 2; 143 } else if (index >= EVERGREEN_SAMPLER_OFFSET 144 && index < EVERGREEN_SAMPLER_END) { 145 res->cs[cs_end] = PKT3C(PKT3_SET_SAMPLER, num, 0); 146 res->cs[cs_end+1] = (index - EVERGREEN_SAMPLER_OFFSET) >> 2; 147 } else if (index >= EVERGREEN_CTL_CONST_OFFSET 148 && index < EVERGREEN_CTL_CONST_END) { 149 res->cs[cs_end] = PKT3C(PKT3_SET_CTL_CONST, num, 0); 150 res->cs[cs_end+1] = (index - EVERGREEN_CTL_CONST_OFFSET) >> 2; 151 } else if (index >= EVERGREEN_LOOP_CONST_OFFSET 152 && index < EVERGREEN_LOOP_CONST_END) { 153 res->cs[cs_end] = PKT3C(PKT3_SET_LOOP_CONST, num, 0); 154 res->cs[cs_end+1] = (index - EVERGREEN_LOOP_CONST_OFFSET) >> 2; 155 } else if (index >= EVERGREEN_BOOL_CONST_OFFSET 156 && index < EVERGREEN_BOOL_CONST_END) { 157 res->cs[cs_end] = PKT3C(PKT3_SET_BOOL_CONST, num, 0); 158 res->cs[cs_end+1] = (index - EVERGREEN_BOOL_CONST_OFFSET) >> 2; 159 } else { 160 res->cs[cs_end] = PKT0(index, num-1); 161 res->cs_end--; 162 } 163 164 res->cs_end += 2; 165} 166 167void evergreen_emit_force_reloc(struct evergreen_compute_resource* res) 168{ 169 res->do_reloc[res->cs_end] += 1; 170} 171 172void evergreen_emit_ctx_reg_set( 173 struct r600_context *ctx, 174 unsigned index, 175 int num) 176{ 177 178 if (index >= EVERGREEN_CONFIG_REG_OFFSET 179 && index < EVERGREEN_CONFIG_REG_END) { 180 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONFIG_REG, num, 0); 181 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONFIG_REG_OFFSET) >> 2; 182 } else if (index >= EVERGREEN_CONTEXT_REG_OFFSET 183 && index < EVERGREEN_CONTEXT_REG_END) { 184 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CONTEXT_REG, num, 0); 185 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; 186 } else if (index >= EVERGREEN_RESOURCE_OFFSET 187 && index < EVERGREEN_RESOURCE_END) { 188 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_RESOURCE, num, 0); 189 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_RESOURCE_OFFSET) >> 2; 190 } else if (index >= EVERGREEN_SAMPLER_OFFSET 191 && index < EVERGREEN_SAMPLER_END) { 192 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_SAMPLER, num, 0); 193 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_SAMPLER_OFFSET) >> 2; 194 } else if (index >= EVERGREEN_CTL_CONST_OFFSET 195 && index < EVERGREEN_CTL_CONST_END) { 196 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_CTL_CONST, num, 0); 197 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_CTL_CONST_OFFSET) >> 2; 198 } else if (index >= EVERGREEN_LOOP_CONST_OFFSET 199 && index < EVERGREEN_LOOP_CONST_END) { 200 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_LOOP_CONST, num, 0); 201 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_LOOP_CONST_OFFSET) >> 2; 202 } else if (index >= EVERGREEN_BOOL_CONST_OFFSET 203 && index < EVERGREEN_BOOL_CONST_END) { 204 ctx->cs->buf[ctx->cs->cdw++] = PKT3C(PKT3_SET_BOOL_CONST, num, 0); 205 ctx->cs->buf[ctx->cs->cdw++] = (index - EVERGREEN_BOOL_CONST_OFFSET) >> 2; 206 } else { 207 ctx->cs->buf[ctx->cs->cdw++] = PKT0(index, num-1); 208 } 209} 210 211void evergreen_emit_ctx_reloc( 212 struct r600_context *ctx, 213 struct r600_resource *bo, 214 enum radeon_bo_usage usage) 215{ 216 assert(bo); 217 218 ctx->cs->buf[ctx->cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 219 u32 rr = r600_context_bo_reloc(ctx, bo, usage); 220 ctx->cs->buf[ctx->cs->cdw++] = rr; 221} 222 223int evergreen_compute_get_gpu_format( 224 struct number_type_and_format* fmt, 225 struct r600_resource *bo) 226{ 227 switch (bo->b.b.format) 228 { 229 case PIPE_FORMAT_R8_UNORM: 230 case PIPE_FORMAT_R32_UNORM: 231 case PIPE_FORMAT_R32_UINT: 232 fmt->format = V_028C70_COLOR_32; 233 fmt->number_type = V_028C70_NUMBER_UNORM; 234 fmt->num_format_all = 0; 235 break; 236 case PIPE_FORMAT_R32_FLOAT: 237 fmt->format = V_028C70_COLOR_32_FLOAT; 238 fmt->number_type = V_028C70_NUMBER_FLOAT; 239 fmt->num_format_all = 0; 240 break; 241 case PIPE_FORMAT_R32G32B32A32_FLOAT: 242 fmt->format = V_028C70_COLOR_32_32_32_32_FLOAT; 243 fmt->number_type = V_028C70_NUMBER_FLOAT; 244 fmt->num_format_all = 0; 245 break; 246 247 ///TODO: other formats... 248 249 default: 250 return 0; 251 } 252 253 return 1; 254} 255 256void evergreen_set_rat( 257 struct r600_pipe_compute *pipe, 258 int id, 259 struct r600_resource* bo, 260 int start, 261 int size) 262{ 263 assert(id < 12); 264 assert((size & 3) == 0); 265 assert((start & 0xFF) == 0); 266 267 struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state); 268 struct pipe_surface rat_templ; 269 270 COMPUTE_DBG("bind rat: %i \n", id); 271 272 /* Create the RAT surface */ 273 memset(&rat_templ, 0, sizeof(rat_templ)); 274 rat_templ.usage = RADEON_USAGE_READWRITE; 275 rat_templ.format = PIPE_FORMAT_R32_UINT; 276 rat_templ.u.tex.level = 0; 277 rat_templ.u.tex.first_layer = 0; 278 rat_templ.u.tex.last_layer = 0; 279 280 /* Add the RAT the list of color buffers */ 281 pipe->ctx->framebuffer.cbufs[id] = pipe->ctx->context.create_surface( 282 (struct pipe_context *)pipe->ctx, 283 (struct pipe_resource *)bo, &rat_templ); 284 285 /* Update the number of color buffers */ 286 pipe->ctx->nr_cbufs = MAX2(id + 1, pipe->ctx->nr_cbufs); 287 288 /* Update the cb_target_mask 289 * XXX: I think this is a potential spot for bugs once we start doing 290 * GL interop. cb_target_mask may be modified in the 3D sections 291 * of this driver. */ 292 pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4)); 293 294 295 /* Get the CB register writes for the RAT */ 296 evergreen_cb(pipe->ctx, state, &pipe->ctx->framebuffer, id); 297 298 /* Add the register blocks to the dirty list */ 299 free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 300 pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER] = state; 301 r600_context_pipe_state_set(pipe->ctx, state); 302} 303 304void evergreen_set_lds( 305 struct r600_pipe_compute *pipe, 306 int num_lds, 307 int size, 308 int num_waves) 309{ 310 struct evergreen_compute_resource* res = 311 get_empty_res(pipe, COMPUTE_RESOURCE_LDS, 0); 312 313 if (pipe->ctx->chip_class < CAYMAN) { 314 evergreen_reg_set(res, R_008E2C_SQ_LDS_RESOURCE_MGMT, 315 S_008E2C_NUM_LS_LDS(num_lds)); 316 } else { 317 evergreen_reg_set(res, CM_R_0286FC_SPI_LDS_MGMT, 318 S_0286FC_NUM_LS_LDS(num_lds)); 319 } 320 evergreen_reg_set(res, CM_R_0288E8_SQ_LDS_ALLOC, size | num_waves << 14); 321} 322 323void evergreen_set_gds( 324 struct r600_pipe_compute *pipe, 325 uint32_t addr, 326 uint32_t size) 327{ 328 struct evergreen_compute_resource* res = 329 get_empty_res(pipe, COMPUTE_RESOURCE_GDS, 0); 330 331 evergreen_reg_set(res, R_028728_GDS_ORDERED_WAVE_PER_SE, 1); 332 evergreen_reg_set(res, R_028720_GDS_ADDR_BASE, addr); 333 evergreen_reg_set(res, R_028724_GDS_ADDR_SIZE, size); 334} 335 336void evergreen_set_export( 337 struct r600_pipe_compute *pipe, 338 struct r600_resource* bo, 339 int offset, int size) 340{ 341 #define SX_MEMORY_EXPORT_BASE 0x9010 342 #define SX_MEMORY_EXPORT_SIZE 0x9014 343 344 struct evergreen_compute_resource* res = 345 get_empty_res(pipe, COMPUTE_RESOURCE_EXPORT, 0); 346 347 evergreen_reg_set(res, SX_MEMORY_EXPORT_SIZE, size); 348 349 if (size) { 350 evergreen_reg_set(res, SX_MEMORY_EXPORT_BASE, offset); 351 res->bo = bo; 352 res->usage = RADEON_USAGE_WRITE; 353 res->coher_bo_size = size; 354 res->flags = 0; 355 } 356} 357 358void evergreen_set_loop_const( 359 struct r600_pipe_compute *pipe, 360 int id, int count, int init, int inc) { 361 362 struct evergreen_compute_resource* res = 363 get_empty_res(pipe, COMPUTE_RESOURCE_LOOP, id); 364 365 assert(id < 32); 366 assert(count <= 0xFFF); 367 assert(init <= 0xFF); 368 assert(inc <= 0xFF); 369 370 /* Compute shaders use LOOP_CONST registers SQ_LOOP_CONST_160 to 371 * SQ_LOOP_CONST_191 */ 372 evergreen_reg_set(res, R_03A200_SQ_LOOP_CONST_0 + (160 * 4) + (id * 4), 373 count | init << 12 | inc << 24); 374} 375 376void evergreen_set_tmp_ring( 377 struct r600_pipe_compute *pipe, 378 struct r600_resource* bo, 379 int offset, int size, int se) 380{ 381 #define SQ_LSTMP_RING_BASE 0x00008e10 382 #define SQ_LSTMP_RING_SIZE 0x00008e14 383 #define GRBM_GFX_INDEX 0x802C 384 #define INSTANCE_INDEX(x) ((x) << 0) 385 #define SE_INDEX(x) ((x) << 16) 386 #define INSTANCE_BROADCAST_WRITES (1 << 30) 387 #define SE_BROADCAST_WRITES (1 << 31) 388 389 struct evergreen_compute_resource* res = 390 get_empty_res(pipe, COMPUTE_RESOURCE_TMPRING, se); 391 392 evergreen_reg_set(res, 393 GRBM_GFX_INDEX,INSTANCE_INDEX(0) 394 | SE_INDEX(se) 395 | INSTANCE_BROADCAST_WRITES); 396 evergreen_reg_set(res, SQ_LSTMP_RING_SIZE, size); 397 398 if (size) { 399 assert(bo); 400 401 evergreen_reg_set(res, SQ_LSTMP_RING_BASE, offset); 402 res->bo = bo; 403 res->usage = RADEON_USAGE_WRITE; 404 res->coher_bo_size = 0; 405 res->flags = 0; 406 } 407 408 if (size) { 409 evergreen_emit_force_reloc(res); 410 } 411 412 evergreen_reg_set(res, 413 GRBM_GFX_INDEX,INSTANCE_INDEX(0) 414 | SE_INDEX(0) 415 | INSTANCE_BROADCAST_WRITES 416 | SE_BROADCAST_WRITES); 417} 418 419static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 420{ 421 if (R600_BIG_ENDIAN) { 422 switch(colorformat) { 423 case V_028C70_COLOR_4_4: 424 return ENDIAN_NONE; 425 426 /* 8-bit buffers. */ 427 case V_028C70_COLOR_8: 428 return ENDIAN_NONE; 429 430 /* 16-bit buffers. */ 431 case V_028C70_COLOR_5_6_5: 432 case V_028C70_COLOR_1_5_5_5: 433 case V_028C70_COLOR_4_4_4_4: 434 case V_028C70_COLOR_16: 435 case V_028C70_COLOR_8_8: 436 return ENDIAN_8IN16; 437 438 /* 32-bit buffers. */ 439 case V_028C70_COLOR_8_8_8_8: 440 case V_028C70_COLOR_2_10_10_10: 441 case V_028C70_COLOR_8_24: 442 case V_028C70_COLOR_24_8: 443 case V_028C70_COLOR_32_FLOAT: 444 case V_028C70_COLOR_16_16_FLOAT: 445 case V_028C70_COLOR_16_16: 446 return ENDIAN_8IN32; 447 448 /* 64-bit buffers. */ 449 case V_028C70_COLOR_16_16_16_16: 450 case V_028C70_COLOR_16_16_16_16_FLOAT: 451 return ENDIAN_8IN16; 452 453 case V_028C70_COLOR_32_32_FLOAT: 454 case V_028C70_COLOR_32_32: 455 case V_028C70_COLOR_X24_8_32_FLOAT: 456 return ENDIAN_8IN32; 457 458 /* 96-bit buffers. */ 459 case V_028C70_COLOR_32_32_32_FLOAT: 460 /* 128-bit buffers. */ 461 case V_028C70_COLOR_32_32_32_32_FLOAT: 462 case V_028C70_COLOR_32_32_32_32: 463 return ENDIAN_8IN32; 464 default: 465 return ENDIAN_NONE; /* Unsupported. */ 466 } 467 } else { 468 return ENDIAN_NONE; 469 } 470} 471 472static unsigned r600_tex_dim(unsigned dim) 473{ 474 switch (dim) { 475 default: 476 case PIPE_TEXTURE_1D: 477 return V_030000_SQ_TEX_DIM_1D; 478 case PIPE_TEXTURE_1D_ARRAY: 479 return V_030000_SQ_TEX_DIM_1D_ARRAY; 480 case PIPE_TEXTURE_2D: 481 case PIPE_TEXTURE_RECT: 482 return V_030000_SQ_TEX_DIM_2D; 483 case PIPE_TEXTURE_2D_ARRAY: 484 return V_030000_SQ_TEX_DIM_2D_ARRAY; 485 case PIPE_TEXTURE_3D: 486 return V_030000_SQ_TEX_DIM_3D; 487 case PIPE_TEXTURE_CUBE: 488 return V_030000_SQ_TEX_DIM_CUBEMAP; 489 } 490} 491 492void evergreen_set_vtx_resource( 493 struct r600_pipe_compute *pipe, 494 struct r600_resource* bo, 495 int id, uint64_t offset, int writable) 496{ 497 assert(id < 16); 498 uint32_t sq_vtx_constant_word2, sq_vtx_constant_word3, sq_vtx_constant_word4; 499 struct number_type_and_format fmt; 500 uint64_t va; 501 502 fmt.format = 0; 503 504 assert(bo->b.b.height0 <= 1); 505 assert(bo->b.b.depth0 <= 1); 506 507 int e = evergreen_compute_get_gpu_format(&fmt, bo); 508 509 assert(e && "unknown format"); 510 511 struct evergreen_compute_resource* res = 512 get_empty_res(pipe, COMPUTE_RESOURCE_VERT, id); 513 514 unsigned size = bo->b.b.width0; 515 unsigned stride = 1; 516 517// size = (size * util_format_get_blockwidth(bo->b.b.b.format) * 518// util_format_get_blocksize(bo->b.b.b.format)); 519 520 va = r600_resource_va(&pipe->ctx->screen->screen, &bo->b.b) + offset; 521 522 COMPUTE_DBG("id: %i vtx size: %i byte, width0: %i elem\n", 523 id, size, bo->b.b.width0); 524 525 sq_vtx_constant_word2 = 526 S_030008_BASE_ADDRESS_HI(va >> 32) | 527 S_030008_STRIDE(stride) | 528 S_030008_DATA_FORMAT(fmt.format) | 529 S_030008_NUM_FORMAT_ALL(fmt.num_format_all) | 530 S_030008_ENDIAN_SWAP(0); 531 532 COMPUTE_DBG("%08X %i %i %i %i\n", sq_vtx_constant_word2, offset, 533 stride, fmt.format, fmt.num_format_all); 534 535 sq_vtx_constant_word3 = 536 S_03000C_DST_SEL_X(0) | 537 S_03000C_DST_SEL_Y(1) | 538 S_03000C_DST_SEL_Z(2) | 539 S_03000C_DST_SEL_W(3); 540 541 sq_vtx_constant_word4 = 0; 542 543 evergreen_emit_raw_value(res, PKT3C(PKT3_SET_RESOURCE, 8, 0)); 544 evergreen_emit_raw_value(res, (id+816)*32 >> 2); 545 evergreen_emit_raw_value(res, (unsigned)((va) & 0xffffffff)); 546 evergreen_emit_raw_value(res, size - 1); 547 evergreen_emit_raw_value(res, sq_vtx_constant_word2); 548 evergreen_emit_raw_value(res, sq_vtx_constant_word3); 549 evergreen_emit_raw_value(res, sq_vtx_constant_word4); 550 evergreen_emit_raw_value(res, 0); 551 evergreen_emit_raw_value(res, 0); 552 evergreen_emit_raw_value(res, S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER)); 553 554 res->bo = bo; 555 556 if (writable) { 557 res->usage = RADEON_USAGE_READWRITE; 558 } 559 else { 560 res->usage = RADEON_USAGE_READ; 561 } 562 563 res->coher_bo_size = size; 564 565 r600_inval_vertex_cache(pipe->ctx); 566 /* XXX: Do we really need to invalidate the texture cache here? 567 * r600_inval_vertex_cache() will invalidate the texture cache 568 * if the chip does not have a vertex cache. 569 */ 570 r600_inval_texture_cache(pipe->ctx); 571} 572 573void evergreen_set_tex_resource( 574 struct r600_pipe_compute *pipe, 575 struct r600_pipe_sampler_view* view, 576 int id) 577{ 578 struct evergreen_compute_resource* res = 579 get_empty_res(pipe, COMPUTE_RESOURCE_TEX, id); 580 struct r600_resource_texture *tmp = 581 (struct r600_resource_texture*)view->base.texture; 582 583 unsigned format, endian; 584 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 585 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 586 unsigned height, depth; 587 588 swizzle[0] = 0; 589 swizzle[1] = 1; 590 swizzle[2] = 2; 591 swizzle[3] = 3; 592 593 format = r600_translate_texformat((struct pipe_screen *)pipe->ctx->screen, 594 view->base.format, swizzle, &word4, &yuv_format); 595 596 if (format == ~0) { 597 format = 0; 598 } 599 600 endian = r600_colorformat_endian_swap(format); 601 602 height = view->base.texture->height0; 603 depth = view->base.texture->depth0; 604 605 pitch = align(tmp->pitch_in_blocks[0] * 606 util_format_get_blockwidth(tmp->real_format), 8); 607 array_mode = tmp->array_mode[0]; 608 tile_type = tmp->tile_type; 609 610 assert(view->base.texture->target != PIPE_TEXTURE_1D_ARRAY); 611 assert(view->base.texture->target != PIPE_TEXTURE_2D_ARRAY); 612 613 evergreen_emit_raw_value(res, PKT3C(PKT3_SET_RESOURCE, 8, 0)); 614 evergreen_emit_raw_value(res, (id+816)*32 >> 2); ///TODO: check this line 615 evergreen_emit_raw_value(res, 616 (S_030000_DIM(r600_tex_dim(view->base.texture->target)) | 617 S_030000_PITCH((pitch / 8) - 1) | 618 S_030000_NON_DISP_TILING_ORDER(tile_type) | 619 S_030000_TEX_WIDTH(view->base.texture->width0 - 1))); 620 evergreen_emit_raw_value(res, (S_030004_TEX_HEIGHT(height - 1) | 621 S_030004_TEX_DEPTH(depth - 1) | 622 S_030004_ARRAY_MODE(array_mode))); 623 evergreen_emit_raw_value(res, tmp->offset[0] >> 8); 624 evergreen_emit_raw_value(res, tmp->offset[0] >> 8); 625 evergreen_emit_raw_value(res, (word4 | 626 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 627 S_030010_ENDIAN_SWAP(endian) | 628 S_030010_BASE_LEVEL(0))); 629 evergreen_emit_raw_value(res, (S_030014_LAST_LEVEL(0) | 630 S_030014_BASE_ARRAY(0) | 631 S_030014_LAST_ARRAY(0))); 632 evergreen_emit_raw_value(res, (S_030018_MAX_ANISO(4 /* max 16 samples */))); 633 evergreen_emit_raw_value(res, 634 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) 635 | S_03001C_DATA_FORMAT(format)); 636 637 res->bo = (struct r600_resource*)view->base.texture; 638 639 res->usage = RADEON_USAGE_READ; 640 641 res->coher_bo_size = tmp->offset[0] + util_format_get_blockwidth(tmp->real_format)*view->base.texture->width0*height*depth; 642 643 r600_inval_texture_cache(pipe->ctx); 644 645 evergreen_emit_force_reloc(res); 646 evergreen_emit_force_reloc(res); 647} 648 649void evergreen_set_sampler_resource( 650 struct r600_pipe_compute *pipe, 651 struct compute_sampler_state *sampler, 652 int id) 653{ 654 struct evergreen_compute_resource* res = 655 get_empty_res(pipe, COMPUTE_RESOURCE_SAMPLER, id); 656 657 unsigned aniso_flag_offset = sampler->state.max_anisotropy > 1 ? 2 : 0; 658 659 evergreen_emit_raw_value(res, PKT3C(PKT3_SET_SAMPLER, 3, 0)); 660 evergreen_emit_raw_value(res, (id + 90)*3); 661 evergreen_emit_raw_value(res, 662 S_03C000_CLAMP_X(r600_tex_wrap(sampler->state.wrap_s)) | 663 S_03C000_CLAMP_Y(r600_tex_wrap(sampler->state.wrap_t)) | 664 S_03C000_CLAMP_Z(r600_tex_wrap(sampler->state.wrap_r)) | 665 S_03C000_XY_MAG_FILTER(r600_tex_filter(sampler->state.mag_img_filter) | aniso_flag_offset) | 666 S_03C000_XY_MIN_FILTER(r600_tex_filter(sampler->state.min_img_filter) | aniso_flag_offset) | 667 S_03C000_BORDER_COLOR_TYPE(V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK) 668 ); 669 evergreen_emit_raw_value(res, 670 S_03C004_MIN_LOD(S_FIXED(CLAMP(sampler->state.min_lod, 0, 15), 8)) | 671 S_03C004_MAX_LOD(S_FIXED(CLAMP(sampler->state.max_lod, 0, 15), 8)) 672 ); 673 evergreen_emit_raw_value(res, 674 S_03C008_LOD_BIAS(S_FIXED(CLAMP(sampler->state.lod_bias, -16, 16), 8)) | 675 (sampler->state.seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) | 676 S_03C008_TYPE(1) 677 ); 678} 679 680void evergreen_set_const_cache( 681 struct r600_pipe_compute *pipe, 682 int cache_id, 683 struct r600_resource* cbo, 684 int size, int offset) 685{ 686 #define SQ_ALU_CONST_BUFFER_SIZE_LS_0 0x00028fc0 687 #define SQ_ALU_CONST_CACHE_LS_0 0x00028f40 688 689 struct evergreen_compute_resource* res = 690 get_empty_res(pipe, COMPUTE_RESOURCE_CONST_MEM, cache_id); 691 692 assert(size < 0x200); 693 assert((offset & 0xFF) == 0); 694 assert(cache_id < 16); 695 696 evergreen_reg_set(res, SQ_ALU_CONST_BUFFER_SIZE_LS_0 + cache_id*4, size); 697 evergreen_reg_set(res, SQ_ALU_CONST_CACHE_LS_0 + cache_id*4, offset >> 8); 698 res->bo = cbo; 699 res->usage = RADEON_USAGE_READ; 700 res->coher_bo_size = size; 701 702 r600_inval_shader_cache(pipe->ctx); 703} 704 705struct r600_resource* r600_compute_buffer_alloc_vram( 706 struct r600_screen *screen, 707 unsigned size) 708{ 709 assert(size); 710 711 struct pipe_resource * buffer = pipe_buffer_create( 712 (struct pipe_screen*) screen, 713 PIPE_BIND_CUSTOM, 714 PIPE_USAGE_IMMUTABLE, 715 size); 716 717 return (struct r600_resource *)buffer; 718} 719