evergreen_state.c revision c0c979eebc076b95cc8d18a013ce2968fe6311ad 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24/* TODO:
25 *	- fix mask for depth control & cull for query
26 */
27#include <stdio.h>
28#include <errno.h>
29#include "pipe/p_defines.h"
30#include "pipe/p_state.h"
31#include "pipe/p_context.h"
32#include "tgsi/tgsi_scan.h"
33#include "tgsi/tgsi_parse.h"
34#include "tgsi/tgsi_util.h"
35#include "util/u_blitter.h"
36#include "util/u_double_list.h"
37#include "util/u_transfer.h"
38#include "util/u_surface.h"
39#include "util/u_pack_color.h"
40#include "util/u_memory.h"
41#include "util/u_inlines.h"
42#include "util/u_framebuffer.h"
43#include "pipebuffer/pb_buffer.h"
44#include "r600.h"
45#include "evergreend.h"
46#include "r600_resource.h"
47#include "r600_shader.h"
48#include "r600_pipe.h"
49#include "r600_formats.h"
50
51static uint32_t eg_num_banks(uint32_t nbanks)
52{
53	switch (nbanks) {
54	case 2:
55		return 0;
56	case 4:
57		return 1;
58	case 8:
59	default:
60		return 2;
61	case 16:
62		return 3;
63	}
64}
65
66
67static unsigned eg_tile_split(unsigned tile_split)
68{
69	switch (tile_split) {
70	case 64:	tile_split = 0;	break;
71	case 128:	tile_split = 1;	break;
72	case 256:	tile_split = 2;	break;
73	case 512:	tile_split = 3;	break;
74	default:
75	case 1024:	tile_split = 4;	break;
76	case 2048:	tile_split = 5;	break;
77	case 4096:	tile_split = 6;	break;
78	}
79	return tile_split;
80}
81
82static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
83{
84	switch (macro_tile_aspect) {
85	default:
86	case 1:	macro_tile_aspect = 0;	break;
87	case 2:	macro_tile_aspect = 1;	break;
88	case 4:	macro_tile_aspect = 2;	break;
89	case 8:	macro_tile_aspect = 3;	break;
90	}
91	return macro_tile_aspect;
92}
93
94static unsigned eg_bank_wh(unsigned bankwh)
95{
96	switch (bankwh) {
97	default:
98	case 1:	bankwh = 0;	break;
99	case 2:	bankwh = 1;	break;
100	case 4:	bankwh = 2;	break;
101	case 8:	bankwh = 3;	break;
102	}
103	return bankwh;
104}
105
106static uint32_t r600_translate_blend_function(int blend_func)
107{
108	switch (blend_func) {
109	case PIPE_BLEND_ADD:
110		return V_028780_COMB_DST_PLUS_SRC;
111	case PIPE_BLEND_SUBTRACT:
112		return V_028780_COMB_SRC_MINUS_DST;
113	case PIPE_BLEND_REVERSE_SUBTRACT:
114		return V_028780_COMB_DST_MINUS_SRC;
115	case PIPE_BLEND_MIN:
116		return V_028780_COMB_MIN_DST_SRC;
117	case PIPE_BLEND_MAX:
118		return V_028780_COMB_MAX_DST_SRC;
119	default:
120		R600_ERR("Unknown blend function %d\n", blend_func);
121		assert(0);
122		break;
123	}
124	return 0;
125}
126
127static uint32_t r600_translate_blend_factor(int blend_fact)
128{
129	switch (blend_fact) {
130	case PIPE_BLENDFACTOR_ONE:
131		return V_028780_BLEND_ONE;
132	case PIPE_BLENDFACTOR_SRC_COLOR:
133		return V_028780_BLEND_SRC_COLOR;
134	case PIPE_BLENDFACTOR_SRC_ALPHA:
135		return V_028780_BLEND_SRC_ALPHA;
136	case PIPE_BLENDFACTOR_DST_ALPHA:
137		return V_028780_BLEND_DST_ALPHA;
138	case PIPE_BLENDFACTOR_DST_COLOR:
139		return V_028780_BLEND_DST_COLOR;
140	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
141		return V_028780_BLEND_SRC_ALPHA_SATURATE;
142	case PIPE_BLENDFACTOR_CONST_COLOR:
143		return V_028780_BLEND_CONST_COLOR;
144	case PIPE_BLENDFACTOR_CONST_ALPHA:
145		return V_028780_BLEND_CONST_ALPHA;
146	case PIPE_BLENDFACTOR_ZERO:
147		return V_028780_BLEND_ZERO;
148	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
149		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
150	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
151		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
152	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
153		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
154	case PIPE_BLENDFACTOR_INV_DST_COLOR:
155		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
156	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
157		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
158	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
159		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
160	case PIPE_BLENDFACTOR_SRC1_COLOR:
161		return V_028780_BLEND_SRC1_COLOR;
162	case PIPE_BLENDFACTOR_SRC1_ALPHA:
163		return V_028780_BLEND_SRC1_ALPHA;
164	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
165		return V_028780_BLEND_INV_SRC1_COLOR;
166	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
167		return V_028780_BLEND_INV_SRC1_ALPHA;
168	default:
169		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
170		assert(0);
171		break;
172	}
173	return 0;
174}
175
176static uint32_t r600_translate_stencil_op(int s_op)
177{
178	switch (s_op) {
179	case PIPE_STENCIL_OP_KEEP:
180		return V_028800_STENCIL_KEEP;
181	case PIPE_STENCIL_OP_ZERO:
182		return V_028800_STENCIL_ZERO;
183	case PIPE_STENCIL_OP_REPLACE:
184		return V_028800_STENCIL_REPLACE;
185	case PIPE_STENCIL_OP_INCR:
186		return V_028800_STENCIL_INCR;
187	case PIPE_STENCIL_OP_DECR:
188		return V_028800_STENCIL_DECR;
189	case PIPE_STENCIL_OP_INCR_WRAP:
190		return V_028800_STENCIL_INCR_WRAP;
191	case PIPE_STENCIL_OP_DECR_WRAP:
192		return V_028800_STENCIL_DECR_WRAP;
193	case PIPE_STENCIL_OP_INVERT:
194		return V_028800_STENCIL_INVERT;
195	default:
196		R600_ERR("Unknown stencil op %d", s_op);
197		assert(0);
198		break;
199	}
200	return 0;
201}
202
203static uint32_t r600_translate_fill(uint32_t func)
204{
205	switch(func) {
206	case PIPE_POLYGON_MODE_FILL:
207		return 2;
208	case PIPE_POLYGON_MODE_LINE:
209		return 1;
210	case PIPE_POLYGON_MODE_POINT:
211		return 0;
212	default:
213		assert(0);
214		return 0;
215	}
216}
217
218/* translates straight */
219static uint32_t r600_translate_ds_func(int func)
220{
221	return func;
222}
223
224static unsigned r600_tex_wrap(unsigned wrap)
225{
226	switch (wrap) {
227	default:
228	case PIPE_TEX_WRAP_REPEAT:
229		return V_03C000_SQ_TEX_WRAP;
230	case PIPE_TEX_WRAP_CLAMP:
231		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
232	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
233		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
234	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
235		return V_03C000_SQ_TEX_CLAMP_BORDER;
236	case PIPE_TEX_WRAP_MIRROR_REPEAT:
237		return V_03C000_SQ_TEX_MIRROR;
238	case PIPE_TEX_WRAP_MIRROR_CLAMP:
239		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
240	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
241		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
242	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
243		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
244	}
245}
246
247static unsigned r600_tex_filter(unsigned filter)
248{
249	switch (filter) {
250	default:
251	case PIPE_TEX_FILTER_NEAREST:
252		return V_03C000_SQ_TEX_XY_FILTER_POINT;
253	case PIPE_TEX_FILTER_LINEAR:
254		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
255	}
256}
257
258static unsigned r600_tex_mipfilter(unsigned filter)
259{
260	switch (filter) {
261	case PIPE_TEX_MIPFILTER_NEAREST:
262		return V_03C000_SQ_TEX_Z_FILTER_POINT;
263	case PIPE_TEX_MIPFILTER_LINEAR:
264		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
265	default:
266	case PIPE_TEX_MIPFILTER_NONE:
267		return V_03C000_SQ_TEX_Z_FILTER_NONE;
268	}
269}
270
271static unsigned r600_tex_compare(unsigned compare)
272{
273	switch (compare) {
274	default:
275	case PIPE_FUNC_NEVER:
276		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
277	case PIPE_FUNC_LESS:
278		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
279	case PIPE_FUNC_EQUAL:
280		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
281	case PIPE_FUNC_LEQUAL:
282		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
283	case PIPE_FUNC_GREATER:
284		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
285	case PIPE_FUNC_NOTEQUAL:
286		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
287	case PIPE_FUNC_GEQUAL:
288		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
289	case PIPE_FUNC_ALWAYS:
290		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
291	}
292}
293
294static unsigned r600_tex_dim(unsigned dim)
295{
296	switch (dim) {
297	default:
298	case PIPE_TEXTURE_1D:
299		return V_030000_SQ_TEX_DIM_1D;
300	case PIPE_TEXTURE_1D_ARRAY:
301		return V_030000_SQ_TEX_DIM_1D_ARRAY;
302	case PIPE_TEXTURE_2D:
303	case PIPE_TEXTURE_RECT:
304		return V_030000_SQ_TEX_DIM_2D;
305	case PIPE_TEXTURE_2D_ARRAY:
306		return V_030000_SQ_TEX_DIM_2D_ARRAY;
307	case PIPE_TEXTURE_3D:
308		return V_030000_SQ_TEX_DIM_3D;
309	case PIPE_TEXTURE_CUBE:
310		return V_030000_SQ_TEX_DIM_CUBEMAP;
311	}
312}
313
314static uint32_t r600_translate_dbformat(enum pipe_format format)
315{
316	switch (format) {
317	case PIPE_FORMAT_Z16_UNORM:
318		return V_028040_Z_16;
319	case PIPE_FORMAT_Z24X8_UNORM:
320	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
321		return V_028040_Z_24;
322	case PIPE_FORMAT_Z32_FLOAT:
323	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
324		return V_028040_Z_32_FLOAT;
325	default:
326		return ~0U;
327	}
328}
329
330static uint32_t r600_translate_colorswap(enum pipe_format format)
331{
332	switch (format) {
333	/* 8-bit buffers. */
334	case PIPE_FORMAT_L4A4_UNORM:
335	case PIPE_FORMAT_A4R4_UNORM:
336		return V_028C70_SWAP_ALT;
337
338	case PIPE_FORMAT_A8_UNORM:
339	case PIPE_FORMAT_A8_UINT:
340	case PIPE_FORMAT_A8_SINT:
341	case PIPE_FORMAT_R4A4_UNORM:
342		return V_028C70_SWAP_ALT_REV;
343	case PIPE_FORMAT_I8_UNORM:
344	case PIPE_FORMAT_L8_UNORM:
345	case PIPE_FORMAT_I8_UINT:
346	case PIPE_FORMAT_I8_SINT:
347	case PIPE_FORMAT_L8_UINT:
348	case PIPE_FORMAT_L8_SINT:
349	case PIPE_FORMAT_L8_SRGB:
350	case PIPE_FORMAT_R8_UNORM:
351	case PIPE_FORMAT_R8_SNORM:
352	case PIPE_FORMAT_R8_UINT:
353	case PIPE_FORMAT_R8_SINT:
354		return V_028C70_SWAP_STD;
355
356	/* 16-bit buffers. */
357	case PIPE_FORMAT_B5G6R5_UNORM:
358		return V_028C70_SWAP_STD_REV;
359
360	case PIPE_FORMAT_B5G5R5A1_UNORM:
361	case PIPE_FORMAT_B5G5R5X1_UNORM:
362		return V_028C70_SWAP_ALT;
363
364	case PIPE_FORMAT_B4G4R4A4_UNORM:
365	case PIPE_FORMAT_B4G4R4X4_UNORM:
366		return V_028C70_SWAP_ALT;
367
368	case PIPE_FORMAT_Z16_UNORM:
369		return V_028C70_SWAP_STD;
370
371	case PIPE_FORMAT_L8A8_UNORM:
372	case PIPE_FORMAT_L8A8_UINT:
373	case PIPE_FORMAT_L8A8_SINT:
374	case PIPE_FORMAT_L8A8_SRGB:
375		return V_028C70_SWAP_ALT;
376	case PIPE_FORMAT_R8G8_UNORM:
377	case PIPE_FORMAT_R8G8_UINT:
378	case PIPE_FORMAT_R8G8_SINT:
379		return V_028C70_SWAP_STD;
380
381	case PIPE_FORMAT_R16_UNORM:
382	case PIPE_FORMAT_R16_UINT:
383	case PIPE_FORMAT_R16_SINT:
384	case PIPE_FORMAT_R16_FLOAT:
385		return V_028C70_SWAP_STD;
386
387	/* 32-bit buffers. */
388	case PIPE_FORMAT_A8B8G8R8_SRGB:
389		return V_028C70_SWAP_STD_REV;
390	case PIPE_FORMAT_B8G8R8A8_SRGB:
391		return V_028C70_SWAP_ALT;
392
393	case PIPE_FORMAT_B8G8R8A8_UNORM:
394	case PIPE_FORMAT_B8G8R8X8_UNORM:
395		return V_028C70_SWAP_ALT;
396
397	case PIPE_FORMAT_A8R8G8B8_UNORM:
398	case PIPE_FORMAT_X8R8G8B8_UNORM:
399		return V_028C70_SWAP_ALT_REV;
400	case PIPE_FORMAT_R8G8B8A8_SNORM:
401	case PIPE_FORMAT_R8G8B8A8_UNORM:
402	case PIPE_FORMAT_R8G8B8A8_SSCALED:
403	case PIPE_FORMAT_R8G8B8A8_USCALED:
404	case PIPE_FORMAT_R8G8B8A8_SINT:
405	case PIPE_FORMAT_R8G8B8A8_UINT:
406	case PIPE_FORMAT_R8G8B8X8_UNORM:
407		return V_028C70_SWAP_STD;
408
409	case PIPE_FORMAT_A8B8G8R8_UNORM:
410	case PIPE_FORMAT_X8B8G8R8_UNORM:
411	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
412		return V_028C70_SWAP_STD_REV;
413
414	case PIPE_FORMAT_Z24X8_UNORM:
415	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
416		return V_028C70_SWAP_STD;
417
418	case PIPE_FORMAT_X8Z24_UNORM:
419	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
420		return V_028C70_SWAP_STD;
421
422	case PIPE_FORMAT_R10G10B10A2_UNORM:
423	case PIPE_FORMAT_R10G10B10X2_SNORM:
424	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
425		return V_028C70_SWAP_STD;
426
427	case PIPE_FORMAT_B10G10R10A2_UNORM:
428	case PIPE_FORMAT_B10G10R10A2_UINT:
429		return V_028C70_SWAP_ALT;
430
431	case PIPE_FORMAT_R11G11B10_FLOAT:
432	case PIPE_FORMAT_R32_FLOAT:
433	case PIPE_FORMAT_R32_UINT:
434	case PIPE_FORMAT_R32_SINT:
435	case PIPE_FORMAT_Z32_FLOAT:
436	case PIPE_FORMAT_R16G16_FLOAT:
437	case PIPE_FORMAT_R16G16_UNORM:
438	case PIPE_FORMAT_R16G16_UINT:
439	case PIPE_FORMAT_R16G16_SINT:
440		return V_028C70_SWAP_STD;
441
442	/* 64-bit buffers. */
443	case PIPE_FORMAT_R32G32_FLOAT:
444	case PIPE_FORMAT_R32G32_UINT:
445	case PIPE_FORMAT_R32G32_SINT:
446	case PIPE_FORMAT_R16G16B16A16_UNORM:
447	case PIPE_FORMAT_R16G16B16A16_SNORM:
448	case PIPE_FORMAT_R16G16B16A16_USCALED:
449	case PIPE_FORMAT_R16G16B16A16_SSCALED:
450	case PIPE_FORMAT_R16G16B16A16_UINT:
451	case PIPE_FORMAT_R16G16B16A16_SINT:
452	case PIPE_FORMAT_R16G16B16A16_FLOAT:
453	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
454
455	/* 128-bit buffers. */
456	case PIPE_FORMAT_R32G32B32A32_FLOAT:
457	case PIPE_FORMAT_R32G32B32A32_SNORM:
458	case PIPE_FORMAT_R32G32B32A32_UNORM:
459	case PIPE_FORMAT_R32G32B32A32_SSCALED:
460	case PIPE_FORMAT_R32G32B32A32_USCALED:
461	case PIPE_FORMAT_R32G32B32A32_SINT:
462	case PIPE_FORMAT_R32G32B32A32_UINT:
463		return V_028C70_SWAP_STD;
464	default:
465		R600_ERR("unsupported colorswap format %d\n", format);
466		return ~0U;
467	}
468	return ~0U;
469}
470
471static uint32_t r600_translate_colorformat(enum pipe_format format)
472{
473	switch (format) {
474	/* 8-bit buffers. */
475	case PIPE_FORMAT_A8_UNORM:
476	case PIPE_FORMAT_A8_UINT:
477	case PIPE_FORMAT_A8_SINT:
478	case PIPE_FORMAT_I8_UNORM:
479	case PIPE_FORMAT_I8_UINT:
480	case PIPE_FORMAT_I8_SINT:
481	case PIPE_FORMAT_L8_UNORM:
482	case PIPE_FORMAT_L8_UINT:
483	case PIPE_FORMAT_L8_SINT:
484	case PIPE_FORMAT_L8_SRGB:
485	case PIPE_FORMAT_R8_UNORM:
486	case PIPE_FORMAT_R8_SNORM:
487	case PIPE_FORMAT_R8_UINT:
488	case PIPE_FORMAT_R8_SINT:
489		return V_028C70_COLOR_8;
490
491	/* 16-bit buffers. */
492	case PIPE_FORMAT_B5G6R5_UNORM:
493		return V_028C70_COLOR_5_6_5;
494
495	case PIPE_FORMAT_B5G5R5A1_UNORM:
496	case PIPE_FORMAT_B5G5R5X1_UNORM:
497		return V_028C70_COLOR_1_5_5_5;
498
499	case PIPE_FORMAT_B4G4R4A4_UNORM:
500	case PIPE_FORMAT_B4G4R4X4_UNORM:
501		return V_028C70_COLOR_4_4_4_4;
502
503	case PIPE_FORMAT_Z16_UNORM:
504		return V_028C70_COLOR_16;
505
506	case PIPE_FORMAT_L8A8_UNORM:
507	case PIPE_FORMAT_L8A8_UINT:
508	case PIPE_FORMAT_L8A8_SINT:
509	case PIPE_FORMAT_L8A8_SRGB:
510	case PIPE_FORMAT_R8G8_UNORM:
511	case PIPE_FORMAT_R8G8_UINT:
512	case PIPE_FORMAT_R8G8_SINT:
513		return V_028C70_COLOR_8_8;
514
515	case PIPE_FORMAT_R16_UNORM:
516	case PIPE_FORMAT_R16_UINT:
517	case PIPE_FORMAT_R16_SINT:
518		return V_028C70_COLOR_16;
519
520	case PIPE_FORMAT_R16_FLOAT:
521		return V_028C70_COLOR_16_FLOAT;
522
523	/* 32-bit buffers. */
524	case PIPE_FORMAT_A8B8G8R8_SRGB:
525	case PIPE_FORMAT_A8B8G8R8_UNORM:
526	case PIPE_FORMAT_A8R8G8B8_UNORM:
527	case PIPE_FORMAT_B8G8R8A8_SRGB:
528	case PIPE_FORMAT_B8G8R8A8_UNORM:
529	case PIPE_FORMAT_B8G8R8X8_UNORM:
530	case PIPE_FORMAT_R8G8B8A8_SNORM:
531	case PIPE_FORMAT_R8G8B8A8_UNORM:
532	case PIPE_FORMAT_R8G8B8X8_UNORM:
533	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
534	case PIPE_FORMAT_X8B8G8R8_UNORM:
535	case PIPE_FORMAT_X8R8G8B8_UNORM:
536	case PIPE_FORMAT_R8G8B8_UNORM:
537	case PIPE_FORMAT_R8G8B8A8_SSCALED:
538	case PIPE_FORMAT_R8G8B8A8_USCALED:
539	case PIPE_FORMAT_R8G8B8A8_SINT:
540	case PIPE_FORMAT_R8G8B8A8_UINT:
541		return V_028C70_COLOR_8_8_8_8;
542
543	case PIPE_FORMAT_R10G10B10A2_UNORM:
544	case PIPE_FORMAT_R10G10B10X2_SNORM:
545	case PIPE_FORMAT_B10G10R10A2_UNORM:
546	case PIPE_FORMAT_B10G10R10A2_UINT:
547	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
548		return V_028C70_COLOR_2_10_10_10;
549
550	case PIPE_FORMAT_Z24X8_UNORM:
551	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
552		return V_028C70_COLOR_8_24;
553
554	case PIPE_FORMAT_X8Z24_UNORM:
555	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
556		return V_028C70_COLOR_24_8;
557
558	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
559		return V_028C70_COLOR_X24_8_32_FLOAT;
560
561	case PIPE_FORMAT_R32_UINT:
562	case PIPE_FORMAT_R32_SINT:
563		return V_028C70_COLOR_32;
564
565	case PIPE_FORMAT_R32_FLOAT:
566	case PIPE_FORMAT_Z32_FLOAT:
567		return V_028C70_COLOR_32_FLOAT;
568
569	case PIPE_FORMAT_R16G16_FLOAT:
570		return V_028C70_COLOR_16_16_FLOAT;
571
572	case PIPE_FORMAT_R16G16_SSCALED:
573	case PIPE_FORMAT_R16G16_UNORM:
574	case PIPE_FORMAT_R16G16_UINT:
575	case PIPE_FORMAT_R16G16_SINT:
576		return V_028C70_COLOR_16_16;
577
578	case PIPE_FORMAT_R11G11B10_FLOAT:
579		return V_028C70_COLOR_10_11_11_FLOAT;
580
581	/* 64-bit buffers. */
582	case PIPE_FORMAT_R16G16B16_USCALED:
583	case PIPE_FORMAT_R16G16B16_SSCALED:
584	case PIPE_FORMAT_R16G16B16A16_UINT:
585	case PIPE_FORMAT_R16G16B16A16_SINT:
586	case PIPE_FORMAT_R16G16B16A16_USCALED:
587	case PIPE_FORMAT_R16G16B16A16_SSCALED:
588	case PIPE_FORMAT_R16G16B16A16_UNORM:
589	case PIPE_FORMAT_R16G16B16A16_SNORM:
590		return V_028C70_COLOR_16_16_16_16;
591
592	case PIPE_FORMAT_R16G16B16_FLOAT:
593	case PIPE_FORMAT_R16G16B16A16_FLOAT:
594		return V_028C70_COLOR_16_16_16_16_FLOAT;
595
596	case PIPE_FORMAT_R32G32_FLOAT:
597		return V_028C70_COLOR_32_32_FLOAT;
598
599	case PIPE_FORMAT_R32G32_USCALED:
600	case PIPE_FORMAT_R32G32_SSCALED:
601	case PIPE_FORMAT_R32G32_SINT:
602	case PIPE_FORMAT_R32G32_UINT:
603		return V_028C70_COLOR_32_32;
604
605	/* 96-bit buffers. */
606	case PIPE_FORMAT_R32G32B32_FLOAT:
607		return V_028C70_COLOR_32_32_32_FLOAT;
608
609	/* 128-bit buffers. */
610	case PIPE_FORMAT_R32G32B32A32_SNORM:
611	case PIPE_FORMAT_R32G32B32A32_UNORM:
612	case PIPE_FORMAT_R32G32B32A32_SSCALED:
613	case PIPE_FORMAT_R32G32B32A32_USCALED:
614	case PIPE_FORMAT_R32G32B32A32_SINT:
615	case PIPE_FORMAT_R32G32B32A32_UINT:
616		return V_028C70_COLOR_32_32_32_32;
617	case PIPE_FORMAT_R32G32B32A32_FLOAT:
618		return V_028C70_COLOR_32_32_32_32_FLOAT;
619
620	/* YUV buffers. */
621	case PIPE_FORMAT_UYVY:
622	case PIPE_FORMAT_YUYV:
623	default:
624		return ~0U; /* Unsupported. */
625	}
626}
627
628static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
629{
630	if (R600_BIG_ENDIAN) {
631		switch(colorformat) {
632
633		/* 8-bit buffers. */
634		case V_028C70_COLOR_8:
635			return ENDIAN_NONE;
636
637		/* 16-bit buffers. */
638		case V_028C70_COLOR_5_6_5:
639		case V_028C70_COLOR_1_5_5_5:
640		case V_028C70_COLOR_4_4_4_4:
641		case V_028C70_COLOR_16:
642		case V_028C70_COLOR_8_8:
643			return ENDIAN_8IN16;
644
645		/* 32-bit buffers. */
646		case V_028C70_COLOR_8_8_8_8:
647		case V_028C70_COLOR_2_10_10_10:
648		case V_028C70_COLOR_8_24:
649		case V_028C70_COLOR_24_8:
650		case V_028C70_COLOR_32_FLOAT:
651		case V_028C70_COLOR_16_16_FLOAT:
652		case V_028C70_COLOR_16_16:
653			return ENDIAN_8IN32;
654
655		/* 64-bit buffers. */
656		case V_028C70_COLOR_16_16_16_16:
657		case V_028C70_COLOR_16_16_16_16_FLOAT:
658			return ENDIAN_8IN16;
659
660		case V_028C70_COLOR_32_32_FLOAT:
661		case V_028C70_COLOR_32_32:
662		case V_028C70_COLOR_X24_8_32_FLOAT:
663			return ENDIAN_8IN32;
664
665		/* 96-bit buffers. */
666		case V_028C70_COLOR_32_32_32_FLOAT:
667		/* 128-bit buffers. */
668		case V_028C70_COLOR_32_32_32_32_FLOAT:
669		case V_028C70_COLOR_32_32_32_32:
670			return ENDIAN_8IN32;
671		default:
672			return ENDIAN_NONE; /* Unsupported. */
673		}
674	} else {
675		return ENDIAN_NONE;
676	}
677}
678
679static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
680{
681	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
682}
683
684static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
685{
686	return r600_translate_colorformat(format) != ~0U &&
687		r600_translate_colorswap(format) != ~0U;
688}
689
690static bool r600_is_zs_format_supported(enum pipe_format format)
691{
692	return r600_translate_dbformat(format) != ~0U;
693}
694
695boolean evergreen_is_format_supported(struct pipe_screen *screen,
696				      enum pipe_format format,
697				      enum pipe_texture_target target,
698				      unsigned sample_count,
699				      unsigned usage)
700{
701	unsigned retval = 0;
702
703	if (target >= PIPE_MAX_TEXTURE_TYPES) {
704		R600_ERR("r600: unsupported texture type %d\n", target);
705		return FALSE;
706	}
707
708	if (!util_format_is_supported(format, usage))
709		return FALSE;
710
711	/* Multisample */
712	if (sample_count > 1)
713		return FALSE;
714
715	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
716	    r600_is_sampler_format_supported(screen, format)) {
717		retval |= PIPE_BIND_SAMPLER_VIEW;
718	}
719
720	if ((usage & (PIPE_BIND_RENDER_TARGET |
721		      PIPE_BIND_DISPLAY_TARGET |
722		      PIPE_BIND_SCANOUT |
723		      PIPE_BIND_SHARED)) &&
724	    r600_is_colorbuffer_format_supported(format)) {
725		retval |= usage &
726			  (PIPE_BIND_RENDER_TARGET |
727			   PIPE_BIND_DISPLAY_TARGET |
728			   PIPE_BIND_SCANOUT |
729			   PIPE_BIND_SHARED);
730	}
731
732	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
733	    r600_is_zs_format_supported(format)) {
734		retval |= PIPE_BIND_DEPTH_STENCIL;
735	}
736
737	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
738	    r600_is_vertex_format_supported(format)) {
739		retval |= PIPE_BIND_VERTEX_BUFFER;
740	}
741
742	if (usage & PIPE_BIND_TRANSFER_READ)
743		retval |= PIPE_BIND_TRANSFER_READ;
744	if (usage & PIPE_BIND_TRANSFER_WRITE)
745		retval |= PIPE_BIND_TRANSFER_WRITE;
746
747	return retval == usage;
748}
749
750static void evergreen_set_blend_color(struct pipe_context *ctx,
751					const struct pipe_blend_color *state)
752{
753	struct r600_context *rctx = (struct r600_context *)ctx;
754	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
755
756	if (rstate == NULL)
757		return;
758
759	rstate->id = R600_PIPE_STATE_BLEND_COLOR;
760	r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
761	r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
762	r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
763	r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
764
765	free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
766	rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
767	r600_context_pipe_state_set(rctx, rstate);
768}
769
770static void *evergreen_create_blend_state(struct pipe_context *ctx,
771					const struct pipe_blend_state *state)
772{
773	struct r600_context *rctx = (struct r600_context *)ctx;
774	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
775	struct r600_pipe_state *rstate;
776	uint32_t color_control, target_mask;
777	/* FIXME there is more then 8 framebuffer */
778	unsigned blend_cntl[8];
779
780	if (blend == NULL) {
781		return NULL;
782	}
783
784	rstate = &blend->rstate;
785
786	rstate->id = R600_PIPE_STATE_BLEND;
787
788	target_mask = 0;
789	color_control = S_028808_MODE(1);
790	if (state->logicop_enable) {
791		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
792	} else {
793		color_control |= (0xcc << 16);
794	}
795	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
796	if (state->independent_blend_enable) {
797		for (int i = 0; i < 8; i++) {
798			target_mask |= (state->rt[i].colormask << (4 * i));
799		}
800	} else {
801		for (int i = 0; i < 8; i++) {
802			target_mask |= (state->rt[0].colormask << (4 * i));
803		}
804	}
805	blend->cb_target_mask = target_mask;
806
807	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
808				color_control, NULL, 0);
809
810	if (rctx->chip_class != CAYMAN)
811		r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, ~0, NULL, 0);
812	else {
813		r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
814		r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
815	}
816
817	for (int i = 0; i < 8; i++) {
818		/* state->rt entries > 0 only written if independent blending */
819		const int j = state->independent_blend_enable ? i : 0;
820
821		unsigned eqRGB = state->rt[j].rgb_func;
822		unsigned srcRGB = state->rt[j].rgb_src_factor;
823		unsigned dstRGB = state->rt[j].rgb_dst_factor;
824		unsigned eqA = state->rt[j].alpha_func;
825		unsigned srcA = state->rt[j].alpha_src_factor;
826		unsigned dstA = state->rt[j].alpha_dst_factor;
827
828		blend_cntl[i] = 0;
829		if (!state->rt[j].blend_enable)
830			continue;
831
832		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
833		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
834		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
835		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
836
837		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
838			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
839			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
840			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
841			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
842		}
843	}
844	for (int i = 0; i < 8; i++) {
845		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
846	}
847
848	return rstate;
849}
850
851static void *evergreen_create_dsa_state(struct pipe_context *ctx,
852				   const struct pipe_depth_stencil_alpha_state *state)
853{
854	struct r600_context *rctx = (struct r600_context *)ctx;
855	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
856	unsigned db_depth_control, alpha_test_control, alpha_ref;
857	unsigned db_render_override, db_render_control;
858	struct r600_pipe_state *rstate;
859
860	if (dsa == NULL) {
861		return NULL;
862	}
863
864	dsa->valuemask[0] = state->stencil[0].valuemask;
865	dsa->valuemask[1] = state->stencil[1].valuemask;
866	dsa->writemask[0] = state->stencil[0].writemask;
867	dsa->writemask[1] = state->stencil[1].writemask;
868
869	rstate = &dsa->rstate;
870
871	rstate->id = R600_PIPE_STATE_DSA;
872	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
873		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
874		S_028800_ZFUNC(state->depth.func);
875
876	/* stencil */
877	if (state->stencil[0].enabled) {
878		db_depth_control |= S_028800_STENCIL_ENABLE(1);
879		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
880		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
881		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
882		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
883
884		if (state->stencil[1].enabled) {
885			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
886			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
887			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
888			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
889			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
890		}
891	}
892
893	/* alpha */
894	alpha_test_control = 0;
895	alpha_ref = 0;
896	if (state->alpha.enabled) {
897		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
898		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
899		alpha_ref = fui(state->alpha.ref_value);
900	}
901	dsa->alpha_ref = alpha_ref;
902
903	/* misc */
904	db_render_control = 0;
905	db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
906		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
907		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
908	/* TODO db_render_override depends on query */
909	r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
910	r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
911	r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
912	r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
913	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
914	/* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
915	 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
916	 * evergreen_pipe_shader_ps().*/
917	r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
918	r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
919	r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
920	r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
921	r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
922	r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
923	dsa->db_render_override = db_render_override;
924
925	return rstate;
926}
927
928static void *evergreen_create_rs_state(struct pipe_context *ctx,
929					const struct pipe_rasterizer_state *state)
930{
931	struct r600_context *rctx = (struct r600_context *)ctx;
932	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
933	struct r600_pipe_state *rstate;
934	unsigned tmp;
935	unsigned prov_vtx = 1, polygon_dual_mode;
936	unsigned clip_rule;
937	float psize_min, psize_max;
938
939	if (rs == NULL) {
940		return NULL;
941	}
942
943	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
944				state->fill_back != PIPE_POLYGON_MODE_FILL);
945
946	if (state->flatshade_first)
947		prov_vtx = 0;
948
949	rstate = &rs->rstate;
950	rs->flatshade = state->flatshade;
951	rs->sprite_coord_enable = state->sprite_coord_enable;
952	rs->two_side = state->light_twoside;
953	rs->clip_plane_enable = state->clip_plane_enable;
954	rs->pa_sc_line_stipple = state->line_stipple_enable ?
955				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
956				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
957	rs->pa_su_sc_mode_cntl =
958		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
959		S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
960		S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
961		S_028814_FACE(!state->front_ccw) |
962		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
963		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
964		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
965		S_028814_POLY_MODE(polygon_dual_mode) |
966		S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
967		S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
968	rs->pa_cl_clip_cntl =
969		S_028810_PS_UCP_MODE(3) |
970		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
971		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
972		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
973
974	clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
975
976	/* offset */
977	rs->offset_units = state->offset_units;
978	rs->offset_scale = state->offset_scale * 12.0f;
979
980	rstate->id = R600_PIPE_STATE_RASTERIZER;
981	tmp = S_0286D4_FLAT_SHADE_ENA(1);
982	if (state->sprite_coord_enable) {
983		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
984			S_0286D4_PNT_SPRITE_OVRD_X(2) |
985			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
986			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
987			S_0286D4_PNT_SPRITE_OVRD_W(1);
988		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
989			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
990		}
991	}
992	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
993
994	r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
995	/* point size 12.4 fixed point */
996	tmp = (unsigned)(state->point_size * 8.0);
997	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
998
999	if (state->point_size_per_vertex) {
1000		psize_min = util_get_min_point_size(state);
1001		psize_max = 8192;
1002	} else {
1003		/* Force the point size to be as if the vertex output was disabled. */
1004		psize_min = state->point_size;
1005		psize_max = state->point_size;
1006	}
1007	/* Divide by two, because 0.5 = 1 pixel. */
1008	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
1009				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
1010				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
1011				NULL, 0);
1012
1013	tmp = (unsigned)state->line_width * 8;
1014	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
1015	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
1016				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
1017				NULL, 0);
1018
1019	if (rctx->chip_class == CAYMAN) {
1020		r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
1021		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
1022					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1023					NULL, 0);
1024		r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
1025		r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
1026		r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
1027		r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
1028
1029
1030	} else {
1031		r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
1032
1033		r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
1034		r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
1035		r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
1036		r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
1037
1038		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1039					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1040					NULL, 0);
1041	}
1042	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
1043	r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
1044	return rstate;
1045}
1046
1047static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1048					const struct pipe_sampler_state *state)
1049{
1050	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1051	union util_color uc;
1052	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1053
1054	if (rstate == NULL) {
1055		return NULL;
1056	}
1057
1058	rstate->id = R600_PIPE_STATE_SAMPLER;
1059	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1060	r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1061			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1062			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1063			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1064			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1065			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1066			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1067			S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1068			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1069			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
1070	r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1071			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1072			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1073			NULL, 0);
1074	r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1075					S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1076					(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1077					S_03C008_TYPE(1),
1078					NULL, 0);
1079
1080	if (uc.ui) {
1081		r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1082		r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1083		r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1084		r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1085	}
1086	return rstate;
1087}
1088
1089static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1090							struct pipe_resource *texture,
1091							const struct pipe_sampler_view *state)
1092{
1093	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1094	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1095	struct r600_pipe_resource_state *rstate;
1096	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1097	unsigned format, endian;
1098	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1099	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1100	unsigned height, depth, width;
1101	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1102
1103	if (view == NULL)
1104		return NULL;
1105	rstate = &view->state;
1106
1107	/* initialize base object */
1108	view->base = *state;
1109	view->base.texture = NULL;
1110	pipe_reference(NULL, &texture->reference);
1111	view->base.texture = texture;
1112	view->base.reference.count = 1;
1113	view->base.context = ctx;
1114
1115	swizzle[0] = state->swizzle_r;
1116	swizzle[1] = state->swizzle_g;
1117	swizzle[2] = state->swizzle_b;
1118	swizzle[3] = state->swizzle_a;
1119
1120	format = r600_translate_texformat(ctx->screen, state->format,
1121					  swizzle,
1122					  &word4, &yuv_format);
1123	if (format == ~0) {
1124		format = 0;
1125	}
1126
1127	if (tmp->depth && !tmp->is_flushing_texture) {
1128		r600_texture_depth_flush(ctx, texture, TRUE);
1129		tmp = tmp->flushed_depth_texture;
1130	}
1131
1132	endian = r600_colorformat_endian_swap(format);
1133
1134	if (!rscreen->use_surface) {
1135		height = texture->height0;
1136		depth = texture->depth0;
1137		width = texture->width0;
1138		pitch = align(tmp->pitch_in_blocks[0] *
1139				util_format_get_blockwidth(state->format), 8);
1140		array_mode = tmp->array_mode[0];
1141		tile_type = tmp->tile_type;
1142		tile_split = 0;
1143		macro_aspect = 0;
1144		bankw = 0;
1145		bankh = 0;
1146	} else {
1147		width = tmp->surface.level[0].npix_x;
1148		height = tmp->surface.level[0].npix_y;
1149		depth = tmp->surface.level[0].npix_z;
1150		pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1151		tile_type = tmp->tile_type;
1152
1153		switch (tmp->surface.level[0].mode) {
1154		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1155			array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1156			break;
1157		case RADEON_SURF_MODE_2D:
1158			array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1159			break;
1160		case RADEON_SURF_MODE_1D:
1161			array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1162			break;
1163		case RADEON_SURF_MODE_LINEAR:
1164		default:
1165			array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1166			break;
1167		}
1168		tile_split = tmp->surface.tile_split;
1169		macro_aspect = tmp->surface.mtilea;
1170		bankw = tmp->surface.bankw;
1171		bankh = tmp->surface.bankh;
1172		tile_split = eg_tile_split(tile_split);
1173		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1174		bankw = eg_bank_wh(bankw);
1175		bankh = eg_bank_wh(bankh);
1176	}
1177	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1178
1179	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1180	        height = 1;
1181		depth = texture->array_size;
1182	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1183		depth = texture->array_size;
1184	}
1185
1186	rstate->bo[0] = &tmp->resource;
1187	rstate->bo[1] = &tmp->resource;
1188	rstate->bo_usage[0] = RADEON_USAGE_READ;
1189	rstate->bo_usage[1] = RADEON_USAGE_READ;
1190
1191	rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1192			  S_030000_PITCH((pitch / 8) - 1) |
1193			  S_030000_NON_DISP_TILING_ORDER(tile_type) |
1194			  S_030000_TEX_WIDTH(width - 1));
1195	rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1196			  S_030004_TEX_DEPTH(depth - 1) |
1197			  S_030004_ARRAY_MODE(array_mode));
1198	rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1199	if (state->u.tex.last_level) {
1200		rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1201	} else {
1202		rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1203	}
1204	rstate->val[4] = (word4 |
1205			  S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1206			  S_030010_ENDIAN_SWAP(endian) |
1207			  S_030010_BASE_LEVEL(state->u.tex.first_level));
1208	rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1209			  S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1210			  S_030014_LAST_ARRAY(state->u.tex.last_layer));
1211	/* aniso max 16 samples */
1212	rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1213			 (S_030018_TILE_SPLIT(tile_split));
1214	rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1215			 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1216			 S_03001C_BANK_WIDTH(bankw) |
1217			 S_03001C_BANK_HEIGHT(bankh) |
1218			 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1219			 S_03001C_NUM_BANKS(nbanks);
1220
1221	return &view->base;
1222}
1223
1224static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1225					struct pipe_sampler_view **views)
1226{
1227	struct r600_context *rctx = (struct r600_context *)ctx;
1228	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1229
1230	for (int i = 0; i < count; i++) {
1231		if (resource[i]) {
1232			evergreen_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1233								     i + R600_MAX_CONST_BUFFERS);
1234		}
1235	}
1236}
1237
1238static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1239					struct pipe_sampler_view **views)
1240{
1241	struct r600_context *rctx = (struct r600_context *)ctx;
1242	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1243	int i;
1244	int has_depth = 0;
1245
1246	for (i = 0; i < count; i++) {
1247		if (&rctx->ps_samplers.views[i]->base != views[i]) {
1248			if (resource[i]) {
1249				if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1250					has_depth = 1;
1251				evergreen_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1252									     i + R600_MAX_CONST_BUFFERS);
1253			} else
1254				evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1255									     i + R600_MAX_CONST_BUFFERS);
1256
1257			pipe_sampler_view_reference(
1258				(struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1259				views[i]);
1260		} else {
1261			if (resource[i]) {
1262				if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1263					has_depth = 1;
1264			}
1265		}
1266	}
1267	for (i = count; i < NUM_TEX_UNITS; i++) {
1268		if (rctx->ps_samplers.views[i]) {
1269			evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1270								     i + R600_MAX_CONST_BUFFERS);
1271			pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1272		}
1273	}
1274	rctx->have_depth_texture = has_depth;
1275	rctx->ps_samplers.n_views = count;
1276}
1277
1278static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1279{
1280	struct r600_context *rctx = (struct r600_context *)ctx;
1281	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1282
1283	if (count)
1284		r600_inval_texture_cache(rctx);
1285
1286	memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1287	rctx->ps_samplers.n_samplers = count;
1288
1289	for (int i = 0; i < count; i++) {
1290		evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1291	}
1292}
1293
1294static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1295{
1296	struct r600_context *rctx = (struct r600_context *)ctx;
1297	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1298
1299	if (count)
1300		r600_inval_texture_cache(rctx);
1301
1302	for (int i = 0; i < count; i++) {
1303		evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1304	}
1305}
1306
1307static void evergreen_set_clip_state(struct pipe_context *ctx,
1308				const struct pipe_clip_state *state)
1309{
1310	struct r600_context *rctx = (struct r600_context *)ctx;
1311	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1312	struct pipe_resource *cbuf;
1313
1314	if (rstate == NULL)
1315		return;
1316
1317	rctx->clip = *state;
1318	rstate->id = R600_PIPE_STATE_CLIP;
1319	for (int i = 0; i < 6; i++) {
1320		r600_pipe_state_add_reg(rstate,
1321					R_0285BC_PA_CL_UCP0_X + i * 16,
1322					fui(state->ucp[i][0]), NULL, 0);
1323		r600_pipe_state_add_reg(rstate,
1324					R_0285C0_PA_CL_UCP0_Y + i * 16,
1325					fui(state->ucp[i][1]) , NULL, 0);
1326		r600_pipe_state_add_reg(rstate,
1327					R_0285C4_PA_CL_UCP0_Z + i * 16,
1328					fui(state->ucp[i][2]), NULL, 0);
1329		r600_pipe_state_add_reg(rstate,
1330					R_0285C8_PA_CL_UCP0_W + i * 16,
1331					fui(state->ucp[i][3]), NULL, 0);
1332	}
1333
1334	free(rctx->states[R600_PIPE_STATE_CLIP]);
1335	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1336	r600_context_pipe_state_set(rctx, rstate);
1337
1338	cbuf = pipe_user_buffer_create(ctx->screen,
1339                                   state->ucp,
1340                                   4*4*8, /* 8*4 floats */
1341                                   PIPE_BIND_CONSTANT_BUFFER);
1342	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1343	pipe_resource_reference(&cbuf, NULL);
1344}
1345
1346static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1347					 const struct pipe_poly_stipple *state)
1348{
1349}
1350
1351static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1352{
1353}
1354
1355static void evergreen_set_scissor_state(struct pipe_context *ctx,
1356					const struct pipe_scissor_state *state)
1357{
1358	struct r600_context *rctx = (struct r600_context *)ctx;
1359	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1360	uint32_t tl, br;
1361
1362	if (rstate == NULL)
1363		return;
1364
1365	rstate->id = R600_PIPE_STATE_SCISSOR;
1366	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1367	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1368	r600_pipe_state_add_reg(rstate,
1369				R_028210_PA_SC_CLIPRECT_0_TL, tl,
1370				NULL, 0);
1371	r600_pipe_state_add_reg(rstate,
1372				R_028214_PA_SC_CLIPRECT_0_BR, br,
1373				NULL, 0);
1374	r600_pipe_state_add_reg(rstate,
1375				R_028218_PA_SC_CLIPRECT_1_TL, tl,
1376				NULL, 0);
1377	r600_pipe_state_add_reg(rstate,
1378				R_02821C_PA_SC_CLIPRECT_1_BR, br,
1379				NULL, 0);
1380	r600_pipe_state_add_reg(rstate,
1381				R_028220_PA_SC_CLIPRECT_2_TL, tl,
1382				NULL, 0);
1383	r600_pipe_state_add_reg(rstate,
1384				R_028224_PA_SC_CLIPRECT_2_BR, br,
1385				NULL, 0);
1386	r600_pipe_state_add_reg(rstate,
1387				R_028228_PA_SC_CLIPRECT_3_TL, tl,
1388				NULL, 0);
1389	r600_pipe_state_add_reg(rstate,
1390				R_02822C_PA_SC_CLIPRECT_3_BR, br,
1391				NULL, 0);
1392
1393	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1394	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1395	r600_context_pipe_state_set(rctx, rstate);
1396}
1397
1398static void evergreen_set_viewport_state(struct pipe_context *ctx,
1399					const struct pipe_viewport_state *state)
1400{
1401	struct r600_context *rctx = (struct r600_context *)ctx;
1402	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1403
1404	if (rstate == NULL)
1405		return;
1406
1407	rctx->viewport = *state;
1408	rstate->id = R600_PIPE_STATE_VIEWPORT;
1409	r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1410	r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1411	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1412	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1413	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1414	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1415	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1416	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1417	r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1418
1419	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1420	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1421	r600_context_pipe_state_set(rctx, rstate);
1422}
1423
1424static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1425			 const struct pipe_framebuffer_state *state, int cb)
1426{
1427	struct r600_screen *rscreen = rctx->screen;
1428	struct r600_resource_texture *rtex;
1429	struct r600_surface *surf;
1430	unsigned level = state->cbufs[cb]->u.tex.level;
1431	unsigned pitch, slice;
1432	unsigned color_info, color_attrib;
1433	unsigned format, swap, ntype, endian;
1434	uint64_t offset;
1435	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1436	const struct util_format_description *desc;
1437	int i;
1438	unsigned blend_clamp = 0, blend_bypass = 0;
1439
1440	surf = (struct r600_surface *)state->cbufs[cb];
1441	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1442
1443	if (rtex->depth)
1444		rctx->have_depth_fb = TRUE;
1445
1446	if (rtex->depth && !rtex->is_flushing_texture) {
1447	        r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1448		rtex = rtex->flushed_depth_texture;
1449	}
1450
1451	/* XXX quite sure for dx10+ hw don't need any offset hacks */
1452	if (!rscreen->use_surface) {
1453		offset = r600_texture_get_offset(rtex,
1454				level, state->cbufs[cb]->u.tex.first_layer);
1455		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1456		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1457		if (slice) {
1458			slice = slice - 1;
1459		}
1460		color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1461		tile_split = 0;
1462		macro_aspect = 0;
1463		bankw = 0;
1464		bankh = 0;
1465		if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1466			tile_type = rtex->tile_type;
1467		} else {
1468			/* workaround for linear buffers */
1469			tile_type = 1;
1470		}
1471	} else {
1472		offset = rtex->surface.level[level].offset;
1473		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1474			offset += rtex->surface.level[level].slice_size *
1475				  state->cbufs[cb]->u.tex.first_layer;
1476		}
1477		pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1478		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1479		if (slice) {
1480			slice = slice - 1;
1481		}
1482		color_info = 0;
1483		switch (rtex->surface.level[level].mode) {
1484		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1485			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1486			tile_type = 1;
1487			break;
1488		case RADEON_SURF_MODE_1D:
1489			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1490			tile_type = rtex->tile_type;
1491			break;
1492		case RADEON_SURF_MODE_2D:
1493			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1494			tile_type = rtex->tile_type;
1495			break;
1496		case RADEON_SURF_MODE_LINEAR:
1497		default:
1498			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1499			tile_type = 1;
1500			break;
1501		}
1502		tile_split = rtex->surface.tile_split;
1503		macro_aspect = rtex->surface.mtilea;
1504		bankw = rtex->surface.bankw;
1505		bankh = rtex->surface.bankh;
1506		tile_split = eg_tile_split(tile_split);
1507		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1508		bankw = eg_bank_wh(bankw);
1509		bankh = eg_bank_wh(bankh);
1510	}
1511	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1512	desc = util_format_description(surf->base.format);
1513	for (i = 0; i < 4; i++) {
1514		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1515			break;
1516		}
1517	}
1518
1519	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1520			S_028C74_NUM_BANKS(nbanks) |
1521			S_028C74_BANK_WIDTH(bankw) |
1522			S_028C74_BANK_HEIGHT(bankh) |
1523			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1524			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1525
1526	ntype = V_028C70_NUMBER_UNORM;
1527	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1528		ntype = V_028C70_NUMBER_SRGB;
1529	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1530		if (desc->channel[i].normalized)
1531			ntype = V_028C70_NUMBER_SNORM;
1532		else if (desc->channel[i].pure_integer)
1533			ntype = V_028C70_NUMBER_SINT;
1534	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1535		if (desc->channel[i].normalized)
1536			ntype = V_028C70_NUMBER_UNORM;
1537		else if (desc->channel[i].pure_integer)
1538			ntype = V_028C70_NUMBER_UINT;
1539	}
1540
1541	format = r600_translate_colorformat(surf->base.format);
1542	swap = r600_translate_colorswap(surf->base.format);
1543	if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1544		endian = ENDIAN_NONE;
1545	} else {
1546		endian = r600_colorformat_endian_swap(format);
1547	}
1548
1549	/* blend clamp should be set for all NORM/SRGB types */
1550	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1551	    ntype == V_028C70_NUMBER_SRGB)
1552		blend_clamp = 1;
1553
1554	/* set blend bypass according to docs if SINT/UINT or
1555	   8/24 COLOR variants */
1556	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1557	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1558	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1559		blend_clamp = 0;
1560		blend_bypass = 1;
1561	}
1562
1563	color_info |= S_028C70_FORMAT(format) |
1564		S_028C70_COMP_SWAP(swap) |
1565		S_028C70_BLEND_CLAMP(blend_clamp) |
1566		S_028C70_BLEND_BYPASS(blend_bypass) |
1567		S_028C70_NUMBER_TYPE(ntype) |
1568		S_028C70_ENDIAN(endian);
1569
1570	/* EXPORT_NORM is an optimzation that can be enabled for better
1571	 * performance in certain cases.
1572	 * EXPORT_NORM can be enabled if:
1573	 * - 11-bit or smaller UNORM/SNORM/SRGB
1574	 * - 16-bit or smaller FLOAT
1575	 */
1576	/* FIXME: This should probably be the same for all CBs if we want
1577	 * useful alpha tests. */
1578	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1579	    ((desc->channel[i].size < 12 &&
1580	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1581	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1582	     (desc->channel[i].size < 17 &&
1583	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1584		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1585		rctx->export_16bpc = true;
1586	} else {
1587		rctx->export_16bpc = false;
1588	}
1589	rctx->alpha_ref_dirty = true;
1590
1591
1592	offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1593	offset >>= 8;
1594
1595	/* FIXME handle enabling of CB beyond BASE8 which has different offset */
1596	r600_pipe_state_add_reg(rstate,
1597				R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1598				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1599	r600_pipe_state_add_reg(rstate,
1600				R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1601				0x0, NULL, 0);
1602	r600_pipe_state_add_reg(rstate,
1603				R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1604				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1605	r600_pipe_state_add_reg(rstate,
1606				R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1607				S_028C64_PITCH_TILE_MAX(pitch),
1608				NULL, 0);
1609	r600_pipe_state_add_reg(rstate,
1610				R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1611				S_028C68_SLICE_TILE_MAX(slice),
1612				NULL, 0);
1613	if (!rscreen->use_surface) {
1614		r600_pipe_state_add_reg(rstate,
1615					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1616					0x00000000, NULL, 0);
1617	} else {
1618		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1619			r600_pipe_state_add_reg(rstate,
1620						R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1621						0x00000000, NULL, 0);
1622		} else {
1623			r600_pipe_state_add_reg(rstate,
1624						R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1625						S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1626						S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1627						NULL, 0);
1628		}
1629	}
1630	r600_pipe_state_add_reg(rstate,
1631				R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1632				color_attrib,
1633				&rtex->resource, RADEON_USAGE_READWRITE);
1634}
1635
1636static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1637			 const struct pipe_framebuffer_state *state)
1638{
1639	struct r600_screen *rscreen = rctx->screen;
1640	struct r600_resource_texture *rtex;
1641	struct r600_surface *surf;
1642	uint64_t offset;
1643	unsigned level, first_layer, pitch, slice, format, array_mode;
1644	unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1645
1646	if (state->zsbuf == NULL)
1647		return;
1648
1649	surf = (struct r600_surface *)state->zsbuf;
1650	level = surf->base.u.tex.level;
1651	rtex = (struct r600_resource_texture*)surf->base.texture;
1652	first_layer = surf->base.u.tex.first_layer;
1653	format = r600_translate_dbformat(rtex->real_format);
1654
1655	offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1656	/* XXX remove this once tiling is properly supported */
1657	if (!rscreen->use_surface) {
1658		/* XXX remove this once tiling is properly supported */
1659		array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1660				V_028C70_ARRAY_1D_TILED_THIN1;
1661
1662		offset += r600_texture_get_offset(rtex, level, first_layer);
1663		pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1664		slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1665		if (slice) {
1666			slice = slice - 1;
1667		}
1668		tile_split = 0;
1669		macro_aspect = 0;
1670		bankw = 0;
1671		bankh = 0;
1672	} else {
1673		offset += rtex->surface.level[level].offset;
1674		pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1675		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1676		if (slice) {
1677			slice = slice - 1;
1678		}
1679		switch (rtex->surface.level[level].mode) {
1680		case RADEON_SURF_MODE_2D:
1681			array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1682			break;
1683		case RADEON_SURF_MODE_1D:
1684		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1685		case RADEON_SURF_MODE_LINEAR:
1686		default:
1687			array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1688			break;
1689		}
1690		tile_split = rtex->surface.tile_split;
1691		macro_aspect = rtex->surface.mtilea;
1692		bankw = rtex->surface.bankw;
1693		bankh = rtex->surface.bankh;
1694		tile_split = eg_tile_split(tile_split);
1695		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1696		bankw = eg_bank_wh(bankw);
1697		bankh = eg_bank_wh(bankh);
1698	}
1699	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1700	offset >>= 8;
1701
1702	z_info = S_028040_ARRAY_MODE(array_mode) |
1703		 S_028040_FORMAT(format) |
1704		 S_028040_TILE_SPLIT(tile_split)|
1705		 S_028040_NUM_BANKS(nbanks) |
1706		 S_028040_BANK_WIDTH(bankw) |
1707		 S_028040_BANK_HEIGHT(bankh) |
1708		 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1709
1710	r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1711				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1712	r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1713				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1714	if (!rscreen->use_surface) {
1715		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1716					0x00000000, NULL, 0);
1717	} else {
1718		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1719					S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1720					S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1721					NULL, 0);
1722	}
1723
1724	if (rtex->stencil) {
1725		uint64_t stencil_offset =
1726			r600_texture_get_offset(rtex->stencil, level, first_layer);
1727		unsigned stile_split;
1728
1729		stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1730		stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1731		stencil_offset >>= 8;
1732
1733		r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1734					stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1735		r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1736					stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1737		r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1738					1 | S_028044_TILE_SPLIT(stile_split),
1739					&rtex->stencil->resource, RADEON_USAGE_READWRITE);
1740	} else {
1741		if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1742			uint64_t stencil_offset = rtex->surface.stencil_offset;
1743			unsigned stile_split = rtex->surface.stencil_tile_split;
1744
1745			stile_split = eg_tile_split(stile_split);
1746			stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1747			stencil_offset += rtex->surface.level[level].offset / 4;
1748			stencil_offset >>= 8;
1749
1750			r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1751						stencil_offset, &rtex->resource,
1752						RADEON_USAGE_READWRITE);
1753			r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1754						stencil_offset, &rtex->resource,
1755						RADEON_USAGE_READWRITE);
1756			r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1757						1 | S_028044_TILE_SPLIT(stile_split),
1758						&rtex->resource,
1759						RADEON_USAGE_READWRITE);
1760		} else {
1761			r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1762						offset, &rtex->resource,
1763						RADEON_USAGE_READWRITE);
1764			r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1765						offset, &rtex->resource,
1766						RADEON_USAGE_READWRITE);
1767			r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1768						0, NULL, RADEON_USAGE_READWRITE);
1769		}
1770	}
1771
1772	r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1773				&rtex->resource, RADEON_USAGE_READWRITE);
1774	r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1775				S_028058_PITCH_TILE_MAX(pitch),
1776				NULL, 0);
1777	r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1778				S_02805C_SLICE_TILE_MAX(slice),
1779				NULL, 0);
1780}
1781
1782static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1783					const struct pipe_framebuffer_state *state)
1784{
1785	struct r600_context *rctx = (struct r600_context *)ctx;
1786	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1787	uint32_t shader_mask, tl, br;
1788	int tl_x, tl_y, br_x, br_y;
1789
1790	if (rstate == NULL)
1791		return;
1792
1793	r600_flush_framebuffer(rctx, false);
1794
1795	/* unreference old buffer and reference new one */
1796	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1797
1798	util_copy_framebuffer_state(&rctx->framebuffer, state);
1799
1800	/* build states */
1801	rctx->have_depth_fb = 0;
1802	rctx->nr_cbufs = state->nr_cbufs;
1803	for (int i = 0; i < state->nr_cbufs; i++) {
1804		evergreen_cb(rctx, rstate, state, i);
1805	}
1806	if (state->zsbuf) {
1807		evergreen_db(rctx, rstate, state);
1808	}
1809
1810	shader_mask = 0;
1811	for (int i = 0; i < state->nr_cbufs; i++) {
1812		shader_mask |= 0xf << (i * 4);
1813	}
1814	tl_x = 0;
1815	tl_y = 0;
1816	br_x = state->width;
1817	br_y = state->height;
1818	/* EG hw workaround */
1819	if (br_x == 0)
1820		tl_x = 1;
1821	if (br_y == 0)
1822		tl_y = 1;
1823	/* cayman hw workaround */
1824	if (rctx->chip_class == CAYMAN) {
1825		if (br_x == 1 && br_y == 1)
1826			br_x = 2;
1827	}
1828	tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1829	br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1830
1831	r600_pipe_state_add_reg(rstate,
1832				R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1833				NULL, 0);
1834	r600_pipe_state_add_reg(rstate,
1835				R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1836				NULL, 0);
1837	r600_pipe_state_add_reg(rstate,
1838				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1839				NULL, 0);
1840	r600_pipe_state_add_reg(rstate,
1841				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1842				NULL, 0);
1843	r600_pipe_state_add_reg(rstate,
1844				R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1845				NULL, 0);
1846	r600_pipe_state_add_reg(rstate,
1847				R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1848				NULL, 0);
1849	r600_pipe_state_add_reg(rstate,
1850				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1851				NULL, 0);
1852	r600_pipe_state_add_reg(rstate,
1853				R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1854				NULL, 0);
1855	r600_pipe_state_add_reg(rstate,
1856				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1857				NULL, 0);
1858	r600_pipe_state_add_reg(rstate,
1859				R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1860				NULL, 0);
1861	r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1862				shader_mask, NULL, 0);
1863
1864
1865	if (rctx->chip_class == CAYMAN) {
1866		r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1867					0x00000000, NULL, 0);
1868	} else {
1869		r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1870					0x00000000, NULL, 0);
1871		r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1872					0x00000000, NULL, 0);
1873	}
1874
1875	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1876	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1877	r600_context_pipe_state_set(rctx, rstate);
1878
1879	if (state->zsbuf) {
1880		evergreen_polygon_offset_update(rctx);
1881	}
1882}
1883
1884void evergreen_init_state_functions(struct r600_context *rctx)
1885{
1886	rctx->context.create_blend_state = evergreen_create_blend_state;
1887	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1888	rctx->context.create_fs_state = r600_create_shader_state;
1889	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1890	rctx->context.create_sampler_state = evergreen_create_sampler_state;
1891	rctx->context.create_sampler_view = evergreen_create_sampler_view;
1892	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1893	rctx->context.create_vs_state = r600_create_shader_state;
1894	rctx->context.bind_blend_state = r600_bind_blend_state;
1895	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1896	rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1897	rctx->context.bind_fs_state = r600_bind_ps_shader;
1898	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1899	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1900	rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1901	rctx->context.bind_vs_state = r600_bind_vs_shader;
1902	rctx->context.delete_blend_state = r600_delete_state;
1903	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1904	rctx->context.delete_fs_state = r600_delete_ps_shader;
1905	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1906	rctx->context.delete_sampler_state = r600_delete_state;
1907	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1908	rctx->context.delete_vs_state = r600_delete_vs_shader;
1909	rctx->context.set_blend_color = evergreen_set_blend_color;
1910	rctx->context.set_clip_state = evergreen_set_clip_state;
1911	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1912	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1913	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1914	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1915	rctx->context.set_sample_mask = evergreen_set_sample_mask;
1916	rctx->context.set_scissor_state = evergreen_set_scissor_state;
1917	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1918	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1919	rctx->context.set_index_buffer = r600_set_index_buffer;
1920	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1921	rctx->context.set_viewport_state = evergreen_set_viewport_state;
1922	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1923	rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1924	rctx->context.texture_barrier = r600_texture_barrier;
1925	rctx->context.create_stream_output_target = r600_create_so_target;
1926	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1927	rctx->context.set_stream_output_targets = r600_set_so_targets;
1928}
1929
1930static void cayman_init_config(struct r600_context *rctx)
1931{
1932  	struct r600_pipe_state *rstate = &rctx->config;
1933	unsigned tmp;
1934
1935	tmp = 0x00000000;
1936	tmp |= S_008C00_EXPORT_SRC_C(1);
1937	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
1938
1939	/* always set the temp clauses */
1940	r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
1941	r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
1942	r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
1943	r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
1944
1945	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1946
1947	r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1948	r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1949	r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1950	r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1951	r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1952	r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1953	r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1954	r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1955	r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1956	r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1957	r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1958	r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1959	r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1960	r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1961	r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1962	r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1963	r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1964	r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1965	r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1966
1967	r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
1968	r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
1969	r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
1970	r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
1971	r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
1972	r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
1973	r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
1974	r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
1975	r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
1976	r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
1977	r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
1978	r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
1979	r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
1980	r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
1981	r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
1982	r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
1983	r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
1984	r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
1985	r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
1986	r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
1987	r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
1988	r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
1989	r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
1990	r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
1991	r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
1992	r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
1993	r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
1994	r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
1995	r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
1996	r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
1997	r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
1998	r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
1999
2000	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2001
2002	r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
2003	r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
2004
2005	r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
2006	r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
2007
2008	r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
2009	r600_context_pipe_state_set(rctx, rstate);
2010}
2011
2012void evergreen_init_config(struct r600_context *rctx)
2013{
2014	struct r600_pipe_state *rstate = &rctx->config;
2015	int ps_prio;
2016	int vs_prio;
2017	int gs_prio;
2018	int es_prio;
2019	int hs_prio, cs_prio, ls_prio;
2020	int num_ps_gprs;
2021	int num_vs_gprs;
2022	int num_gs_gprs;
2023	int num_es_gprs;
2024	int num_hs_gprs;
2025	int num_ls_gprs;
2026	int num_temp_gprs;
2027	int num_ps_threads;
2028	int num_vs_threads;
2029	int num_gs_threads;
2030	int num_es_threads;
2031	int num_hs_threads;
2032	int num_ls_threads;
2033	int num_ps_stack_entries;
2034	int num_vs_stack_entries;
2035	int num_gs_stack_entries;
2036	int num_es_stack_entries;
2037	int num_hs_stack_entries;
2038	int num_ls_stack_entries;
2039	enum radeon_family family;
2040	unsigned tmp;
2041
2042	family = rctx->family;
2043
2044	if (rctx->chip_class == CAYMAN) {
2045		cayman_init_config(rctx);
2046		return;
2047	}
2048
2049	ps_prio = 0;
2050	vs_prio = 1;
2051	gs_prio = 2;
2052	es_prio = 3;
2053	hs_prio = 0;
2054	ls_prio = 0;
2055	cs_prio = 0;
2056
2057	switch (family) {
2058	case CHIP_CEDAR:
2059	default:
2060		num_ps_gprs = 93;
2061		num_vs_gprs = 46;
2062		num_temp_gprs = 4;
2063		num_gs_gprs = 31;
2064		num_es_gprs = 31;
2065		num_hs_gprs = 23;
2066		num_ls_gprs = 23;
2067		num_ps_threads = 96;
2068		num_vs_threads = 16;
2069		num_gs_threads = 16;
2070		num_es_threads = 16;
2071		num_hs_threads = 16;
2072		num_ls_threads = 16;
2073		num_ps_stack_entries = 42;
2074		num_vs_stack_entries = 42;
2075		num_gs_stack_entries = 42;
2076		num_es_stack_entries = 42;
2077		num_hs_stack_entries = 42;
2078		num_ls_stack_entries = 42;
2079		break;
2080	case CHIP_REDWOOD:
2081		num_ps_gprs = 93;
2082		num_vs_gprs = 46;
2083		num_temp_gprs = 4;
2084		num_gs_gprs = 31;
2085		num_es_gprs = 31;
2086		num_hs_gprs = 23;
2087		num_ls_gprs = 23;
2088		num_ps_threads = 128;
2089		num_vs_threads = 20;
2090		num_gs_threads = 20;
2091		num_es_threads = 20;
2092		num_hs_threads = 20;
2093		num_ls_threads = 20;
2094		num_ps_stack_entries = 42;
2095		num_vs_stack_entries = 42;
2096		num_gs_stack_entries = 42;
2097		num_es_stack_entries = 42;
2098		num_hs_stack_entries = 42;
2099		num_ls_stack_entries = 42;
2100		break;
2101	case CHIP_JUNIPER:
2102		num_ps_gprs = 93;
2103		num_vs_gprs = 46;
2104		num_temp_gprs = 4;
2105		num_gs_gprs = 31;
2106		num_es_gprs = 31;
2107		num_hs_gprs = 23;
2108		num_ls_gprs = 23;
2109		num_ps_threads = 128;
2110		num_vs_threads = 20;
2111		num_gs_threads = 20;
2112		num_es_threads = 20;
2113		num_hs_threads = 20;
2114		num_ls_threads = 20;
2115		num_ps_stack_entries = 85;
2116		num_vs_stack_entries = 85;
2117		num_gs_stack_entries = 85;
2118		num_es_stack_entries = 85;
2119		num_hs_stack_entries = 85;
2120		num_ls_stack_entries = 85;
2121		break;
2122	case CHIP_CYPRESS:
2123	case CHIP_HEMLOCK:
2124		num_ps_gprs = 93;
2125		num_vs_gprs = 46;
2126		num_temp_gprs = 4;
2127		num_gs_gprs = 31;
2128		num_es_gprs = 31;
2129		num_hs_gprs = 23;
2130		num_ls_gprs = 23;
2131		num_ps_threads = 128;
2132		num_vs_threads = 20;
2133		num_gs_threads = 20;
2134		num_es_threads = 20;
2135		num_hs_threads = 20;
2136		num_ls_threads = 20;
2137		num_ps_stack_entries = 85;
2138		num_vs_stack_entries = 85;
2139		num_gs_stack_entries = 85;
2140		num_es_stack_entries = 85;
2141		num_hs_stack_entries = 85;
2142		num_ls_stack_entries = 85;
2143		break;
2144	case CHIP_PALM:
2145		num_ps_gprs = 93;
2146		num_vs_gprs = 46;
2147		num_temp_gprs = 4;
2148		num_gs_gprs = 31;
2149		num_es_gprs = 31;
2150		num_hs_gprs = 23;
2151		num_ls_gprs = 23;
2152		num_ps_threads = 96;
2153		num_vs_threads = 16;
2154		num_gs_threads = 16;
2155		num_es_threads = 16;
2156		num_hs_threads = 16;
2157		num_ls_threads = 16;
2158		num_ps_stack_entries = 42;
2159		num_vs_stack_entries = 42;
2160		num_gs_stack_entries = 42;
2161		num_es_stack_entries = 42;
2162		num_hs_stack_entries = 42;
2163		num_ls_stack_entries = 42;
2164		break;
2165	case CHIP_SUMO:
2166		num_ps_gprs = 93;
2167		num_vs_gprs = 46;
2168		num_temp_gprs = 4;
2169		num_gs_gprs = 31;
2170		num_es_gprs = 31;
2171		num_hs_gprs = 23;
2172		num_ls_gprs = 23;
2173		num_ps_threads = 96;
2174		num_vs_threads = 25;
2175		num_gs_threads = 25;
2176		num_es_threads = 25;
2177		num_hs_threads = 25;
2178		num_ls_threads = 25;
2179		num_ps_stack_entries = 42;
2180		num_vs_stack_entries = 42;
2181		num_gs_stack_entries = 42;
2182		num_es_stack_entries = 42;
2183		num_hs_stack_entries = 42;
2184		num_ls_stack_entries = 42;
2185		break;
2186	case CHIP_SUMO2:
2187		num_ps_gprs = 93;
2188		num_vs_gprs = 46;
2189		num_temp_gprs = 4;
2190		num_gs_gprs = 31;
2191		num_es_gprs = 31;
2192		num_hs_gprs = 23;
2193		num_ls_gprs = 23;
2194		num_ps_threads = 96;
2195		num_vs_threads = 25;
2196		num_gs_threads = 25;
2197		num_es_threads = 25;
2198		num_hs_threads = 25;
2199		num_ls_threads = 25;
2200		num_ps_stack_entries = 85;
2201		num_vs_stack_entries = 85;
2202		num_gs_stack_entries = 85;
2203		num_es_stack_entries = 85;
2204		num_hs_stack_entries = 85;
2205		num_ls_stack_entries = 85;
2206		break;
2207	case CHIP_BARTS:
2208		num_ps_gprs = 93;
2209		num_vs_gprs = 46;
2210		num_temp_gprs = 4;
2211		num_gs_gprs = 31;
2212		num_es_gprs = 31;
2213		num_hs_gprs = 23;
2214		num_ls_gprs = 23;
2215		num_ps_threads = 128;
2216		num_vs_threads = 20;
2217		num_gs_threads = 20;
2218		num_es_threads = 20;
2219		num_hs_threads = 20;
2220		num_ls_threads = 20;
2221		num_ps_stack_entries = 85;
2222		num_vs_stack_entries = 85;
2223		num_gs_stack_entries = 85;
2224		num_es_stack_entries = 85;
2225		num_hs_stack_entries = 85;
2226		num_ls_stack_entries = 85;
2227		break;
2228	case CHIP_TURKS:
2229		num_ps_gprs = 93;
2230		num_vs_gprs = 46;
2231		num_temp_gprs = 4;
2232		num_gs_gprs = 31;
2233		num_es_gprs = 31;
2234		num_hs_gprs = 23;
2235		num_ls_gprs = 23;
2236		num_ps_threads = 128;
2237		num_vs_threads = 20;
2238		num_gs_threads = 20;
2239		num_es_threads = 20;
2240		num_hs_threads = 20;
2241		num_ls_threads = 20;
2242		num_ps_stack_entries = 42;
2243		num_vs_stack_entries = 42;
2244		num_gs_stack_entries = 42;
2245		num_es_stack_entries = 42;
2246		num_hs_stack_entries = 42;
2247		num_ls_stack_entries = 42;
2248		break;
2249	case CHIP_CAICOS:
2250		num_ps_gprs = 93;
2251		num_vs_gprs = 46;
2252		num_temp_gprs = 4;
2253		num_gs_gprs = 31;
2254		num_es_gprs = 31;
2255		num_hs_gprs = 23;
2256		num_ls_gprs = 23;
2257		num_ps_threads = 128;
2258		num_vs_threads = 10;
2259		num_gs_threads = 10;
2260		num_es_threads = 10;
2261		num_hs_threads = 10;
2262		num_ls_threads = 10;
2263		num_ps_stack_entries = 42;
2264		num_vs_stack_entries = 42;
2265		num_gs_stack_entries = 42;
2266		num_es_stack_entries = 42;
2267		num_hs_stack_entries = 42;
2268		num_ls_stack_entries = 42;
2269		break;
2270	}
2271
2272	tmp = 0x00000000;
2273	switch (family) {
2274	case CHIP_CEDAR:
2275	case CHIP_PALM:
2276	case CHIP_SUMO:
2277	case CHIP_SUMO2:
2278	case CHIP_CAICOS:
2279		break;
2280	default:
2281		tmp |= S_008C00_VC_ENABLE(1);
2282		break;
2283	}
2284	tmp |= S_008C00_EXPORT_SRC_C(1);
2285	tmp |= S_008C00_CS_PRIO(cs_prio);
2286	tmp |= S_008C00_LS_PRIO(ls_prio);
2287	tmp |= S_008C00_HS_PRIO(hs_prio);
2288	tmp |= S_008C00_PS_PRIO(ps_prio);
2289	tmp |= S_008C00_VS_PRIO(vs_prio);
2290	tmp |= S_008C00_GS_PRIO(gs_prio);
2291	tmp |= S_008C00_ES_PRIO(es_prio);
2292	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2293
2294	/* enable dynamic GPR resource management */
2295	if (rctx->screen->info.drm_minor >= 7) {
2296		/* always set temp clauses */
2297		r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2298					S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
2299		r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
2300		r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
2301		r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
2302		r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2303					S_028838_PS_GPRS(0x1e) |
2304					S_028838_VS_GPRS(0x1e) |
2305					S_028838_GS_GPRS(0x1e) |
2306					S_028838_ES_GPRS(0x1e) |
2307					S_028838_HS_GPRS(0x1e) |
2308					S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2309	} else {
2310		tmp = 0;
2311		tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2312		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2313		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2314		r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2315
2316		tmp = 0;
2317		tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2318		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2319		r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2320
2321		tmp = 0;
2322		tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2323		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2324		r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
2325	}
2326
2327	tmp = 0;
2328	tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2329	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2330	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2331	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2332	r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
2333
2334	tmp = 0;
2335	tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2336	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2337	r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
2338
2339	tmp = 0;
2340	tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2341	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2342	r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2343
2344	tmp = 0;
2345	tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2346	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2347	r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2348
2349	tmp = 0;
2350	tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2351	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2352	r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
2353
2354	tmp = 0;
2355	tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2356	tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2357	r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
2358
2359	r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
2360	r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
2361
2362#if 0
2363	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
2364
2365	r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
2366#endif
2367	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
2368
2369	r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
2370	r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
2371	r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2372	r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2373	r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2374	r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2375
2376	r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
2377	r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
2378	r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
2379	r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
2380
2381	r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
2382	r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
2383	r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
2384	r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
2385	r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
2386	r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
2387	r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
2388	r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
2389	r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
2390	r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
2391	r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
2392	r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
2393	r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
2394	r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
2395	r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
2396	r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
2397	r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
2398	r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
2399
2400	r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
2401	r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
2402	r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
2403	r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
2404	r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
2405	r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
2406	r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
2407	r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
2408	r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
2409	r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
2410	r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
2411	r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
2412	r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
2413	r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
2414	r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
2415	r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
2416	r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
2417	r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
2418	r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
2419	r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
2420	r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
2421	r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
2422	r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
2423	r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
2424	r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
2425	r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
2426	r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
2427	r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
2428	r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
2429	r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
2430	r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
2431	r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
2432
2433	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2434
2435	r600_context_pipe_state_set(rctx, rstate);
2436}
2437
2438void evergreen_polygon_offset_update(struct r600_context *rctx)
2439{
2440	struct r600_pipe_state state;
2441
2442	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2443	state.nregs = 0;
2444	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2445		float offset_units = rctx->rasterizer->offset_units;
2446		unsigned offset_db_fmt_cntl = 0, depth;
2447
2448		switch (rctx->framebuffer.zsbuf->texture->format) {
2449		case PIPE_FORMAT_Z24X8_UNORM:
2450		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2451			depth = -24;
2452			offset_units *= 2.0f;
2453			break;
2454		case PIPE_FORMAT_Z32_FLOAT:
2455		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2456			depth = -23;
2457			offset_units *= 1.0f;
2458			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2459			break;
2460		case PIPE_FORMAT_Z16_UNORM:
2461			depth = -16;
2462			offset_units *= 4.0f;
2463			break;
2464		default:
2465			return;
2466		}
2467		/* FIXME some of those reg can be computed with cso */
2468		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2469		r600_pipe_state_add_reg(&state,
2470				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2471				fui(rctx->rasterizer->offset_scale), NULL, 0);
2472		r600_pipe_state_add_reg(&state,
2473				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2474				fui(offset_units), NULL, 0);
2475		r600_pipe_state_add_reg(&state,
2476				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2477				fui(rctx->rasterizer->offset_scale), NULL, 0);
2478		r600_pipe_state_add_reg(&state,
2479				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2480				fui(offset_units), NULL, 0);
2481		r600_pipe_state_add_reg(&state,
2482				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2483				offset_db_fmt_cntl, NULL, 0);
2484		r600_context_pipe_state_set(rctx, &state);
2485	}
2486}
2487
2488void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2489{
2490	struct r600_context *rctx = (struct r600_context *)ctx;
2491	struct r600_pipe_state *rstate = &shader->rstate;
2492	struct r600_shader *rshader = &shader->shader;
2493	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2494	int pos_index = -1, face_index = -1;
2495	int ninterp = 0;
2496	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2497	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2498
2499	rstate->nregs = 0;
2500
2501	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2502	for (i = 0; i < rshader->ninput; i++) {
2503		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2504		   POSITION goes via GPRs from the SC so isn't counted */
2505		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2506			pos_index = i;
2507		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2508			face_index = i;
2509		else {
2510			ninterp++;
2511			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2512				have_linear = TRUE;
2513			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2514				have_perspective = TRUE;
2515			if (rshader->input[i].centroid)
2516				have_centroid = TRUE;
2517		}
2518
2519		sid = rshader->input[i].spi_sid;
2520
2521		if (sid) {
2522
2523			tmp = S_028644_SEMANTIC(sid);
2524
2525			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2526				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2527				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2528					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2529				tmp |= S_028644_FLAT_SHADE(1);
2530			}
2531
2532			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2533					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2534				tmp |= S_028644_PT_SPRITE_TEX(1);
2535			}
2536
2537			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2538					tmp, NULL, 0);
2539
2540			idx++;
2541		}
2542	}
2543
2544	for (i = 0; i < rshader->noutput; i++) {
2545		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2546			db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2547		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2548			db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2549	}
2550	if (rshader->uses_kill)
2551		db_shader_control |= S_02880C_KILL_ENABLE(1);
2552
2553	exports_ps = 0;
2554	num_cout = 0;
2555	for (i = 0; i < rshader->noutput; i++) {
2556		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2557		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2558			exports_ps |= 1;
2559		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2560			if (rshader->fs_write_all)
2561				num_cout = rshader->nr_cbufs;
2562			else
2563				num_cout++;
2564		}
2565	}
2566	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2567	if (!exports_ps) {
2568		/* always at least export 1 component per pixel */
2569		exports_ps = 2;
2570	}
2571
2572	if (ninterp == 0) {
2573		ninterp = 1;
2574		have_perspective = TRUE;
2575	}
2576
2577	if (!have_perspective && !have_linear)
2578		have_perspective = TRUE;
2579
2580	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2581		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2582		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2583	spi_input_z = 0;
2584	if (pos_index != -1) {
2585		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2586			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2587			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2588		spi_input_z |= 1;
2589	}
2590
2591	spi_ps_in_control_1 = 0;
2592	if (face_index != -1) {
2593		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2594			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2595	}
2596
2597	spi_baryc_cntl = 0;
2598	if (have_perspective)
2599		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2600				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2601	if (have_linear)
2602		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2603				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2604
2605	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2606				spi_ps_in_control_0, NULL, 0);
2607	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2608				spi_ps_in_control_1, NULL, 0);
2609	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2610				0, NULL, 0);
2611	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2612	r600_pipe_state_add_reg(rstate,
2613				R_0286E0_SPI_BARYC_CNTL,
2614				spi_baryc_cntl,
2615				NULL, 0);
2616
2617	r600_pipe_state_add_reg(rstate,
2618				R_028840_SQ_PGM_START_PS,
2619				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2620				shader->bo, RADEON_USAGE_READ);
2621	r600_pipe_state_add_reg(rstate,
2622				R_028844_SQ_PGM_RESOURCES_PS,
2623				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2624				S_028844_PRIME_CACHE_ON_DRAW(1) |
2625				S_028844_STACK_SIZE(rshader->bc.nstack),
2626				NULL, 0);
2627	r600_pipe_state_add_reg(rstate,
2628				R_028848_SQ_PGM_RESOURCES_2_PS,
2629				S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2630				NULL, 0);
2631	r600_pipe_state_add_reg(rstate,
2632				R_02884C_SQ_PGM_EXPORTS_PS,
2633				exports_ps, NULL, 0);
2634	r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2635				db_shader_control,
2636				NULL, 0);
2637	r600_pipe_state_add_reg(rstate,
2638				R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2639				NULL, 0);
2640
2641	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2642	if (rctx->rasterizer)
2643		shader->flatshade = rctx->rasterizer->flatshade;
2644}
2645
2646void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2647{
2648	struct r600_context *rctx = (struct r600_context *)ctx;
2649	struct r600_pipe_state *rstate = &shader->rstate;
2650	struct r600_shader *rshader = &shader->shader;
2651	unsigned spi_vs_out_id[10] = {};
2652	unsigned i, tmp, nparams = 0;
2653
2654	/* clear previous register */
2655	rstate->nregs = 0;
2656
2657	for (i = 0; i < rshader->noutput; i++) {
2658		if (rshader->output[i].spi_sid) {
2659			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2660			spi_vs_out_id[nparams / 4] |= tmp;
2661			nparams++;
2662		}
2663	}
2664
2665	for (i = 0; i < 10; i++) {
2666		r600_pipe_state_add_reg(rstate,
2667					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2668					spi_vs_out_id[i], NULL, 0);
2669	}
2670
2671	/* Certain attributes (position, psize, etc.) don't count as params.
2672	 * VS is required to export at least one param and r600_shader_from_tgsi()
2673	 * takes care of adding a dummy export.
2674	 */
2675	if (nparams < 1)
2676		nparams = 1;
2677
2678	r600_pipe_state_add_reg(rstate,
2679			R_0286C4_SPI_VS_OUT_CONFIG,
2680			S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2681			NULL, 0);
2682	r600_pipe_state_add_reg(rstate,
2683			R_028860_SQ_PGM_RESOURCES_VS,
2684			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2685			S_028860_STACK_SIZE(rshader->bc.nstack),
2686			NULL, 0);
2687	r600_pipe_state_add_reg(rstate,
2688				R_028864_SQ_PGM_RESOURCES_2_VS,
2689				S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2690				NULL, 0);
2691	r600_pipe_state_add_reg(rstate,
2692			R_02885C_SQ_PGM_START_VS,
2693			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2694			shader->bo, RADEON_USAGE_READ);
2695
2696	r600_pipe_state_add_reg(rstate,
2697				R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2698				NULL, 0);
2699
2700	shader->pa_cl_vs_out_cntl =
2701		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2702		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2703		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2704		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2705}
2706
2707void evergreen_fetch_shader(struct pipe_context *ctx,
2708			    struct r600_vertex_element *ve)
2709{
2710	struct r600_context *rctx = (struct r600_context *)ctx;
2711	struct r600_pipe_state *rstate = &ve->rstate;
2712	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2713	rstate->nregs = 0;
2714	r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2715				0x00000000, NULL, 0);
2716	r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2717				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2718				ve->fetch_shader, RADEON_USAGE_READ);
2719}
2720
2721void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2722{
2723	struct pipe_depth_stencil_alpha_state dsa;
2724	struct r600_pipe_state *rstate;
2725
2726	memset(&dsa, 0, sizeof(dsa));
2727
2728	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2729	r600_pipe_state_add_reg(rstate,
2730				R_028000_DB_RENDER_CONTROL,
2731				S_028000_DEPTH_COPY_ENABLE(1) |
2732				S_028000_STENCIL_COPY_ENABLE(1) |
2733				S_028000_COPY_CENTROID(1),
2734				NULL, 0);
2735	return rstate;
2736}
2737
2738void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2739					 struct r600_pipe_resource_state *rstate)
2740{
2741	rstate->id = R600_PIPE_STATE_RESOURCE;
2742
2743	rstate->val[0] = 0;
2744	rstate->bo[0] = NULL;
2745	rstate->val[1] = 0;
2746	rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2747	rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2748	  S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2749	  S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2750	  S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2751	rstate->val[4] = 0;
2752	rstate->val[5] = 0;
2753	rstate->val[6] = 0;
2754	rstate->val[7] = 0xc0000000;
2755}
2756
2757
2758void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2759					struct r600_pipe_resource_state *rstate,
2760					struct r600_resource *rbuffer,
2761					unsigned offset, unsigned stride,
2762					enum radeon_bo_usage usage)
2763{
2764	uint64_t va;
2765
2766	va = r600_resource_va(ctx->screen, (void *)rbuffer);
2767	rstate->bo[0] = rbuffer;
2768	rstate->bo_usage[0] = usage;
2769	rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2770	rstate->val[1] = rbuffer->buf->size - offset - 1;
2771	rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2772			 S_030008_STRIDE(stride) |
2773			 (((va + offset) >> 32UL) & 0xFF);
2774}
2775