r600_state.c revision 43e3f19c766863a655bb9f7c04f7820cbda0c8f5 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "r600d.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31
32static uint32_t r600_translate_blend_function(int blend_func)
33{
34	switch (blend_func) {
35	case PIPE_BLEND_ADD:
36		return V_028804_COMB_DST_PLUS_SRC;
37	case PIPE_BLEND_SUBTRACT:
38		return V_028804_COMB_SRC_MINUS_DST;
39	case PIPE_BLEND_REVERSE_SUBTRACT:
40		return V_028804_COMB_DST_MINUS_SRC;
41	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return V_038000_SQ_TEX_DIM_2D;
113	case PIPE_TEXTURE_2D_ARRAY:
114		return V_038000_SQ_TEX_DIM_2D_ARRAY;
115	case PIPE_TEXTURE_3D:
116		return V_038000_SQ_TEX_DIM_3D;
117	case PIPE_TEXTURE_CUBE:
118		return V_038000_SQ_TEX_DIM_CUBEMAP;
119	}
120}
121
122static uint32_t r600_translate_dbformat(enum pipe_format format)
123{
124	switch (format) {
125	case PIPE_FORMAT_Z16_UNORM:
126		return V_028010_DEPTH_16;
127	case PIPE_FORMAT_Z24X8_UNORM:
128		return V_028010_DEPTH_X8_24;
129	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130		return V_028010_DEPTH_8_24;
131	case PIPE_FORMAT_Z32_FLOAT:
132		return V_028010_DEPTH_32_FLOAT;
133	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134		return V_028010_DEPTH_X24_8_32_FLOAT;
135	default:
136		return ~0U;
137	}
138}
139
140static uint32_t r600_translate_colorswap(enum pipe_format format)
141{
142	switch (format) {
143	/* 8-bit buffers. */
144	case PIPE_FORMAT_A8_UNORM:
145	case PIPE_FORMAT_A8_SNORM:
146	case PIPE_FORMAT_A8_UINT:
147	case PIPE_FORMAT_A8_SINT:
148	case PIPE_FORMAT_A16_UNORM:
149	case PIPE_FORMAT_A16_SNORM:
150	case PIPE_FORMAT_A16_UINT:
151	case PIPE_FORMAT_A16_SINT:
152	case PIPE_FORMAT_A16_FLOAT:
153	case PIPE_FORMAT_A32_UINT:
154	case PIPE_FORMAT_A32_SINT:
155	case PIPE_FORMAT_A32_FLOAT:
156	case PIPE_FORMAT_R4A4_UNORM:
157		return V_0280A0_SWAP_ALT_REV;
158	case PIPE_FORMAT_I8_UNORM:
159	case PIPE_FORMAT_I8_SNORM:
160	case PIPE_FORMAT_I8_UINT:
161	case PIPE_FORMAT_I8_SINT:
162	case PIPE_FORMAT_L8_UNORM:
163	case PIPE_FORMAT_L8_SNORM:
164	case PIPE_FORMAT_L8_UINT:
165	case PIPE_FORMAT_L8_SINT:
166	case PIPE_FORMAT_L8_SRGB:
167	case PIPE_FORMAT_L16_UNORM:
168	case PIPE_FORMAT_L16_SNORM:
169	case PIPE_FORMAT_L16_UINT:
170	case PIPE_FORMAT_L16_SINT:
171	case PIPE_FORMAT_L16_FLOAT:
172	case PIPE_FORMAT_L32_UINT:
173	case PIPE_FORMAT_L32_SINT:
174	case PIPE_FORMAT_L32_FLOAT:
175	case PIPE_FORMAT_I16_UNORM:
176	case PIPE_FORMAT_I16_SNORM:
177	case PIPE_FORMAT_I16_UINT:
178	case PIPE_FORMAT_I16_SINT:
179	case PIPE_FORMAT_I16_FLOAT:
180	case PIPE_FORMAT_I32_UINT:
181	case PIPE_FORMAT_I32_SINT:
182	case PIPE_FORMAT_I32_FLOAT:
183	case PIPE_FORMAT_R8_UNORM:
184	case PIPE_FORMAT_R8_SNORM:
185	case PIPE_FORMAT_R8_UINT:
186	case PIPE_FORMAT_R8_SINT:
187		return V_0280A0_SWAP_STD;
188
189	case PIPE_FORMAT_L4A4_UNORM:
190	case PIPE_FORMAT_A4R4_UNORM:
191		return V_0280A0_SWAP_ALT;
192
193	/* 16-bit buffers. */
194	case PIPE_FORMAT_B5G6R5_UNORM:
195		return V_0280A0_SWAP_STD_REV;
196
197	case PIPE_FORMAT_B5G5R5A1_UNORM:
198	case PIPE_FORMAT_B5G5R5X1_UNORM:
199		return V_0280A0_SWAP_ALT;
200
201	case PIPE_FORMAT_B4G4R4A4_UNORM:
202	case PIPE_FORMAT_B4G4R4X4_UNORM:
203		return V_0280A0_SWAP_ALT;
204
205	case PIPE_FORMAT_Z16_UNORM:
206		return V_0280A0_SWAP_STD;
207
208	case PIPE_FORMAT_L8A8_UNORM:
209	case PIPE_FORMAT_L8A8_SNORM:
210	case PIPE_FORMAT_L8A8_UINT:
211	case PIPE_FORMAT_L8A8_SINT:
212	case PIPE_FORMAT_L8A8_SRGB:
213	case PIPE_FORMAT_L16A16_UNORM:
214	case PIPE_FORMAT_L16A16_SNORM:
215	case PIPE_FORMAT_L16A16_UINT:
216	case PIPE_FORMAT_L16A16_SINT:
217	case PIPE_FORMAT_L16A16_FLOAT:
218	case PIPE_FORMAT_L32A32_UINT:
219	case PIPE_FORMAT_L32A32_SINT:
220	case PIPE_FORMAT_L32A32_FLOAT:
221		return V_0280A0_SWAP_ALT;
222	case PIPE_FORMAT_R8G8_UNORM:
223	case PIPE_FORMAT_R8G8_SNORM:
224	case PIPE_FORMAT_R8G8_UINT:
225	case PIPE_FORMAT_R8G8_SINT:
226		return V_0280A0_SWAP_STD;
227
228	case PIPE_FORMAT_R16_UNORM:
229	case PIPE_FORMAT_R16_SNORM:
230	case PIPE_FORMAT_R16_UINT:
231	case PIPE_FORMAT_R16_SINT:
232	case PIPE_FORMAT_R16_FLOAT:
233		return V_0280A0_SWAP_STD;
234
235	/* 32-bit buffers. */
236
237	case PIPE_FORMAT_A8B8G8R8_SRGB:
238		return V_0280A0_SWAP_STD_REV;
239	case PIPE_FORMAT_B8G8R8A8_SRGB:
240		return V_0280A0_SWAP_ALT;
241
242	case PIPE_FORMAT_B8G8R8A8_UNORM:
243	case PIPE_FORMAT_B8G8R8X8_UNORM:
244		return V_0280A0_SWAP_ALT;
245
246	case PIPE_FORMAT_A8R8G8B8_UNORM:
247	case PIPE_FORMAT_X8R8G8B8_UNORM:
248		return V_0280A0_SWAP_ALT_REV;
249	case PIPE_FORMAT_R8G8B8A8_SNORM:
250	case PIPE_FORMAT_R8G8B8A8_UNORM:
251	case PIPE_FORMAT_R8G8B8X8_UNORM:
252	case PIPE_FORMAT_R8G8B8A8_SINT:
253	case PIPE_FORMAT_R8G8B8A8_UINT:
254		return V_0280A0_SWAP_STD;
255
256	case PIPE_FORMAT_A8B8G8R8_UNORM:
257	case PIPE_FORMAT_X8B8G8R8_UNORM:
258	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259		return V_0280A0_SWAP_STD_REV;
260
261	case PIPE_FORMAT_Z24X8_UNORM:
262	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263		return V_0280A0_SWAP_STD;
264
265	case PIPE_FORMAT_X8Z24_UNORM:
266	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267		return V_0280A0_SWAP_STD;
268
269	case PIPE_FORMAT_R10G10B10A2_UNORM:
270	case PIPE_FORMAT_R10G10B10X2_SNORM:
271	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272		return V_0280A0_SWAP_STD;
273
274	case PIPE_FORMAT_B10G10R10A2_UNORM:
275	case PIPE_FORMAT_B10G10R10A2_UINT:
276		return V_0280A0_SWAP_ALT;
277
278	case PIPE_FORMAT_R11G11B10_FLOAT:
279	case PIPE_FORMAT_R16G16_UNORM:
280	case PIPE_FORMAT_R16G16_SNORM:
281	case PIPE_FORMAT_R16G16_FLOAT:
282	case PIPE_FORMAT_R16G16_UINT:
283	case PIPE_FORMAT_R16G16_SINT:
284	case PIPE_FORMAT_R16G16B16_FLOAT:
285	case PIPE_FORMAT_R32G32B32_FLOAT:
286	case PIPE_FORMAT_R32_UINT:
287	case PIPE_FORMAT_R32_SINT:
288	case PIPE_FORMAT_R32_FLOAT:
289	case PIPE_FORMAT_Z32_FLOAT:
290		return V_0280A0_SWAP_STD;
291
292	/* 64-bit buffers. */
293	case PIPE_FORMAT_R32G32_FLOAT:
294	case PIPE_FORMAT_R32G32_UINT:
295	case PIPE_FORMAT_R32G32_SINT:
296	case PIPE_FORMAT_R16G16B16A16_UNORM:
297	case PIPE_FORMAT_R16G16B16A16_SNORM:
298	case PIPE_FORMAT_R16G16B16A16_UINT:
299	case PIPE_FORMAT_R16G16B16A16_SINT:
300	case PIPE_FORMAT_R16G16B16A16_FLOAT:
301	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303	/* 128-bit buffers. */
304	case PIPE_FORMAT_R32G32B32A32_FLOAT:
305	case PIPE_FORMAT_R32G32B32A32_SNORM:
306	case PIPE_FORMAT_R32G32B32A32_UNORM:
307	case PIPE_FORMAT_R32G32B32A32_SINT:
308	case PIPE_FORMAT_R32G32B32A32_UINT:
309		return V_0280A0_SWAP_STD;
310	default:
311		R600_ERR("unsupported colorswap format %d\n", format);
312		return ~0U;
313	}
314	return ~0U;
315}
316
317static uint32_t r600_translate_colorformat(enum pipe_format format)
318{
319	switch (format) {
320	case PIPE_FORMAT_L4A4_UNORM:
321	case PIPE_FORMAT_R4A4_UNORM:
322	case PIPE_FORMAT_A4R4_UNORM:
323		return V_0280A0_COLOR_4_4;
324
325	/* 8-bit buffers. */
326	case PIPE_FORMAT_A8_UNORM:
327	case PIPE_FORMAT_A8_SNORM:
328	case PIPE_FORMAT_A8_UINT:
329	case PIPE_FORMAT_A8_SINT:
330	case PIPE_FORMAT_I8_UNORM:
331	case PIPE_FORMAT_I8_SNORM:
332	case PIPE_FORMAT_I8_UINT:
333	case PIPE_FORMAT_I8_SINT:
334	case PIPE_FORMAT_L8_UNORM:
335	case PIPE_FORMAT_L8_SNORM:
336	case PIPE_FORMAT_L8_UINT:
337	case PIPE_FORMAT_L8_SINT:
338	case PIPE_FORMAT_L8_SRGB:
339	case PIPE_FORMAT_R8_UNORM:
340	case PIPE_FORMAT_R8_SNORM:
341	case PIPE_FORMAT_R8_UINT:
342	case PIPE_FORMAT_R8_SINT:
343		return V_0280A0_COLOR_8;
344
345	/* 16-bit buffers. */
346	case PIPE_FORMAT_B5G6R5_UNORM:
347		return V_0280A0_COLOR_5_6_5;
348
349	case PIPE_FORMAT_B5G5R5A1_UNORM:
350	case PIPE_FORMAT_B5G5R5X1_UNORM:
351		return V_0280A0_COLOR_1_5_5_5;
352
353	case PIPE_FORMAT_B4G4R4A4_UNORM:
354	case PIPE_FORMAT_B4G4R4X4_UNORM:
355		return V_0280A0_COLOR_4_4_4_4;
356
357	case PIPE_FORMAT_Z16_UNORM:
358		return V_0280A0_COLOR_16;
359
360	case PIPE_FORMAT_L8A8_UNORM:
361	case PIPE_FORMAT_L8A8_SNORM:
362	case PIPE_FORMAT_L8A8_UINT:
363	case PIPE_FORMAT_L8A8_SINT:
364	case PIPE_FORMAT_L8A8_SRGB:
365	case PIPE_FORMAT_R8G8_UNORM:
366	case PIPE_FORMAT_R8G8_SNORM:
367	case PIPE_FORMAT_R8G8_UINT:
368	case PIPE_FORMAT_R8G8_SINT:
369		return V_0280A0_COLOR_8_8;
370
371	case PIPE_FORMAT_R16_UNORM:
372	case PIPE_FORMAT_R16_SNORM:
373	case PIPE_FORMAT_R16_UINT:
374	case PIPE_FORMAT_R16_SINT:
375	case PIPE_FORMAT_A16_UNORM:
376	case PIPE_FORMAT_A16_SNORM:
377	case PIPE_FORMAT_A16_UINT:
378	case PIPE_FORMAT_A16_SINT:
379	case PIPE_FORMAT_L16_UNORM:
380	case PIPE_FORMAT_L16_SNORM:
381	case PIPE_FORMAT_L16_UINT:
382	case PIPE_FORMAT_L16_SINT:
383	case PIPE_FORMAT_I16_UNORM:
384	case PIPE_FORMAT_I16_SNORM:
385	case PIPE_FORMAT_I16_UINT:
386	case PIPE_FORMAT_I16_SINT:
387		return V_0280A0_COLOR_16;
388
389	case PIPE_FORMAT_R16_FLOAT:
390	case PIPE_FORMAT_A16_FLOAT:
391	case PIPE_FORMAT_L16_FLOAT:
392	case PIPE_FORMAT_I16_FLOAT:
393		return V_0280A0_COLOR_16_FLOAT;
394
395	/* 32-bit buffers. */
396	case PIPE_FORMAT_A8B8G8R8_SRGB:
397	case PIPE_FORMAT_A8B8G8R8_UNORM:
398	case PIPE_FORMAT_A8R8G8B8_UNORM:
399	case PIPE_FORMAT_B8G8R8A8_SRGB:
400	case PIPE_FORMAT_B8G8R8A8_UNORM:
401	case PIPE_FORMAT_B8G8R8X8_UNORM:
402	case PIPE_FORMAT_R8G8B8A8_SNORM:
403	case PIPE_FORMAT_R8G8B8A8_UNORM:
404	case PIPE_FORMAT_R8G8B8X8_UNORM:
405	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406	case PIPE_FORMAT_X8B8G8R8_UNORM:
407	case PIPE_FORMAT_X8R8G8B8_UNORM:
408	case PIPE_FORMAT_R8G8B8_UNORM:
409	case PIPE_FORMAT_R8G8B8A8_SINT:
410	case PIPE_FORMAT_R8G8B8A8_UINT:
411		return V_0280A0_COLOR_8_8_8_8;
412
413	case PIPE_FORMAT_R10G10B10A2_UNORM:
414	case PIPE_FORMAT_R10G10B10X2_SNORM:
415	case PIPE_FORMAT_B10G10R10A2_UNORM:
416	case PIPE_FORMAT_B10G10R10A2_UINT:
417	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
418		return V_0280A0_COLOR_2_10_10_10;
419
420	case PIPE_FORMAT_Z24X8_UNORM:
421	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
422		return V_0280A0_COLOR_8_24;
423
424	case PIPE_FORMAT_X8Z24_UNORM:
425	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
426		return V_0280A0_COLOR_24_8;
427
428	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
429		return V_0280A0_COLOR_X24_8_32_FLOAT;
430
431	case PIPE_FORMAT_R32_UINT:
432	case PIPE_FORMAT_R32_SINT:
433	case PIPE_FORMAT_A32_UINT:
434	case PIPE_FORMAT_A32_SINT:
435	case PIPE_FORMAT_L32_UINT:
436	case PIPE_FORMAT_L32_SINT:
437	case PIPE_FORMAT_I32_UINT:
438	case PIPE_FORMAT_I32_SINT:
439		return V_0280A0_COLOR_32;
440
441	case PIPE_FORMAT_R32_FLOAT:
442	case PIPE_FORMAT_A32_FLOAT:
443	case PIPE_FORMAT_L32_FLOAT:
444	case PIPE_FORMAT_I32_FLOAT:
445	case PIPE_FORMAT_Z32_FLOAT:
446		return V_0280A0_COLOR_32_FLOAT;
447
448	case PIPE_FORMAT_R16G16_FLOAT:
449	case PIPE_FORMAT_L16A16_FLOAT:
450		return V_0280A0_COLOR_16_16_FLOAT;
451
452	case PIPE_FORMAT_R16G16_UNORM:
453	case PIPE_FORMAT_R16G16_SNORM:
454	case PIPE_FORMAT_R16G16_UINT:
455	case PIPE_FORMAT_R16G16_SINT:
456	case PIPE_FORMAT_L16A16_UNORM:
457	case PIPE_FORMAT_L16A16_SNORM:
458	case PIPE_FORMAT_L16A16_UINT:
459	case PIPE_FORMAT_L16A16_SINT:
460		return V_0280A0_COLOR_16_16;
461
462	case PIPE_FORMAT_R11G11B10_FLOAT:
463		return V_0280A0_COLOR_10_11_11_FLOAT;
464
465	/* 64-bit buffers. */
466	case PIPE_FORMAT_R16G16B16A16_UINT:
467	case PIPE_FORMAT_R16G16B16A16_SINT:
468	case PIPE_FORMAT_R16G16B16A16_UNORM:
469	case PIPE_FORMAT_R16G16B16A16_SNORM:
470		return V_0280A0_COLOR_16_16_16_16;
471
472	case PIPE_FORMAT_R16G16B16_FLOAT:
473	case PIPE_FORMAT_R16G16B16A16_FLOAT:
474		return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476	case PIPE_FORMAT_R32G32_FLOAT:
477	case PIPE_FORMAT_L32A32_FLOAT:
478		return V_0280A0_COLOR_32_32_FLOAT;
479
480	case PIPE_FORMAT_R32G32_SINT:
481	case PIPE_FORMAT_R32G32_UINT:
482	case PIPE_FORMAT_L32A32_UINT:
483	case PIPE_FORMAT_L32A32_SINT:
484		return V_0280A0_COLOR_32_32;
485
486	/* 96-bit buffers. */
487	case PIPE_FORMAT_R32G32B32_FLOAT:
488		return V_0280A0_COLOR_32_32_32_FLOAT;
489
490	/* 128-bit buffers. */
491	case PIPE_FORMAT_R32G32B32A32_FLOAT:
492		return V_0280A0_COLOR_32_32_32_32_FLOAT;
493	case PIPE_FORMAT_R32G32B32A32_SNORM:
494	case PIPE_FORMAT_R32G32B32A32_UNORM:
495	case PIPE_FORMAT_R32G32B32A32_SINT:
496	case PIPE_FORMAT_R32G32B32A32_UINT:
497		return V_0280A0_COLOR_32_32_32_32;
498
499	/* YUV buffers. */
500	case PIPE_FORMAT_UYVY:
501	case PIPE_FORMAT_YUYV:
502	default:
503		return ~0U; /* Unsupported. */
504	}
505}
506
507static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508{
509	if (R600_BIG_ENDIAN) {
510		switch(colorformat) {
511		case V_0280A0_COLOR_4_4:
512			return ENDIAN_NONE;
513
514		/* 8-bit buffers. */
515		case V_0280A0_COLOR_8:
516			return ENDIAN_NONE;
517
518		/* 16-bit buffers. */
519		case V_0280A0_COLOR_5_6_5:
520		case V_0280A0_COLOR_1_5_5_5:
521		case V_0280A0_COLOR_4_4_4_4:
522		case V_0280A0_COLOR_16:
523		case V_0280A0_COLOR_8_8:
524			return ENDIAN_8IN16;
525
526		/* 32-bit buffers. */
527		case V_0280A0_COLOR_8_8_8_8:
528		case V_0280A0_COLOR_2_10_10_10:
529		case V_0280A0_COLOR_8_24:
530		case V_0280A0_COLOR_24_8:
531		case V_0280A0_COLOR_32_FLOAT:
532		case V_0280A0_COLOR_16_16_FLOAT:
533		case V_0280A0_COLOR_16_16:
534			return ENDIAN_8IN32;
535
536		/* 64-bit buffers. */
537		case V_0280A0_COLOR_16_16_16_16:
538		case V_0280A0_COLOR_16_16_16_16_FLOAT:
539			return ENDIAN_8IN16;
540
541		case V_0280A0_COLOR_32_32_FLOAT:
542		case V_0280A0_COLOR_32_32:
543		case V_0280A0_COLOR_X24_8_32_FLOAT:
544			return ENDIAN_8IN32;
545
546		/* 128-bit buffers. */
547		case V_0280A0_COLOR_32_32_32_FLOAT:
548		case V_0280A0_COLOR_32_32_32_32_FLOAT:
549		case V_0280A0_COLOR_32_32_32_32:
550			return ENDIAN_8IN32;
551		default:
552			return ENDIAN_NONE; /* Unsupported. */
553		}
554	} else {
555		return ENDIAN_NONE;
556	}
557}
558
559static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
560{
561	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
562}
563
564static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
565{
566	return r600_translate_colorformat(format) != ~0U &&
567	       r600_translate_colorswap(format) != ~0U;
568}
569
570static bool r600_is_zs_format_supported(enum pipe_format format)
571{
572	return r600_translate_dbformat(format) != ~0U;
573}
574
575boolean r600_is_format_supported(struct pipe_screen *screen,
576				 enum pipe_format format,
577				 enum pipe_texture_target target,
578				 unsigned sample_count,
579				 unsigned usage)
580{
581	unsigned retval = 0;
582
583	if (target >= PIPE_MAX_TEXTURE_TYPES) {
584		R600_ERR("r600: unsupported texture type %d\n", target);
585		return FALSE;
586	}
587
588	if (!util_format_is_supported(format, usage))
589		return FALSE;
590
591	/* Multisample */
592	if (sample_count > 1)
593		return FALSE;
594
595	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
596	    r600_is_sampler_format_supported(screen, format)) {
597		retval |= PIPE_BIND_SAMPLER_VIEW;
598	}
599
600	if ((usage & (PIPE_BIND_RENDER_TARGET |
601		      PIPE_BIND_DISPLAY_TARGET |
602		      PIPE_BIND_SCANOUT |
603		      PIPE_BIND_SHARED)) &&
604	    r600_is_colorbuffer_format_supported(format)) {
605		retval |= usage &
606			  (PIPE_BIND_RENDER_TARGET |
607			   PIPE_BIND_DISPLAY_TARGET |
608			   PIPE_BIND_SCANOUT |
609			   PIPE_BIND_SHARED);
610	}
611
612	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
613	    r600_is_zs_format_supported(format)) {
614		retval |= PIPE_BIND_DEPTH_STENCIL;
615	}
616
617	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
618	    r600_is_vertex_format_supported(format)) {
619		retval |= PIPE_BIND_VERTEX_BUFFER;
620	}
621
622	if (usage & PIPE_BIND_TRANSFER_READ)
623		retval |= PIPE_BIND_TRANSFER_READ;
624	if (usage & PIPE_BIND_TRANSFER_WRITE)
625		retval |= PIPE_BIND_TRANSFER_WRITE;
626
627	return retval == usage;
628}
629
630void r600_polygon_offset_update(struct r600_context *rctx)
631{
632	struct r600_pipe_state state;
633
634	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
635	state.nregs = 0;
636	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
637		float offset_units = rctx->rasterizer->offset_units;
638		unsigned offset_db_fmt_cntl = 0, depth;
639
640		switch (rctx->framebuffer.zsbuf->format) {
641		case PIPE_FORMAT_Z24X8_UNORM:
642		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
643			depth = -24;
644			offset_units *= 2.0f;
645			break;
646		case PIPE_FORMAT_Z32_FLOAT:
647		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
648			depth = -23;
649			offset_units *= 1.0f;
650			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
651			break;
652		case PIPE_FORMAT_Z16_UNORM:
653			depth = -16;
654			offset_units *= 4.0f;
655			break;
656		default:
657			return;
658		}
659		/* XXX some of those reg can be computed with cso */
660		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
661		r600_pipe_state_add_reg(&state,
662				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
663				fui(rctx->rasterizer->offset_scale));
664		r600_pipe_state_add_reg(&state,
665				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
666				fui(offset_units));
667		r600_pipe_state_add_reg(&state,
668				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
669				fui(rctx->rasterizer->offset_scale));
670		r600_pipe_state_add_reg(&state,
671				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
672				fui(offset_units));
673		r600_pipe_state_add_reg(&state,
674				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
675				offset_db_fmt_cntl);
676		r600_context_pipe_state_set(rctx, &state);
677	}
678}
679
680static void *r600_create_blend_state(struct pipe_context *ctx,
681					const struct pipe_blend_state *state)
682{
683	struct r600_context *rctx = (struct r600_context *)ctx;
684	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
685	struct r600_pipe_state *rstate;
686	uint32_t color_control = 0, target_mask;
687
688	if (blend == NULL) {
689		return NULL;
690	}
691	rstate = &blend->rstate;
692
693	rstate->id = R600_PIPE_STATE_BLEND;
694
695	target_mask = 0;
696
697	/* R600 does not support per-MRT blends */
698	if (rctx->family > CHIP_R600)
699		color_control |= S_028808_PER_MRT_BLEND(1);
700	if (state->logicop_enable) {
701		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
702	} else {
703		color_control |= (0xcc << 16);
704	}
705	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
706	if (state->independent_blend_enable) {
707		for (int i = 0; i < 8; i++) {
708			if (state->rt[i].blend_enable) {
709				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
710			}
711			target_mask |= (state->rt[i].colormask << (4 * i));
712		}
713	} else {
714		for (int i = 0; i < 8; i++) {
715			if (state->rt[0].blend_enable) {
716				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
717			}
718			target_mask |= (state->rt[0].colormask << (4 * i));
719		}
720	}
721
722	if (target_mask)
723		color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL);
724	else
725		color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
726
727	blend->cb_target_mask = target_mask;
728	blend->cb_color_control = color_control;
729	/* only MRT0 has dual src blend */
730	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
731	for (int i = 0; i < 8; i++) {
732		/* state->rt entries > 0 only written if independent blending */
733		const int j = state->independent_blend_enable ? i : 0;
734
735		unsigned eqRGB = state->rt[j].rgb_func;
736		unsigned srcRGB = state->rt[j].rgb_src_factor;
737		unsigned dstRGB = state->rt[j].rgb_dst_factor;
738
739		unsigned eqA = state->rt[j].alpha_func;
740		unsigned srcA = state->rt[j].alpha_src_factor;
741		unsigned dstA = state->rt[j].alpha_dst_factor;
742		uint32_t bc = 0;
743
744		if (!state->rt[j].blend_enable)
745			continue;
746
747		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
748		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
749		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
750
751		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
752			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
753			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
754			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
755			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
756		}
757
758		/* R600 does not support per-MRT blends */
759		if (rctx->family > CHIP_R600)
760			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
761		if (i == 0)
762			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
763	}
764	return rstate;
765}
766
767static void *r600_create_dsa_state(struct pipe_context *ctx,
768				   const struct pipe_depth_stencil_alpha_state *state)
769{
770	struct r600_context *rctx = (struct r600_context *)ctx;
771	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
772	unsigned db_depth_control, alpha_test_control, alpha_ref;
773	struct r600_pipe_state *rstate;
774
775	if (dsa == NULL) {
776		return NULL;
777	}
778
779	dsa->valuemask[0] = state->stencil[0].valuemask;
780	dsa->valuemask[1] = state->stencil[1].valuemask;
781	dsa->writemask[0] = state->stencil[0].writemask;
782	dsa->writemask[1] = state->stencil[1].writemask;
783
784	rstate = &dsa->rstate;
785
786	rstate->id = R600_PIPE_STATE_DSA;
787	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
788		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
789		S_028800_ZFUNC(state->depth.func);
790
791	/* stencil */
792	if (state->stencil[0].enabled) {
793		db_depth_control |= S_028800_STENCIL_ENABLE(1);
794		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
795		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
796		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
797		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
798
799		if (state->stencil[1].enabled) {
800			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
801			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
802			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
803			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
804			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
805		}
806	}
807
808	/* alpha */
809	alpha_test_control = 0;
810	alpha_ref = 0;
811	if (state->alpha.enabled) {
812		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
813		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
814		alpha_ref = fui(state->alpha.ref_value);
815	}
816	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
817	dsa->alpha_ref = alpha_ref;
818
819	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
820	return rstate;
821}
822
823static void *r600_create_rs_state(struct pipe_context *ctx,
824				  const struct pipe_rasterizer_state *state)
825{
826	struct r600_context *rctx = (struct r600_context *)ctx;
827	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
828	struct r600_pipe_state *rstate;
829	unsigned tmp;
830	unsigned prov_vtx = 1, polygon_dual_mode;
831	unsigned sc_mode_cntl;
832	float psize_min, psize_max;
833
834	if (rs == NULL) {
835		return NULL;
836	}
837
838	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
839				state->fill_back != PIPE_POLYGON_MODE_FILL);
840
841	if (state->flatshade_first)
842		prov_vtx = 0;
843
844	rstate = &rs->rstate;
845	rs->flatshade = state->flatshade;
846	rs->sprite_coord_enable = state->sprite_coord_enable;
847	rs->two_side = state->light_twoside;
848	rs->clip_plane_enable = state->clip_plane_enable;
849	rs->pa_sc_line_stipple = state->line_stipple_enable ?
850				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
851				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
852	rs->pa_cl_clip_cntl =
853		S_028810_PS_UCP_MODE(3) |
854		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
855		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
856		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
857
858	/* offset */
859	rs->offset_units = state->offset_units;
860	rs->offset_scale = state->offset_scale * 12.0f;
861
862	rstate->id = R600_PIPE_STATE_RASTERIZER;
863	tmp = S_0286D4_FLAT_SHADE_ENA(1);
864	if (state->sprite_coord_enable) {
865		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
866			S_0286D4_PNT_SPRITE_OVRD_X(2) |
867			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
868			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
869			S_0286D4_PNT_SPRITE_OVRD_W(1);
870		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
871			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
872		}
873	}
874	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
875
876	/* point size 12.4 fixed point */
877	tmp = r600_pack_float_12p4(state->point_size/2);
878	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
879
880	if (state->point_size_per_vertex) {
881		psize_min = util_get_min_point_size(state);
882		psize_max = 8192;
883	} else {
884		/* Force the point size to be as if the vertex output was disabled. */
885		psize_min = state->point_size;
886		psize_max = state->point_size;
887	}
888	/* Divide by two, because 0.5 = 1 pixel. */
889	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
890				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
891				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
892
893	tmp = r600_pack_float_12p4(state->line_width/2);
894	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
895
896	if (rctx->chip_class >= R700) {
897		sc_mode_cntl =
898			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
899			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
900			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
901			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
902	} else {
903		sc_mode_cntl =
904			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
905			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
906		rs->scissor_enable = state->scissor;
907	}
908	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
909
910	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
911
912	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
913				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
914
915	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
916	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
917				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
918				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
919				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
920				S_028814_FACE(!state->front_ccw) |
921				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
922				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
923				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
924				S_028814_POLY_MODE(polygon_dual_mode) |
925				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
926				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
927	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
928	return rstate;
929}
930
931static void *r600_create_sampler_state(struct pipe_context *ctx,
932					const struct pipe_sampler_state *state)
933{
934	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
935	struct r600_pipe_state *rstate;
936	union util_color uc;
937	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
938
939	if (ss == NULL) {
940		return NULL;
941	}
942
943	ss->seamless_cube_map = state->seamless_cube_map;
944	rstate = &ss->rstate;
945	rstate->id = R600_PIPE_STATE_SAMPLER;
946	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
947	r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
948					S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
949					S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
950					S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
951					S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
952					S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
953					S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
954					S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
955					S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
956					S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
957	r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
958					S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
959					S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
960					S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
961	r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
962	if (uc.ui) {
963		r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
964		r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
965		r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
966		r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
967	}
968	return rstate;
969}
970
971static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
972							struct pipe_resource *texture,
973							const struct pipe_sampler_view *state)
974{
975	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
976	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
977	struct r600_pipe_resource_state *rstate;
978	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
979	unsigned format, endian;
980	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
981	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
982	unsigned width, height, depth, offset_level, last_level;
983
984	if (view == NULL)
985		return NULL;
986	rstate = &view->state;
987
988	/* initialize base object */
989	view->base = *state;
990	view->base.texture = NULL;
991	pipe_reference(NULL, &texture->reference);
992	view->base.texture = texture;
993	view->base.reference.count = 1;
994	view->base.context = ctx;
995
996	swizzle[0] = state->swizzle_r;
997	swizzle[1] = state->swizzle_g;
998	swizzle[2] = state->swizzle_b;
999	swizzle[3] = state->swizzle_a;
1000
1001	format = r600_translate_texformat(ctx->screen, state->format,
1002					  swizzle,
1003					  &word4, &yuv_format);
1004	assert(format != ~0);
1005	if (format == ~0) {
1006		FREE(view);
1007		return NULL;
1008	}
1009
1010	if (tmp->is_depth && !tmp->is_flushing_texture) {
1011		r600_init_flushed_depth_texture(ctx, texture, NULL);
1012		tmp = tmp->flushed_depth_texture;
1013		if (!tmp) {
1014			FREE(view);
1015			return NULL;
1016		}
1017	}
1018
1019	endian = r600_colorformat_endian_swap(format);
1020
1021	offset_level = state->u.tex.first_level;
1022	last_level = state->u.tex.last_level - offset_level;
1023	if (!rscreen->use_surface_alloc) {
1024		width = u_minify(texture->width0, offset_level);
1025		height = u_minify(texture->height0, offset_level);
1026		depth = u_minify(texture->depth0, offset_level);
1027
1028		pitch = align(tmp->pitch_in_blocks[offset_level] *
1029				util_format_get_blockwidth(state->format), 8);
1030		array_mode = tmp->array_mode[offset_level];
1031		tile_type = tmp->tile_type;
1032
1033		if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1034			height = 1;
1035			depth = texture->array_size;
1036		} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1037			depth = texture->array_size;
1038		}
1039
1040		rstate->bo[0] = &tmp->resource;
1041		rstate->bo[1] = &tmp->resource;
1042		rstate->bo_usage[0] = RADEON_USAGE_READ;
1043		rstate->bo_usage[1] = RADEON_USAGE_READ;
1044
1045		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1046				S_038000_TILE_MODE(array_mode) |
1047				S_038000_TILE_TYPE(tile_type) |
1048				S_038000_PITCH((pitch / 8) - 1) |
1049				S_038000_TEX_WIDTH(width - 1));
1050		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1051				S_038004_TEX_DEPTH(depth - 1) |
1052				S_038004_DATA_FORMAT(format));
1053		rstate->val[2] = tmp->offset[offset_level] >> 8;
1054		rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1055		rstate->val[4] = (word4 |
1056				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1057				S_038010_REQUEST_SIZE(1) |
1058				S_038010_ENDIAN_SWAP(endian) |
1059				S_038010_BASE_LEVEL(0));
1060		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1061				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1062				S_038014_LAST_ARRAY(state->u.tex.last_layer));
1063		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1064				S_038018_MAX_ANISO(4 /* max 16 samples */));
1065	} else {
1066		width = tmp->surface.level[offset_level].npix_x;
1067		height = tmp->surface.level[offset_level].npix_y;
1068		depth = tmp->surface.level[offset_level].npix_z;
1069		pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1070		tile_type = tmp->tile_type;
1071
1072		if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1073			height = 1;
1074			depth = texture->array_size;
1075		} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1076			depth = texture->array_size;
1077		}
1078		switch (tmp->surface.level[offset_level].mode) {
1079		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1080			array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1081			break;
1082		case RADEON_SURF_MODE_1D:
1083			array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1084			break;
1085		case RADEON_SURF_MODE_2D:
1086			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1087			break;
1088		case RADEON_SURF_MODE_LINEAR:
1089		default:
1090			array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1091			break;
1092		}
1093
1094		rstate->bo[0] = &tmp->resource;
1095		rstate->bo[1] = &tmp->resource;
1096		rstate->bo_usage[0] = RADEON_USAGE_READ;
1097		rstate->bo_usage[1] = RADEON_USAGE_READ;
1098
1099		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1100				S_038000_TILE_MODE(array_mode) |
1101				S_038000_TILE_TYPE(tile_type) |
1102				S_038000_PITCH((pitch / 8) - 1) |
1103				S_038000_TEX_WIDTH(width - 1));
1104		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1105				S_038004_TEX_DEPTH(depth - 1) |
1106				S_038004_DATA_FORMAT(format));
1107		rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1108		if (offset_level >= tmp->surface.last_level) {
1109			rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1110		} else {
1111			rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1112		}
1113		rstate->val[4] = (word4 |
1114				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1115				S_038010_REQUEST_SIZE(1) |
1116				S_038010_ENDIAN_SWAP(endian) |
1117				S_038010_BASE_LEVEL(0));
1118		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1119				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1120				S_038014_LAST_ARRAY(state->u.tex.last_layer));
1121		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1122				S_038018_MAX_ANISO(4 /* max 16 samples */));
1123	}
1124	return &view->base;
1125}
1126
1127static void r600_set_sampler_views(struct r600_context *rctx,
1128				   struct r600_textures_info *dst,
1129				   unsigned count,
1130				   struct pipe_sampler_view **views,
1131				   void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1132{
1133	struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1134	unsigned i;
1135
1136	if (count)
1137		r600_inval_texture_cache(rctx);
1138
1139	for (i = 0; i < count; i++) {
1140		if (rviews[i]) {
1141			if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
1142				rctx->have_depth_texture = true;
1143
1144			/* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1145			if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1146			     rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1147				dst->samplers_dirty = true;
1148
1149			set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1150		} else {
1151			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1152		}
1153
1154		pipe_sampler_view_reference(
1155			(struct pipe_sampler_view **)&dst->views[i],
1156			views[i]);
1157	}
1158
1159	for (i = count; i < dst->n_views; i++) {
1160		if (dst->views[i]) {
1161			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1162			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1163		}
1164	}
1165
1166	dst->n_views = count;
1167}
1168
1169static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1170				      struct pipe_sampler_view **views)
1171{
1172	struct r600_context *rctx = (struct r600_context *)ctx;
1173	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1174			       r600_context_pipe_state_set_vs_resource);
1175}
1176
1177static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1178				      struct pipe_sampler_view **views)
1179{
1180	struct r600_context *rctx = (struct r600_context *)ctx;
1181	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1182			       r600_context_pipe_state_set_ps_resource);
1183}
1184
1185static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1186{
1187	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1188	if (rstate == NULL)
1189		return;
1190
1191	rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1192	r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1193				(enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1194				S_009508_DISABLE_CUBE_ANISO(1) |
1195				S_009508_SYNC_GRADIENT(1) |
1196				S_009508_SYNC_WALKER(1) |
1197				S_009508_SYNC_ALIGNER(1));
1198
1199	free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1200	rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1201	r600_context_pipe_state_set(rctx, rstate);
1202}
1203
1204static void r600_bind_samplers(struct r600_context *rctx,
1205			       struct r600_textures_info *dst,
1206			       unsigned count, void **states)
1207{
1208	memcpy(dst->samplers, states, sizeof(void*) * count);
1209	dst->n_samplers = count;
1210	dst->samplers_dirty = true;
1211}
1212
1213static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1214{
1215	struct r600_context *rctx = (struct r600_context *)ctx;
1216	r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1217}
1218
1219static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1220{
1221	struct r600_context *rctx = (struct r600_context *)ctx;
1222	r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1223}
1224
1225static void r600_update_samplers(struct r600_context *rctx,
1226				 struct r600_textures_info *tex,
1227				 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1228{
1229	unsigned i;
1230
1231	if (tex->samplers_dirty) {
1232		int seamless = -1;
1233		for (i = 0; i < tex->n_samplers; i++) {
1234			if (!tex->samplers[i])
1235				continue;
1236
1237			/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1238			 * filtering between layers.
1239			 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1240			if (tex->views[i]) {
1241				if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1242				    tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1243					tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1244					tex->is_array_sampler[i] = true;
1245				} else {
1246					tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1247					tex->is_array_sampler[i] = false;
1248				}
1249			}
1250
1251			set_sampler(rctx, &tex->samplers[i]->rstate, i);
1252
1253			if (tex->samplers[i])
1254				seamless = tex->samplers[i]->seamless_cube_map;
1255		}
1256
1257		if (seamless != -1)
1258			r600_set_seamless_cubemap(rctx, seamless);
1259
1260		tex->samplers_dirty = false;
1261	}
1262}
1263
1264void r600_update_sampler_states(struct r600_context *rctx)
1265{
1266	r600_update_samplers(rctx, &rctx->vs_samplers,
1267			     r600_context_pipe_state_set_vs_sampler);
1268	r600_update_samplers(rctx, &rctx->ps_samplers,
1269			     r600_context_pipe_state_set_ps_sampler);
1270}
1271
1272static void r600_set_clip_state(struct pipe_context *ctx,
1273				const struct pipe_clip_state *state)
1274{
1275	struct r600_context *rctx = (struct r600_context *)ctx;
1276	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1277	struct pipe_constant_buffer cb;
1278
1279	if (rstate == NULL)
1280		return;
1281
1282	rctx->clip = *state;
1283	rstate->id = R600_PIPE_STATE_CLIP;
1284	for (int i = 0; i < 6; i++) {
1285		r600_pipe_state_add_reg(rstate,
1286					R_028E20_PA_CL_UCP0_X + i * 16,
1287					fui(state->ucp[i][0]));
1288		r600_pipe_state_add_reg(rstate,
1289					R_028E24_PA_CL_UCP0_Y + i * 16,
1290					fui(state->ucp[i][1]) );
1291		r600_pipe_state_add_reg(rstate,
1292					R_028E28_PA_CL_UCP0_Z + i * 16,
1293					fui(state->ucp[i][2]));
1294		r600_pipe_state_add_reg(rstate,
1295					R_028E2C_PA_CL_UCP0_W + i * 16,
1296					fui(state->ucp[i][3]));
1297	}
1298
1299	free(rctx->states[R600_PIPE_STATE_CLIP]);
1300	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1301	r600_context_pipe_state_set(rctx, rstate);
1302
1303	cb.buffer = NULL;
1304	cb.user_buffer = state->ucp;
1305	cb.buffer_offset = 0;
1306	cb.buffer_size = 4*4*8;
1307	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1308	pipe_resource_reference(&cb.buffer, NULL);
1309}
1310
1311static void r600_set_polygon_stipple(struct pipe_context *ctx,
1312					 const struct pipe_poly_stipple *state)
1313{
1314}
1315
1316static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1317{
1318}
1319
1320void r600_set_scissor_state(struct r600_context *rctx,
1321			    const struct pipe_scissor_state *state)
1322{
1323	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1324	uint32_t tl, br;
1325
1326	if (rstate == NULL)
1327		return;
1328
1329	rstate->id = R600_PIPE_STATE_SCISSOR;
1330	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1331	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1332	r600_pipe_state_add_reg(rstate,
1333				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1334	r600_pipe_state_add_reg(rstate,
1335				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1336
1337	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1338	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1339	r600_context_pipe_state_set(rctx, rstate);
1340}
1341
1342static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1343					const struct pipe_scissor_state *state)
1344{
1345	struct r600_context *rctx = (struct r600_context *)ctx;
1346
1347	if (rctx->chip_class == R600) {
1348		rctx->scissor_state = *state;
1349
1350		if (!rctx->scissor_enable)
1351			return;
1352	}
1353
1354	r600_set_scissor_state(rctx, state);
1355}
1356
1357static void r600_set_viewport_state(struct pipe_context *ctx,
1358					const struct pipe_viewport_state *state)
1359{
1360	struct r600_context *rctx = (struct r600_context *)ctx;
1361	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1362
1363	if (rstate == NULL)
1364		return;
1365
1366	rctx->viewport = *state;
1367	rstate->id = R600_PIPE_STATE_VIEWPORT;
1368	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1369	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1370	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1371	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1372	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1373	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1374
1375	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1376	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1377	r600_context_pipe_state_set(rctx, rstate);
1378}
1379
1380static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1381			const struct pipe_framebuffer_state *state, int cb)
1382{
1383	struct r600_screen *rscreen = rctx->screen;
1384	struct r600_resource_texture *rtex;
1385	struct r600_surface *surf;
1386	unsigned level = state->cbufs[cb]->u.tex.level;
1387	unsigned pitch, slice;
1388	unsigned color_info;
1389	unsigned format, swap, ntype, endian;
1390	unsigned offset;
1391	const struct util_format_description *desc;
1392	int i;
1393	unsigned blend_bypass = 0, blend_clamp = 1;
1394
1395	surf = (struct r600_surface *)state->cbufs[cb];
1396	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1397
1398	if (rtex->is_depth)
1399		rctx->have_depth_fb = TRUE;
1400
1401	if (rtex->is_depth && !rtex->is_flushing_texture) {
1402		rtex = rtex->flushed_depth_texture;
1403	}
1404
1405	/* XXX quite sure for dx10+ hw don't need any offset hacks */
1406	if (!rscreen->use_surface_alloc) {
1407		offset = r600_texture_get_offset(rtex,
1408						 level, state->cbufs[cb]->u.tex.first_layer);
1409		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1410		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1411		if (slice) {
1412			slice = slice - 1;
1413		}
1414		color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1415	} else {
1416		offset = rtex->surface.level[level].offset;
1417		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1418			offset += rtex->surface.level[level].slice_size *
1419				  state->cbufs[cb]->u.tex.first_layer;
1420		}
1421		pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1422		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1423		if (slice) {
1424			slice = slice - 1;
1425		}
1426		color_info = 0;
1427		switch (rtex->surface.level[level].mode) {
1428		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1429			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1430			break;
1431		case RADEON_SURF_MODE_1D:
1432			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1433			break;
1434		case RADEON_SURF_MODE_2D:
1435			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1436			break;
1437		case RADEON_SURF_MODE_LINEAR:
1438		default:
1439			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1440			break;
1441		}
1442	}
1443	desc = util_format_description(surf->base.format);
1444
1445	for (i = 0; i < 4; i++) {
1446		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1447			break;
1448		}
1449	}
1450
1451	ntype = V_0280A0_NUMBER_UNORM;
1452	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1453		ntype = V_0280A0_NUMBER_SRGB;
1454	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1455		if (desc->channel[i].normalized)
1456			ntype = V_0280A0_NUMBER_SNORM;
1457		else if (desc->channel[i].pure_integer)
1458			ntype = V_0280A0_NUMBER_SINT;
1459	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1460		if (desc->channel[i].normalized)
1461			ntype = V_0280A0_NUMBER_UNORM;
1462		else if (desc->channel[i].pure_integer)
1463			ntype = V_0280A0_NUMBER_UINT;
1464	}
1465
1466	format = r600_translate_colorformat(surf->base.format);
1467	assert(format != ~0);
1468
1469	swap = r600_translate_colorswap(surf->base.format);
1470	assert(swap != ~0);
1471
1472	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1473		endian = ENDIAN_NONE;
1474	} else {
1475		endian = r600_colorformat_endian_swap(format);
1476	}
1477
1478	/* set blend bypass according to docs if SINT/UINT or
1479	   8/24 COLOR variants */
1480	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1481	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1482	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1483		blend_clamp = 0;
1484		blend_bypass = 1;
1485	}
1486
1487	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
1488		rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1489	else
1490		rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1491
1492	color_info |= S_0280A0_FORMAT(format) |
1493		S_0280A0_COMP_SWAP(swap) |
1494		S_0280A0_BLEND_BYPASS(blend_bypass) |
1495		S_0280A0_BLEND_CLAMP(blend_clamp) |
1496		S_0280A0_NUMBER_TYPE(ntype) |
1497		S_0280A0_ENDIAN(endian);
1498
1499	/* EXPORT_NORM is an optimzation that can be enabled for better
1500	 * performance in certain cases
1501	 */
1502	if (rctx->chip_class == R600) {
1503		/* EXPORT_NORM can be enabled if:
1504		 * - 11-bit or smaller UNORM/SNORM/SRGB
1505		 * - BLEND_CLAMP is enabled
1506		 * - BLEND_FLOAT32 is disabled
1507		 */
1508		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1509		    (desc->channel[i].size < 12 &&
1510		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1511		     ntype != V_0280A0_NUMBER_UINT &&
1512		     ntype != V_0280A0_NUMBER_SINT) &&
1513		    G_0280A0_BLEND_CLAMP(color_info) &&
1514		    !G_0280A0_BLEND_FLOAT32(color_info)) {
1515			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1516		} else {
1517			rctx->export_16bpc = false;
1518		}
1519	} else {
1520		/* EXPORT_NORM can be enabled if:
1521		 * - 11-bit or smaller UNORM/SNORM/SRGB
1522		 * - 16-bit or smaller FLOAT
1523		 */
1524		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1525		    ((desc->channel[i].size < 12 &&
1526		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1527		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1528		    (desc->channel[i].size < 17 &&
1529		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1530			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1531		} else {
1532			rctx->export_16bpc = false;
1533		}
1534	}
1535
1536	/* for possible dual-src MRT write color info 1 */
1537	if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1538		r600_pipe_state_add_reg_bo(rstate,
1539				R_0280A0_CB_COLOR0_INFO + 1 * 4,
1540				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1541	}
1542
1543	r600_pipe_state_add_reg_bo(rstate,
1544				R_028040_CB_COLOR0_BASE + cb * 4,
1545				offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1546	r600_pipe_state_add_reg_bo(rstate,
1547				R_0280A0_CB_COLOR0_INFO + cb * 4,
1548				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1549	r600_pipe_state_add_reg(rstate,
1550				R_028060_CB_COLOR0_SIZE + cb * 4,
1551				S_028060_PITCH_TILE_MAX(pitch) |
1552				S_028060_SLICE_TILE_MAX(slice));
1553	if (!rscreen->use_surface_alloc) {
1554		r600_pipe_state_add_reg(rstate,
1555					R_028080_CB_COLOR0_VIEW + cb * 4,
1556					0x00000000);
1557	} else {
1558		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1559			r600_pipe_state_add_reg(rstate,
1560						R_028080_CB_COLOR0_VIEW + cb * 4,
1561						0x00000000);
1562		} else {
1563			r600_pipe_state_add_reg(rstate,
1564						R_028080_CB_COLOR0_VIEW + cb * 4,
1565						S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1566						S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1567		}
1568	}
1569	r600_pipe_state_add_reg_bo(rstate,
1570				   R_0280E0_CB_COLOR0_FRAG + cb * 4,
1571				   0, &rtex->resource, RADEON_USAGE_READWRITE);
1572	r600_pipe_state_add_reg_bo(rstate,
1573				   R_0280C0_CB_COLOR0_TILE + cb * 4,
1574				   0, &rtex->resource, RADEON_USAGE_READWRITE);
1575}
1576
1577static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1578			const struct pipe_framebuffer_state *state)
1579{
1580	struct r600_screen *rscreen = rctx->screen;
1581	struct r600_resource_texture *rtex;
1582	struct r600_surface *surf;
1583	unsigned level, pitch, slice, format, offset, array_mode;
1584
1585	if (state->zsbuf == NULL)
1586		return;
1587
1588	level = state->zsbuf->u.tex.level;
1589
1590	surf = (struct r600_surface *)state->zsbuf;
1591	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1592
1593	if (!rscreen->use_surface_alloc) {
1594		/* XXX remove this once tiling is properly supported */
1595		array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1596			V_0280A0_ARRAY_1D_TILED_THIN1;
1597
1598		/* XXX quite sure for dx10+ hw don't need any offset hacks */
1599		offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1600				level, state->zsbuf->u.tex.first_layer);
1601		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1602		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1603		if (slice) {
1604			slice = slice - 1;
1605		}
1606	} else {
1607		offset = rtex->surface.level[level].offset;
1608		pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1609		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1610		if (slice) {
1611			slice = slice - 1;
1612		}
1613		switch (rtex->surface.level[level].mode) {
1614		case RADEON_SURF_MODE_2D:
1615			array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1616			break;
1617		case RADEON_SURF_MODE_1D:
1618		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1619		case RADEON_SURF_MODE_LINEAR:
1620		default:
1621			array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1622			break;
1623		}
1624	}
1625
1626	format = r600_translate_dbformat(state->zsbuf->format);
1627	assert(format != ~0);
1628
1629	r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1630				offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1631	r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1632				S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1633	if (!rscreen->use_surface_alloc) {
1634		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1635	} else {
1636		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1637					S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1638					S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1639	}
1640	r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1641				S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1642				&rtex->resource, RADEON_USAGE_READWRITE);
1643	r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1644				(surf->aligned_height / 8) - 1);
1645}
1646
1647static void r600_set_framebuffer_state(struct pipe_context *ctx,
1648					const struct pipe_framebuffer_state *state)
1649{
1650	struct r600_context *rctx = (struct r600_context *)ctx;
1651	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1652	uint32_t tl, br, shader_control;
1653
1654	if (rstate == NULL)
1655		return;
1656
1657	r600_flush_framebuffer(rctx, false);
1658
1659	/* unreference old buffer and reference new one */
1660	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1661
1662	util_copy_framebuffer_state(&rctx->framebuffer, state);
1663
1664	/* build states */
1665	rctx->have_depth_fb = 0;
1666	rctx->export_16bpc = true;
1667	rctx->nr_cbufs = state->nr_cbufs;
1668
1669	for (int i = 0; i < state->nr_cbufs; i++) {
1670		r600_cb(rctx, rstate, state, i);
1671	}
1672	if (state->zsbuf) {
1673		r600_db(rctx, rstate, state);
1674	}
1675
1676	shader_control = 0;
1677	for (int i = 0; i < state->nr_cbufs; i++) {
1678		shader_control |= 1 << i;
1679	}
1680	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1681	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1682
1683	r600_pipe_state_add_reg(rstate,
1684				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1685	r600_pipe_state_add_reg(rstate,
1686				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1687
1688	r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1689				shader_control);
1690
1691	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1692	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1693	r600_context_pipe_state_set(rctx, rstate);
1694
1695	if (state->zsbuf) {
1696		r600_polygon_offset_update(rctx);
1697	}
1698
1699	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1700		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1701		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1702	}
1703}
1704
1705static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1706{
1707	struct radeon_winsys_cs *cs = rctx->cs;
1708	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1709	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1710	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1711	unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1712
1713	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1714	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1715	r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1716	r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1717			       a->cb_color_control |
1718			       S_028808_MULTIWRITE_ENABLE(multiwrite));
1719}
1720
1721static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1722{
1723	struct radeon_winsys_cs *cs = rctx->cs;
1724	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1725	unsigned db_render_control = 0;
1726	unsigned db_render_override =
1727		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1728		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1729		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1730
1731	if (a->occlusion_query_enabled) {
1732		if (rctx->chip_class >= R700) {
1733			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1734		}
1735		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1736	}
1737	if (a->flush_depthstencil_enabled) {
1738		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1739				     S_028D0C_STENCIL_COPY_ENABLE(1) |
1740				     S_028D0C_COPY_CENTROID(1);
1741	}
1742
1743	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1744	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1745	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1746}
1747
1748static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1749{
1750	struct radeon_winsys_cs *cs = rctx->cs;
1751	struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1752	unsigned count = rctx->nr_vertex_buffers;
1753	unsigned i, offset;
1754
1755	for (i = 0; i < count; i++) {
1756		struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1757
1758		if (!rbuffer) {
1759			continue;
1760		}
1761
1762		offset = vb[i].buffer_offset;
1763
1764		/* fetch resources start at index 320 */
1765		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1766		r600_write_value(cs, (320 + i) * 7);
1767		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1768		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1769		r600_write_value(cs, /* RESOURCEi_WORD2 */
1770				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1771				 S_038008_STRIDE(vb[i].stride));
1772		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1773		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1774		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1775		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1776
1777		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1778		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1779	}
1780}
1781
1782static void r600_emit_constant_buffers(struct r600_context *rctx,
1783				       struct r600_constbuf_state *state,
1784				       unsigned buffer_id_base,
1785				       unsigned reg_alu_constbuf_size,
1786				       unsigned reg_alu_const_cache)
1787{
1788	struct radeon_winsys_cs *cs = rctx->cs;
1789	uint32_t dirty_mask = state->dirty_mask;
1790
1791	while (dirty_mask) {
1792		struct pipe_constant_buffer *cb;
1793		struct r600_resource *rbuffer;
1794		unsigned offset;
1795		unsigned buffer_index = ffs(dirty_mask) - 1;
1796
1797		cb = &state->cb[buffer_index];
1798		rbuffer = (struct r600_resource*)cb->buffer;
1799		assert(rbuffer);
1800
1801		offset = cb->buffer_offset;
1802
1803		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1804				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1805		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1806
1807		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1808		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1809
1810		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1811		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1812		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1813		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1814		r600_write_value(cs, /* RESOURCEi_WORD2 */
1815				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1816				 S_038008_STRIDE(16));
1817		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1818		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1819		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1820		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1821
1822		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1823		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1824
1825		dirty_mask &= ~(1 << buffer_index);
1826	}
1827	state->dirty_mask = 0;
1828}
1829
1830static void r600_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1831{
1832	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1833				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1834				   R_028980_ALU_CONST_CACHE_VS_0);
1835}
1836
1837static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1838{
1839	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1840				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1841				   R_028940_ALU_CONST_CACHE_PS_0);
1842}
1843
1844void r600_init_state_functions(struct r600_context *rctx)
1845{
1846	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
1847	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1848	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1849	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1850	r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0);
1851	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffer, 0, 0);
1852	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffer, 0, 0);
1853
1854	rctx->context.create_blend_state = r600_create_blend_state;
1855	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1856	rctx->context.create_fs_state = r600_create_shader_state_ps;
1857	rctx->context.create_rasterizer_state = r600_create_rs_state;
1858	rctx->context.create_sampler_state = r600_create_sampler_state;
1859	rctx->context.create_sampler_view = r600_create_sampler_view;
1860	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1861	rctx->context.create_vs_state = r600_create_shader_state_vs;
1862	rctx->context.bind_blend_state = r600_bind_blend_state;
1863	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1864	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1865	rctx->context.bind_fs_state = r600_bind_ps_shader;
1866	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1867	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1868	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1869	rctx->context.bind_vs_state = r600_bind_vs_shader;
1870	rctx->context.delete_blend_state = r600_delete_state;
1871	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1872	rctx->context.delete_fs_state = r600_delete_ps_shader;
1873	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1874	rctx->context.delete_sampler_state = r600_delete_state;
1875	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1876	rctx->context.delete_vs_state = r600_delete_vs_shader;
1877	rctx->context.set_blend_color = r600_set_blend_color;
1878	rctx->context.set_clip_state = r600_set_clip_state;
1879	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1880	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1881	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1882	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1883	rctx->context.set_sample_mask = r600_set_sample_mask;
1884	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1885	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1886	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1887	rctx->context.set_index_buffer = r600_set_index_buffer;
1888	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1889	rctx->context.set_viewport_state = r600_set_viewport_state;
1890	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1891	rctx->context.texture_barrier = r600_texture_barrier;
1892	rctx->context.create_stream_output_target = r600_create_so_target;
1893	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1894	rctx->context.set_stream_output_targets = r600_set_so_targets;
1895}
1896
1897/* Adjust GPR allocation on R6xx/R7xx */
1898void r600_adjust_gprs(struct r600_context *rctx)
1899{
1900	struct r600_pipe_state rstate;
1901	unsigned num_ps_gprs = rctx->default_ps_gprs;
1902	unsigned num_vs_gprs = rctx->default_vs_gprs;
1903	unsigned tmp;
1904	int diff;
1905
1906	/* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1907	 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1908	 * adjusting the GPR allocation?
1909	 * Do we need this if we aren't really changing config below? */
1910	r600_inval_shader_cache(rctx);
1911
1912	if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1913	{
1914		diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1915		num_vs_gprs -= diff;
1916		num_ps_gprs += diff;
1917	}
1918
1919	if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1920	{
1921		diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1922		num_ps_gprs -= diff;
1923		num_vs_gprs += diff;
1924	}
1925
1926	tmp = 0;
1927	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1928	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1929	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1930	rstate.nregs = 0;
1931	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1932
1933	r600_context_pipe_state_set(rctx, &rstate);
1934}
1935
1936void r600_init_atom_start_cs(struct r600_context *rctx)
1937{
1938	int ps_prio;
1939	int vs_prio;
1940	int gs_prio;
1941	int es_prio;
1942	int num_ps_gprs;
1943	int num_vs_gprs;
1944	int num_gs_gprs;
1945	int num_es_gprs;
1946	int num_temp_gprs;
1947	int num_ps_threads;
1948	int num_vs_threads;
1949	int num_gs_threads;
1950	int num_es_threads;
1951	int num_ps_stack_entries;
1952	int num_vs_stack_entries;
1953	int num_gs_stack_entries;
1954	int num_es_stack_entries;
1955	enum radeon_family family;
1956	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1957	uint32_t tmp;
1958	unsigned i;
1959
1960	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1961
1962	/* R6xx requires this packet at the start of each command buffer */
1963	if (rctx->chip_class == R600) {
1964		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1965		r600_store_value(cb, 0);
1966	}
1967	/* All asics require this one */
1968	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1969	r600_store_value(cb, 0x80000000);
1970	r600_store_value(cb, 0x80000000);
1971
1972	family = rctx->family;
1973	ps_prio = 0;
1974	vs_prio = 1;
1975	gs_prio = 2;
1976	es_prio = 3;
1977	switch (family) {
1978	case CHIP_R600:
1979		num_ps_gprs = 192;
1980		num_vs_gprs = 56;
1981		num_temp_gprs = 4;
1982		num_gs_gprs = 0;
1983		num_es_gprs = 0;
1984		num_ps_threads = 136;
1985		num_vs_threads = 48;
1986		num_gs_threads = 4;
1987		num_es_threads = 4;
1988		num_ps_stack_entries = 128;
1989		num_vs_stack_entries = 128;
1990		num_gs_stack_entries = 0;
1991		num_es_stack_entries = 0;
1992		break;
1993	case CHIP_RV630:
1994	case CHIP_RV635:
1995		num_ps_gprs = 84;
1996		num_vs_gprs = 36;
1997		num_temp_gprs = 4;
1998		num_gs_gprs = 0;
1999		num_es_gprs = 0;
2000		num_ps_threads = 144;
2001		num_vs_threads = 40;
2002		num_gs_threads = 4;
2003		num_es_threads = 4;
2004		num_ps_stack_entries = 40;
2005		num_vs_stack_entries = 40;
2006		num_gs_stack_entries = 32;
2007		num_es_stack_entries = 16;
2008		break;
2009	case CHIP_RV610:
2010	case CHIP_RV620:
2011	case CHIP_RS780:
2012	case CHIP_RS880:
2013	default:
2014		num_ps_gprs = 84;
2015		num_vs_gprs = 36;
2016		num_temp_gprs = 4;
2017		num_gs_gprs = 0;
2018		num_es_gprs = 0;
2019		num_ps_threads = 136;
2020		num_vs_threads = 48;
2021		num_gs_threads = 4;
2022		num_es_threads = 4;
2023		num_ps_stack_entries = 40;
2024		num_vs_stack_entries = 40;
2025		num_gs_stack_entries = 32;
2026		num_es_stack_entries = 16;
2027		break;
2028	case CHIP_RV670:
2029		num_ps_gprs = 144;
2030		num_vs_gprs = 40;
2031		num_temp_gprs = 4;
2032		num_gs_gprs = 0;
2033		num_es_gprs = 0;
2034		num_ps_threads = 136;
2035		num_vs_threads = 48;
2036		num_gs_threads = 4;
2037		num_es_threads = 4;
2038		num_ps_stack_entries = 40;
2039		num_vs_stack_entries = 40;
2040		num_gs_stack_entries = 32;
2041		num_es_stack_entries = 16;
2042		break;
2043	case CHIP_RV770:
2044		num_ps_gprs = 192;
2045		num_vs_gprs = 56;
2046		num_temp_gprs = 4;
2047		num_gs_gprs = 0;
2048		num_es_gprs = 0;
2049		num_ps_threads = 188;
2050		num_vs_threads = 60;
2051		num_gs_threads = 0;
2052		num_es_threads = 0;
2053		num_ps_stack_entries = 256;
2054		num_vs_stack_entries = 256;
2055		num_gs_stack_entries = 0;
2056		num_es_stack_entries = 0;
2057		break;
2058	case CHIP_RV730:
2059	case CHIP_RV740:
2060		num_ps_gprs = 84;
2061		num_vs_gprs = 36;
2062		num_temp_gprs = 4;
2063		num_gs_gprs = 0;
2064		num_es_gprs = 0;
2065		num_ps_threads = 188;
2066		num_vs_threads = 60;
2067		num_gs_threads = 0;
2068		num_es_threads = 0;
2069		num_ps_stack_entries = 128;
2070		num_vs_stack_entries = 128;
2071		num_gs_stack_entries = 0;
2072		num_es_stack_entries = 0;
2073		break;
2074	case CHIP_RV710:
2075		num_ps_gprs = 192;
2076		num_vs_gprs = 56;
2077		num_temp_gprs = 4;
2078		num_gs_gprs = 0;
2079		num_es_gprs = 0;
2080		num_ps_threads = 144;
2081		num_vs_threads = 48;
2082		num_gs_threads = 0;
2083		num_es_threads = 0;
2084		num_ps_stack_entries = 128;
2085		num_vs_stack_entries = 128;
2086		num_gs_stack_entries = 0;
2087		num_es_stack_entries = 0;
2088		break;
2089	}
2090
2091	rctx->default_ps_gprs = num_ps_gprs;
2092	rctx->default_vs_gprs = num_vs_gprs;
2093	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2094
2095	/* SQ_CONFIG */
2096	tmp = 0;
2097	switch (family) {
2098	case CHIP_RV610:
2099	case CHIP_RV620:
2100	case CHIP_RS780:
2101	case CHIP_RS880:
2102	case CHIP_RV710:
2103		break;
2104	default:
2105		tmp |= S_008C00_VC_ENABLE(1);
2106		break;
2107	}
2108	tmp |= S_008C00_DX9_CONSTS(0);
2109	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2110	tmp |= S_008C00_PS_PRIO(ps_prio);
2111	tmp |= S_008C00_VS_PRIO(vs_prio);
2112	tmp |= S_008C00_GS_PRIO(gs_prio);
2113	tmp |= S_008C00_ES_PRIO(es_prio);
2114	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2115
2116	/* SQ_GPR_RESOURCE_MGMT_2 */
2117	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2118	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2119	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2120	r600_store_value(cb, tmp);
2121
2122	/* SQ_THREAD_RESOURCE_MGMT */
2123	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2124	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2125	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2126	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2127	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2128
2129	/* SQ_STACK_RESOURCE_MGMT_1 */
2130	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2131	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2132	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2133
2134	/* SQ_STACK_RESOURCE_MGMT_2 */
2135	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2136	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2137	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2138
2139	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2140
2141	if (rctx->chip_class >= R700) {
2142		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2143		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2144		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2145		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2146	} else {
2147		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2148		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2149		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2150		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2151	}
2152	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2153	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2154	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2155	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2156	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2157	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2158	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2159	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2160	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2161	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2162
2163	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2164	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2165	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2166	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2167	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2168	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2169	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2170	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2171	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2172	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2173	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2174	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2175	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2176	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2177
2178	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2179	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2180	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2181
2182	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2183	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2184	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2185	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2186
2187	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2188
2189	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2190	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2191	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2192
2193	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2194
2195	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2196	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2197	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2198
2199	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2200	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2201	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2202	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2203
2204	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2205	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2206	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2207
2208	r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2209
2210	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2211	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2212
2213	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2214	r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2215	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2216
2217	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2218	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2219	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2220	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2221	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2222	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2223	r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2224
2225	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2226	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2227	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2228
2229	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2230
2231	r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2232	for (i = 0; i < 8; i++) {
2233		r600_store_value(cb, 0);
2234	}
2235
2236	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2237	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2238
2239	if (rctx->chip_class >= R700) {
2240		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2241	}
2242
2243	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2244	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2245	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2246	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2247	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2248
2249	r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2250
2251	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2252	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2253	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2254
2255	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2256	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2257	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2258
2259	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2260	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2261	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2262
2263	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2264	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2265
2266	if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2267		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2268	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2269
2270	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2271	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2272}
2273
2274void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2275{
2276	struct r600_context *rctx = (struct r600_context *)ctx;
2277	struct r600_pipe_state *rstate = &shader->rstate;
2278	struct r600_shader *rshader = &shader->shader;
2279	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2280	int pos_index = -1, face_index = -1;
2281	unsigned tmp, sid, ufi = 0;
2282	int need_linear = 0;
2283	unsigned z_export = 0, stencil_export = 0;
2284
2285	rstate->nregs = 0;
2286
2287	for (i = 0; i < rshader->ninput; i++) {
2288		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2289			pos_index = i;
2290		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2291			face_index = i;
2292
2293		sid = rshader->input[i].spi_sid;
2294
2295		tmp = S_028644_SEMANTIC(sid);
2296
2297		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2298			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2299			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2300				rctx->rasterizer && rctx->rasterizer->flatshade))
2301			tmp |= S_028644_FLAT_SHADE(1);
2302
2303		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2304				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2305			tmp |= S_028644_PT_SPRITE_TEX(1);
2306		}
2307
2308		if (rshader->input[i].centroid)
2309			tmp |= S_028644_SEL_CENTROID(1);
2310
2311		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2312			need_linear = 1;
2313			tmp |= S_028644_SEL_LINEAR(1);
2314		}
2315
2316		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2317				tmp);
2318	}
2319
2320	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2321	for (i = 0; i < rshader->noutput; i++) {
2322		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2323			z_export = 1;
2324		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2325			stencil_export = 1;
2326	}
2327	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2328	db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2329	if (rshader->uses_kill)
2330		db_shader_control |= S_02880C_KILL_ENABLE(1);
2331
2332	exports_ps = 0;
2333	for (i = 0; i < rshader->noutput; i++) {
2334		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2335		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2336			exports_ps |= 1;
2337		}
2338	}
2339	num_cout = rshader->nr_ps_color_exports;
2340	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2341	if (!exports_ps) {
2342		/* always at least export 1 component per pixel */
2343		exports_ps = 2;
2344	}
2345
2346	shader->nr_ps_color_outputs = num_cout;
2347
2348	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2349				S_0286CC_PERSP_GRADIENT_ENA(1)|
2350				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2351	spi_input_z = 0;
2352	if (pos_index != -1) {
2353		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2354					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2355					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2356					S_0286CC_BARYC_SAMPLE_CNTL(1));
2357		spi_input_z |= 1;
2358	}
2359
2360	spi_ps_in_control_1 = 0;
2361	if (face_index != -1) {
2362		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2363			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2364	}
2365
2366	/* HW bug in original R600 */
2367	if (rctx->family == CHIP_R600)
2368		ufi = 1;
2369
2370	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2371	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2372	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2373	r600_pipe_state_add_reg_bo(rstate,
2374				   R_028840_SQ_PGM_START_PS,
2375				   0, shader->bo, RADEON_USAGE_READ);
2376	r600_pipe_state_add_reg(rstate,
2377				R_028850_SQ_PGM_RESOURCES_PS,
2378				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2379				S_028850_STACK_SIZE(rshader->bc.nstack) |
2380				S_028850_UNCACHED_FIRST_INST(ufi));
2381	r600_pipe_state_add_reg(rstate,
2382				R_028854_SQ_PGM_EXPORTS_PS,
2383				exports_ps);
2384	/* only set some bits here, the other bits are set in the dsa state */
2385	shader->db_shader_control = db_shader_control;
2386	shader->ps_depth_export = z_export | stencil_export;
2387
2388	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2389	if (rctx->rasterizer)
2390		shader->flatshade = rctx->rasterizer->flatshade;
2391}
2392
2393void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2394{
2395	struct r600_context *rctx = (struct r600_context *)ctx;
2396	struct r600_pipe_state *rstate = &shader->rstate;
2397	struct r600_shader *rshader = &shader->shader;
2398	unsigned spi_vs_out_id[10] = {};
2399	unsigned i, tmp, nparams = 0;
2400
2401	/* clear previous register */
2402	rstate->nregs = 0;
2403
2404	for (i = 0; i < rshader->noutput; i++) {
2405		if (rshader->output[i].spi_sid) {
2406			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2407			spi_vs_out_id[nparams / 4] |= tmp;
2408			nparams++;
2409		}
2410	}
2411
2412	for (i = 0; i < 10; i++) {
2413		r600_pipe_state_add_reg(rstate,
2414					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2415					spi_vs_out_id[i]);
2416	}
2417
2418	/* Certain attributes (position, psize, etc.) don't count as params.
2419	 * VS is required to export at least one param and r600_shader_from_tgsi()
2420	 * takes care of adding a dummy export.
2421	 */
2422	if (nparams < 1)
2423		nparams = 1;
2424
2425	r600_pipe_state_add_reg(rstate,
2426				R_0286C4_SPI_VS_OUT_CONFIG,
2427				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2428	r600_pipe_state_add_reg(rstate,
2429				R_028868_SQ_PGM_RESOURCES_VS,
2430				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2431				S_028868_STACK_SIZE(rshader->bc.nstack));
2432	r600_pipe_state_add_reg_bo(rstate,
2433			R_028858_SQ_PGM_START_VS,
2434			0, shader->bo, RADEON_USAGE_READ);
2435
2436	shader->pa_cl_vs_out_cntl =
2437		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2438		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2439		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2440		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2441}
2442
2443void r600_fetch_shader(struct pipe_context *ctx,
2444		       struct r600_vertex_element *ve)
2445{
2446	struct r600_pipe_state *rstate;
2447	struct r600_context *rctx = (struct r600_context *)ctx;
2448
2449	rstate = &ve->rstate;
2450	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2451	rstate->nregs = 0;
2452	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2453				0,
2454				ve->fetch_shader, RADEON_USAGE_READ);
2455}
2456
2457void *r600_create_db_flush_dsa(struct r600_context *rctx)
2458{
2459	struct pipe_depth_stencil_alpha_state dsa;
2460	struct r600_pipe_state *rstate;
2461	struct r600_pipe_dsa *dsa_state;
2462	boolean quirk = false;
2463
2464	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2465		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2466		quirk = true;
2467
2468	memset(&dsa, 0, sizeof(dsa));
2469
2470	if (quirk) {
2471		dsa.depth.enabled = 1;
2472		dsa.depth.func = PIPE_FUNC_LEQUAL;
2473		dsa.stencil[0].enabled = 1;
2474		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2475		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2476		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2477		dsa.stencil[0].writemask = 0xff;
2478	}
2479
2480	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2481	dsa_state = (struct r600_pipe_dsa*)rstate;
2482	dsa_state->is_flush = true;
2483	return rstate;
2484}
2485
2486void r600_update_dual_export_state(struct r600_context * rctx)
2487{
2488	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2489			       !rctx->ps_shader->current->ps_depth_export;
2490	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2491				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2492
2493	if (db_shader_control != rctx->db_shader_control) {
2494		struct r600_pipe_state rstate;
2495
2496		rctx->db_shader_control = db_shader_control;
2497		rstate.nregs = 0;
2498		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2499		r600_context_pipe_state_set(rctx, &rstate);
2500	}
2501}
2502