r600_state.c revision 6d28bf917fb1d741d90fd3f05c22769376021fca
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include <stdio.h> 27#include "util/u_inlines.h" 28#include "util/u_format.h" 29#include "util/u_memory.h" 30#include "r600_screen.h" 31#include "r600_context.h" 32#include "r600_resource.h" 33#include "r600d.h" 34 35static void *r600_create_blend_state(struct pipe_context *ctx, 36 const struct pipe_blend_state *state) 37{ 38 struct r600_context *rctx = r600_context(ctx); 39 40 return r600_context_state(rctx, pipe_blend_type, state); 41} 42 43static void *r600_create_dsa_state(struct pipe_context *ctx, 44 const struct pipe_depth_stencil_alpha_state *state) 45{ 46 struct r600_context *rctx = r600_context(ctx); 47 48 return r600_context_state(rctx, pipe_dsa_type, state); 49} 50 51static void *r600_create_rs_state(struct pipe_context *ctx, 52 const struct pipe_rasterizer_state *state) 53{ 54 struct r600_context *rctx = r600_context(ctx); 55 56 return r600_context_state(rctx, pipe_rasterizer_type, state); 57} 58 59static void *r600_create_sampler_state(struct pipe_context *ctx, 60 const struct pipe_sampler_state *state) 61{ 62 struct r600_context *rctx = r600_context(ctx); 63 64 return r600_context_state(rctx, pipe_sampler_type, state); 65} 66 67static void r600_sampler_view_destroy(struct pipe_context *ctx, 68 struct pipe_sampler_view *state) 69{ 70 struct r600_context_state *rstate = (struct r600_context_state *)state; 71 72 r600_context_state_decref(rstate); 73} 74 75static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 76 struct pipe_resource *texture, 77 const struct pipe_sampler_view *state) 78{ 79 struct r600_context *rctx = r600_context(ctx); 80 struct r600_context_state *rstate; 81 82 rstate = r600_context_state(rctx, pipe_sampler_type, state); 83 pipe_reference(NULL, &texture->reference); 84 rstate->state.sampler_view.texture = texture; 85 rstate->state.sampler_view.reference.count = 1; 86 rstate->state.sampler_view.context = ctx; 87 return &rstate->state.sampler_view; 88} 89 90static void *r600_create_shader_state(struct pipe_context *ctx, 91 const struct pipe_shader_state *state) 92{ 93 struct r600_context *rctx = r600_context(ctx); 94 95 return r600_context_state(rctx, pipe_shader_type, state); 96} 97 98static void *r600_create_vertex_elements(struct pipe_context *ctx, 99 unsigned count, 100 const struct pipe_vertex_element *elements) 101{ 102 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 103 104 assert(count < 32); 105 v->count = count; 106 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element)); 107 v->refcount = 1; 108 return v; 109} 110 111static void r600_bind_state(struct pipe_context *ctx, void *state) 112{ 113 struct r600_context *rctx = r600_context(ctx); 114 struct r600_context_state *rstate = (struct r600_context_state *)state; 115 116 if (state == NULL) 117 return; 118 switch (rstate->type) { 119 case pipe_rasterizer_type: 120 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer); 121 rctx->rasterizer = r600_context_state_incref(rstate); 122 break; 123 case pipe_poly_stipple_type: 124 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple); 125 rctx->poly_stipple = r600_context_state_incref(rstate); 126 break; 127 case pipe_scissor_type: 128 rctx->scissor = r600_context_state_decref(rctx->scissor); 129 rctx->scissor = r600_context_state_incref(rstate); 130 break; 131 case pipe_clip_type: 132 rctx->clip = r600_context_state_decref(rctx->clip); 133 rctx->clip = r600_context_state_incref(rstate); 134 break; 135 case pipe_depth_type: 136 rctx->depth = r600_context_state_decref(rctx->depth); 137 rctx->depth = r600_context_state_incref(rstate); 138 break; 139 case pipe_stencil_type: 140 rctx->stencil = r600_context_state_decref(rctx->stencil); 141 rctx->stencil = r600_context_state_incref(rstate); 142 break; 143 case pipe_alpha_type: 144 rctx->alpha = r600_context_state_decref(rctx->alpha); 145 rctx->alpha = r600_context_state_incref(rstate); 146 break; 147 case pipe_dsa_type: 148 rctx->dsa = r600_context_state_decref(rctx->dsa); 149 rctx->dsa = r600_context_state_incref(rstate); 150 break; 151 case pipe_blend_type: 152 rctx->blend = r600_context_state_decref(rctx->blend); 153 rctx->blend = r600_context_state_incref(rstate); 154 break; 155 case pipe_framebuffer_type: 156 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer); 157 rctx->framebuffer = r600_context_state_incref(rstate); 158 break; 159 case pipe_stencil_ref_type: 160 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref); 161 rctx->stencil_ref = r600_context_state_incref(rstate); 162 break; 163 case pipe_viewport_type: 164 rctx->viewport = r600_context_state_decref(rctx->viewport); 165 rctx->viewport = r600_context_state_incref(rstate); 166 break; 167 case pipe_shader_type: 168 case pipe_sampler_type: 169 case pipe_sampler_view_type: 170 default: 171 R600_ERR("invalid type %d\n", rstate->type); 172 return; 173 } 174} 175 176static void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 177{ 178 struct r600_context *rctx = r600_context(ctx); 179 struct r600_context_state *rstate = (struct r600_context_state *)state; 180 181 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader); 182 rctx->ps_shader = r600_context_state_incref(rstate); 183} 184 185static void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 186{ 187 struct r600_context *rctx = r600_context(ctx); 188 struct r600_context_state *rstate = (struct r600_context_state *)state; 189 190 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader); 191 rctx->vs_shader = r600_context_state_incref(rstate); 192} 193 194static void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 195{ 196 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 197 198 if (v == NULL) 199 return; 200 if (--v->refcount) 201 return; 202 free(v); 203} 204 205static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 206{ 207 struct r600_context *rctx = r600_context(ctx); 208 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 209 210 r600_delete_vertex_element(ctx, rctx->vertex_elements); 211 rctx->vertex_elements = v; 212 if (v) { 213 v->refcount++; 214 } 215} 216 217static void r600_bind_ps_sampler(struct pipe_context *ctx, 218 unsigned count, void **states) 219{ 220 struct r600_context *rctx = r600_context(ctx); 221 struct r600_context_state *rstate; 222 unsigned i; 223 224 for (i = 0; i < rctx->ps_nsampler; i++) { 225 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]); 226 } 227 for (i = 0; i < count; i++) { 228 rstate = (struct r600_context_state *)states[i]; 229 rctx->ps_sampler[i] = r600_context_state_incref(rstate); 230 } 231 rctx->ps_nsampler = count; 232} 233 234static void r600_bind_vs_sampler(struct pipe_context *ctx, 235 unsigned count, void **states) 236{ 237 struct r600_context *rctx = r600_context(ctx); 238 struct r600_context_state *rstate; 239 unsigned i; 240 241 for (i = 0; i < rctx->vs_nsampler; i++) { 242 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]); 243 } 244 for (i = 0; i < count; i++) { 245 rstate = (struct r600_context_state *)states[i]; 246 rctx->vs_sampler[i] = r600_context_state_incref(rstate); 247 } 248 rctx->vs_nsampler = count; 249} 250 251static void r600_delete_state(struct pipe_context *ctx, void *state) 252{ 253 struct r600_context_state *rstate = (struct r600_context_state *)state; 254 255 r600_context_state_decref(rstate); 256} 257 258static void r600_set_blend_color(struct pipe_context *ctx, 259 const struct pipe_blend_color *color) 260{ 261} 262 263static void r600_set_clip_state(struct pipe_context *ctx, 264 const struct pipe_clip_state *state) 265{ 266} 267 268static void r600_set_constant_buffer(struct pipe_context *ctx, 269 uint shader, uint index, 270 struct pipe_resource *buffer) 271{ 272 struct r600_screen *rscreen = r600_screen(ctx->screen); 273 struct r600_context *rctx = r600_context(ctx); 274 unsigned nconstant = 0, i, type, id; 275 struct radeon_state *rstate; 276 struct pipe_transfer *transfer; 277 u32 *ptr; 278 279 switch (shader) { 280 case PIPE_SHADER_VERTEX: 281 id = R600_VS_CONSTANT; 282 type = R600_VS_CONSTANT_TYPE; 283 break; 284 case PIPE_SHADER_FRAGMENT: 285 id = R600_PS_CONSTANT; 286 type = R600_PS_CONSTANT_TYPE; 287 break; 288 default: 289 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader); 290 return; 291 } 292 if (buffer && buffer->width0 > 0) { 293 nconstant = buffer->width0 / 16; 294 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer); 295 if (ptr == NULL) 296 return; 297 for (i = 0; i < nconstant; i++) { 298 rstate = radeon_state(rscreen->rw, type, id + i); 299 if (rstate == NULL) 300 return; 301 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; 302 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; 303 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; 304 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; 305 if (radeon_state_pm4(rstate)) 306 return; 307 if (radeon_draw_set_new(rctx->draw, rstate)) 308 return; 309 } 310 pipe_buffer_unmap(ctx, buffer, transfer); 311 } 312} 313 314static void r600_set_ps_sampler_view(struct pipe_context *ctx, 315 unsigned count, 316 struct pipe_sampler_view **views) 317{ 318 struct r600_context *rctx = r600_context(ctx); 319 struct r600_context_state *rstate; 320 unsigned i; 321 322 for (i = 0; i < rctx->ps_nsampler_view; i++) { 323 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]); 324 } 325 for (i = 0; i < count; i++) { 326 rstate = (struct r600_context_state *)views[i]; 327 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate); 328 } 329 rctx->ps_nsampler_view = count; 330} 331 332static void r600_set_vs_sampler_view(struct pipe_context *ctx, 333 unsigned count, 334 struct pipe_sampler_view **views) 335{ 336 struct r600_context *rctx = r600_context(ctx); 337 struct r600_context_state *rstate; 338 unsigned i; 339 340 for (i = 0; i < rctx->vs_nsampler_view; i++) { 341 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]); 342 } 343 for (i = 0; i < count; i++) { 344 rstate = (struct r600_context_state *)views[i]; 345 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate); 346 } 347 rctx->vs_nsampler_view = count; 348} 349 350static void r600_set_framebuffer_state(struct pipe_context *ctx, 351 const struct pipe_framebuffer_state *state) 352{ 353 struct r600_context *rctx = r600_context(ctx); 354 struct r600_context_state *rstate; 355 356 rstate = r600_context_state(rctx, pipe_framebuffer_type, state); 357 r600_bind_state(ctx, rstate); 358} 359 360static void r600_set_polygon_stipple(struct pipe_context *ctx, 361 const struct pipe_poly_stipple *state) 362{ 363} 364 365static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 366{ 367} 368 369static void r600_set_scissor_state(struct pipe_context *ctx, 370 const struct pipe_scissor_state *state) 371{ 372 struct r600_context *rctx = r600_context(ctx); 373 struct r600_context_state *rstate; 374 375 rstate = r600_context_state(rctx, pipe_scissor_type, state); 376 r600_bind_state(ctx, rstate); 377} 378 379static void r600_set_stencil_ref(struct pipe_context *ctx, 380 const struct pipe_stencil_ref *state) 381{ 382 struct r600_context *rctx = r600_context(ctx); 383 struct r600_context_state *rstate; 384 385 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state); 386 r600_bind_state(ctx, rstate); 387} 388 389static void r600_set_vertex_buffers(struct pipe_context *ctx, 390 unsigned count, 391 const struct pipe_vertex_buffer *buffers) 392{ 393 struct r600_context *rctx = r600_context(ctx); 394 unsigned i; 395 396 for (i = 0; i < rctx->nvertex_buffer; i++) { 397 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL); 398 } 399 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count); 400 for (i = 0; i < count; i++) { 401 rctx->vertex_buffer[i].buffer = NULL; 402 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer); 403 } 404 rctx->nvertex_buffer = count; 405} 406 407static void r600_set_index_buffer(struct pipe_context *ctx, 408 const struct pipe_index_buffer *ib) 409{ 410 struct r600_context *rctx = r600_context(ctx); 411 412 if (ib) { 413 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 414 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer)); 415 } 416 else { 417 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 418 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer)); 419 } 420 421 /* TODO make this more like a state */ 422} 423 424static void r600_set_viewport_state(struct pipe_context *ctx, 425 const struct pipe_viewport_state *state) 426{ 427 struct r600_context *rctx = r600_context(ctx); 428 struct r600_context_state *rstate; 429 430 rstate = r600_context_state(rctx, pipe_viewport_type, state); 431 r600_bind_state(ctx, rstate); 432} 433 434void r600_init_state_functions(struct r600_context *rctx) 435{ 436 rctx->context.create_blend_state = r600_create_blend_state; 437 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 438 rctx->context.create_fs_state = r600_create_shader_state; 439 rctx->context.create_rasterizer_state = r600_create_rs_state; 440 rctx->context.create_sampler_state = r600_create_sampler_state; 441 rctx->context.create_sampler_view = r600_create_sampler_view; 442 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 443 rctx->context.create_vs_state = r600_create_shader_state; 444 rctx->context.bind_blend_state = r600_bind_state; 445 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state; 446 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler; 447 rctx->context.bind_fs_state = r600_bind_ps_shader; 448 rctx->context.bind_rasterizer_state = r600_bind_state; 449 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 450 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler; 451 rctx->context.bind_vs_state = r600_bind_vs_shader; 452 rctx->context.delete_blend_state = r600_delete_state; 453 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 454 rctx->context.delete_fs_state = r600_delete_state; 455 rctx->context.delete_rasterizer_state = r600_delete_state; 456 rctx->context.delete_sampler_state = r600_delete_state; 457 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 458 rctx->context.delete_vs_state = r600_delete_state; 459 rctx->context.set_blend_color = r600_set_blend_color; 460 rctx->context.set_clip_state = r600_set_clip_state; 461 rctx->context.set_constant_buffer = r600_set_constant_buffer; 462 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view; 463 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 464 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 465 rctx->context.set_sample_mask = r600_set_sample_mask; 466 rctx->context.set_scissor_state = r600_set_scissor_state; 467 rctx->context.set_stencil_ref = r600_set_stencil_ref; 468 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 469 rctx->context.set_index_buffer = r600_set_index_buffer; 470 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view; 471 rctx->context.set_viewport_state = r600_set_viewport_state; 472 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 473} 474 475struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate) 476{ 477 if (rstate == NULL) 478 return NULL; 479 rstate->refcount++; 480 return rstate; 481} 482 483struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate) 484{ 485 unsigned i; 486 487 if (rstate == NULL) 488 return NULL; 489 if (--rstate->refcount) 490 return NULL; 491 switch (rstate->type) { 492 case pipe_sampler_view_type: 493 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL); 494 break; 495 case pipe_framebuffer_type: 496 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { 497 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL); 498 } 499 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL); 500 break; 501 case pipe_viewport_type: 502 case pipe_depth_type: 503 case pipe_rasterizer_type: 504 case pipe_poly_stipple_type: 505 case pipe_scissor_type: 506 case pipe_clip_type: 507 case pipe_stencil_type: 508 case pipe_alpha_type: 509 case pipe_dsa_type: 510 case pipe_blend_type: 511 case pipe_stencil_ref_type: 512 case pipe_shader_type: 513 case pipe_sampler_type: 514 break; 515 default: 516 R600_ERR("invalid type %d\n", rstate->type); 517 return NULL; 518 } 519 radeon_state_decref(rstate->rstate); 520 FREE(rstate); 521 return NULL; 522} 523 524struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state) 525{ 526 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state); 527 const union pipe_states *states = state; 528 unsigned i; 529 int r; 530 531 if (rstate == NULL) 532 return NULL; 533 rstate->type = type; 534 rstate->refcount = 1; 535 536 switch (rstate->type) { 537 case pipe_sampler_view_type: 538 rstate->state.sampler_view = (*states).sampler_view; 539 rstate->state.sampler_view.texture = NULL; 540 break; 541 case pipe_framebuffer_type: 542 rstate->state.framebuffer = (*states).framebuffer; 543 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { 544 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], 545 (*states).framebuffer.cbufs[i]); 546 } 547 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, 548 (*states).framebuffer.zsbuf); 549 break; 550 case pipe_viewport_type: 551 rstate->state.viewport = (*states).viewport; 552 break; 553 case pipe_depth_type: 554 rstate->state.depth = (*states).depth; 555 break; 556 case pipe_rasterizer_type: 557 rstate->state.rasterizer = (*states).rasterizer; 558 break; 559 case pipe_poly_stipple_type: 560 rstate->state.poly_stipple = (*states).poly_stipple; 561 break; 562 case pipe_scissor_type: 563 rstate->state.scissor = (*states).scissor; 564 break; 565 case pipe_clip_type: 566 rstate->state.clip = (*states).clip; 567 break; 568 case pipe_stencil_type: 569 rstate->state.stencil = (*states).stencil; 570 break; 571 case pipe_alpha_type: 572 rstate->state.alpha = (*states).alpha; 573 break; 574 case pipe_dsa_type: 575 rstate->state.dsa = (*states).dsa; 576 break; 577 case pipe_blend_type: 578 rstate->state.blend = (*states).blend; 579 break; 580 case pipe_stencil_ref_type: 581 rstate->state.stencil_ref = (*states).stencil_ref; 582 break; 583 case pipe_shader_type: 584 rstate->state.shader = (*states).shader; 585 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens); 586 if (r) { 587 r600_context_state_decref(rstate); 588 return NULL; 589 } 590 break; 591 case pipe_sampler_type: 592 rstate->state.sampler = (*states).sampler; 593 break; 594 default: 595 R600_ERR("invalid type %d\n", rstate->type); 596 FREE(rstate); 597 return NULL; 598 } 599 return rstate; 600} 601 602static struct radeon_state *r600_blend(struct r600_context *rctx) 603{ 604 struct r600_screen *rscreen = rctx->screen; 605 struct radeon_state *rstate; 606 607 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND); 608 if (rstate == NULL) 609 return NULL; 610 rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000; 611 rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000; 612 rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000; 613 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000; 614 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001; 615 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; 616 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; 617 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; 618 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; 619 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; 620 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; 621 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; 622 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; 623 if (radeon_state_pm4(rstate)) { 624 radeon_state_decref(rstate); 625 return NULL; 626 } 627 return rstate; 628} 629 630static struct radeon_state *r600_cb0(struct r600_context *rctx) 631{ 632 struct r600_screen *rscreen = rctx->screen; 633 struct r600_resource_texture *rtex; 634 struct r600_resource *rbuffer; 635 struct radeon_state *rstate; 636 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer; 637 unsigned level = state->cbufs[0]->level; 638 unsigned pitch, slice; 639 640 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0); 641 if (rstate == NULL) 642 return NULL; 643 rtex = (struct r600_resource_texture*)state->cbufs[0]->texture; 644 rbuffer = &rtex->resource; 645 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 646 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 647 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 648 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 649 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 650 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; 651 rstate->nbo = 3; 652 pitch = rtex->pitch[level] / 8 - 1; 653 slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1; 654 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000; 655 rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068; 656 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | 657 S_028060_SLICE_TILE_MAX(slice); 658 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; 659 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; 660 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; 661 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; 662 if (radeon_state_pm4(rstate)) { 663 radeon_state_decref(rstate); 664 return NULL; 665 } 666 return rstate; 667} 668 669static struct radeon_state *r600_db(struct r600_context *rctx) 670{ 671 struct r600_screen *rscreen = rctx->screen; 672 struct r600_resource_texture *rtex; 673 struct r600_resource *rbuffer; 674 struct radeon_state *rstate; 675 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer; 676 unsigned level = state->cbufs[0]->level; 677 unsigned pitch, slice; 678 679 if (state->zsbuf == NULL) 680 return NULL; 681 682 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB); 683 if (rstate == NULL) 684 return NULL; 685 686 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 687 rbuffer = &rtex->resource; 688 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 689 rstate->nbo = 1; 690 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; 691 level = state->zsbuf->level; 692 pitch = rtex->pitch[level] / 8 - 1; 693 slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1; 694 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000; 695 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010006; 696 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000; 697 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1; 698 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | 699 S_028000_SLICE_TILE_MAX(slice); 700 if (radeon_state_pm4(rstate)) { 701 radeon_state_decref(rstate); 702 return NULL; 703 } 704 return rstate; 705} 706 707static struct radeon_state *r600_rasterizer(struct r600_context *rctx) 708{ 709 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer; 710 struct r600_screen *rscreen = rctx->screen; 711 struct radeon_state *rstate; 712 713 rctx->flat_shade = state->flatshade; 714 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); 715 if (rstate == NULL) 716 return NULL; 717 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; 718 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000; 719 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000; 720 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000; 721 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; 722 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008; 723 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000; 724 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; 725 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; 726 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; 727 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; 728 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; 729 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; 730 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; 731 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; 732 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000; 733 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; 734 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000; 735 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000; 736 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000; 737 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000; 738 if (radeon_state_pm4(rstate)) { 739 radeon_state_decref(rstate); 740 return NULL; 741 } 742 return rstate; 743} 744 745static struct radeon_state *r600_scissor(struct r600_context *rctx) 746{ 747 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor; 748 struct r600_screen *rscreen = rctx->screen; 749 struct radeon_state *rstate; 750 u32 tl, br; 751 752 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 753 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 754 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); 755 if (rstate == NULL) 756 return NULL; 757 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; 758 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; 759 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; 760 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; 761 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; 762 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; 763 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; 764 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; 765 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; 766 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; 767 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; 768 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; 769 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; 770 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; 771 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; 772 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; 773 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; 774 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; 775 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; 776 if (radeon_state_pm4(rstate)) { 777 radeon_state_decref(rstate); 778 return NULL; 779 } 780 return rstate; 781} 782 783static struct radeon_state *r600_viewport(struct r600_context *rctx) 784{ 785 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport; 786 struct r600_screen *rscreen = rctx->screen; 787 struct radeon_state *rstate; 788 789 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); 790 if (rstate == NULL) 791 return NULL; 792 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; 793 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; 794 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); 795 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); 796 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); 797 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); 798 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); 799 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); 800 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; 801 if (radeon_state_pm4(rstate)) { 802 radeon_state_decref(rstate); 803 return NULL; 804 } 805 return rstate; 806} 807 808static struct radeon_state *r600_dsa(struct r600_context *rctx) 809{ 810 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; 811 struct r600_screen *rscreen = rctx->screen; 812 struct radeon_state *rstate; 813 unsigned db_depth_control; 814 815 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA); 816 if (rstate == NULL) 817 return NULL; 818 db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); 819 820 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; 821 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; 822 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000; 823 rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00; 824 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00; 825 rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000; 826 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; 827 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; 828 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; 829 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control; 830 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; 831 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; 832 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; 833 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; 834 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; 835 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; 836 if (radeon_state_pm4(rstate)) { 837 radeon_state_decref(rstate); 838 return NULL; 839 } 840 return rstate; 841} 842 843static inline unsigned r600_tex_wrap(unsigned wrap) 844{ 845 switch (wrap) { 846 default: 847 case PIPE_TEX_WRAP_REPEAT: 848 return V_03C000_SQ_TEX_WRAP; 849 case PIPE_TEX_WRAP_CLAMP: 850 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; 851 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 852 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; 853 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 854 return V_03C000_SQ_TEX_CLAMP_BORDER; 855 case PIPE_TEX_WRAP_MIRROR_REPEAT: 856 return V_03C000_SQ_TEX_MIRROR; 857 case PIPE_TEX_WRAP_MIRROR_CLAMP: 858 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 859 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 860 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 861 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 862 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; 863 } 864} 865 866static inline unsigned r600_tex_filter(unsigned filter) 867{ 868 switch (filter) { 869 default: 870 case PIPE_TEX_FILTER_NEAREST: 871 return V_03C000_SQ_TEX_XY_FILTER_POINT; 872 case PIPE_TEX_FILTER_LINEAR: 873 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 874 } 875} 876 877static inline unsigned r600_tex_mipfilter(unsigned filter) 878{ 879 switch (filter) { 880 case PIPE_TEX_MIPFILTER_NEAREST: 881 return V_03C000_SQ_TEX_Z_FILTER_POINT; 882 case PIPE_TEX_MIPFILTER_LINEAR: 883 return V_03C000_SQ_TEX_Z_FILTER_LINEAR; 884 default: 885 case PIPE_TEX_MIPFILTER_NONE: 886 return V_03C000_SQ_TEX_Z_FILTER_NONE; 887 } 888} 889 890static inline unsigned r600_tex_compare(unsigned compare) 891{ 892 switch (compare) { 893 default: 894 case PIPE_FUNC_NEVER: 895 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; 896 case PIPE_FUNC_LESS: 897 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; 898 case PIPE_FUNC_EQUAL: 899 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; 900 case PIPE_FUNC_LEQUAL: 901 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 902 case PIPE_FUNC_GREATER: 903 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; 904 case PIPE_FUNC_NOTEQUAL: 905 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 906 case PIPE_FUNC_GEQUAL: 907 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 908 case PIPE_FUNC_ALWAYS: 909 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; 910 } 911} 912 913static struct radeon_state *r600_sampler(struct r600_context *rctx, 914 const struct pipe_sampler_state *state, 915 unsigned id) 916{ 917 struct r600_screen *rscreen = rctx->screen; 918 struct radeon_state *rstate; 919 920 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id); 921 if (rstate == NULL) 922 return NULL; 923 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = 924 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 925 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 926 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 927 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | 928 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | 929 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 930 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)); 931 /* FIXME LOD it depends on texture base level ... */ 932 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] = 933 S_03C004_MIN_LOD(0) | 934 S_03C004_MAX_LOD(0) | 935 S_03C004_LOD_BIAS(0); 936 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1); 937 if (radeon_state_pm4(rstate)) { 938 radeon_state_decref(rstate); 939 return NULL; 940 } 941 return rstate; 942} 943 944static inline unsigned r600_tex_swizzle(unsigned swizzle) 945{ 946 switch (swizzle) { 947 case PIPE_SWIZZLE_RED: 948 return V_038010_SQ_SEL_X; 949 case PIPE_SWIZZLE_GREEN: 950 return V_038010_SQ_SEL_Y; 951 case PIPE_SWIZZLE_BLUE: 952 return V_038010_SQ_SEL_Z; 953 case PIPE_SWIZZLE_ALPHA: 954 return V_038010_SQ_SEL_W; 955 case PIPE_SWIZZLE_ZERO: 956 return V_038010_SQ_SEL_0; 957 default: 958 case PIPE_SWIZZLE_ONE: 959 return V_038010_SQ_SEL_1; 960 } 961} 962 963static inline unsigned r600_format_type(unsigned format_type) 964{ 965 switch (format_type) { 966 default: 967 case UTIL_FORMAT_TYPE_UNSIGNED: 968 return V_038010_SQ_FORMAT_COMP_UNSIGNED; 969 case UTIL_FORMAT_TYPE_SIGNED: 970 return V_038010_SQ_FORMAT_COMP_SIGNED; 971 case UTIL_FORMAT_TYPE_FIXED: 972 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED; 973 } 974} 975 976static inline unsigned r600_tex_dim(unsigned dim) 977{ 978 switch (dim) { 979 default: 980 case PIPE_TEXTURE_1D: 981 return V_038000_SQ_TEX_DIM_1D; 982 case PIPE_TEXTURE_2D: 983 return V_038000_SQ_TEX_DIM_2D; 984 case PIPE_TEXTURE_3D: 985 return V_038000_SQ_TEX_DIM_3D; 986 case PIPE_TEXTURE_CUBE: 987 return V_038000_SQ_TEX_DIM_CUBEMAP; 988 } 989} 990 991static struct radeon_state *r600_resource(struct r600_context *rctx, 992 const struct pipe_sampler_view *view, 993 unsigned id) 994{ 995 struct r600_screen *rscreen = rctx->screen; 996 const struct util_format_description *desc; 997 struct r600_resource_texture *tmp; 998 struct r600_resource *rbuffer; 999 struct radeon_state *rstate; 1000 unsigned format; 1001 1002 if (r600_conv_pipe_format(view->texture->format, &format)) 1003 return NULL; 1004 desc = util_format_description(view->texture->format); 1005 assert(desc == NULL); 1006 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id); 1007 if (rstate == NULL) { 1008 return NULL; 1009 } 1010 tmp = (struct r600_resource_texture*)view->texture; 1011 rbuffer = &tmp->resource; 1012 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 1013 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 1014 rstate->nbo = 2; 1015 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 1016 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; 1017 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 1018 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; 1019 1020 /* FIXME properly handle first level != 0 */ 1021 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = 1022 S_038000_DIM(r600_tex_dim(view->texture->target)) | 1023 S_038000_PITCH((tmp->pitch[0] / 8) - 1) | 1024 S_038000_TEX_WIDTH(view->texture->width0 - 1); 1025 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = 1026 S_038004_TEX_HEIGHT(view->texture->height0 - 1) | 1027 S_038004_TEX_DEPTH(view->texture->depth0 - 1) | 1028 S_038004_DATA_FORMAT(format); 1029 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0; 1030 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; 1031 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 1032 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1033 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1034 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1035 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1036 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | 1037 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | 1038 S_038010_REQUEST_SIZE(1) | 1039 S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_r)) | 1040 S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) | 1041 S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) | 1042 S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) | 1043 S_038010_BASE_LEVEL(view->first_level); 1044 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 1045 S_038014_LAST_LEVEL(view->last_level) | 1046 S_038014_BASE_ARRAY(0) | 1047 S_038014_LAST_ARRAY(0); 1048 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 1049 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE); 1050 if (radeon_state_pm4(rstate)) { 1051 radeon_state_decref(rstate); 1052 return NULL; 1053 } 1054 return rstate; 1055} 1056 1057int r600_context_hw_states(struct r600_context *rctx) 1058{ 1059 unsigned i; 1060 int r; 1061 1062 /* free previous TODO determine what need to be updated, what 1063 * doesn't 1064 */ 1065 //radeon_state_decref(rctx->hw_states.config); 1066 //radeon_state_decref(rctx->hw_states.cb_cntl); 1067 radeon_state_decref(rctx->hw_states.db); 1068 radeon_state_decref(rctx->hw_states.rasterizer); 1069 radeon_state_decref(rctx->hw_states.scissor); 1070 radeon_state_decref(rctx->hw_states.dsa); 1071 radeon_state_decref(rctx->hw_states.blend); 1072 radeon_state_decref(rctx->hw_states.viewport); 1073 radeon_state_decref(rctx->hw_states.cb0); 1074 for (i = 0; i < rctx->hw_states.ps_nresource; i++) { 1075 radeon_state_decref(rctx->hw_states.ps_resource[i]); 1076 rctx->hw_states.ps_resource[i] = NULL; 1077 } 1078 rctx->hw_states.ps_nresource = 0; 1079 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) { 1080 radeon_state_decref(rctx->hw_states.ps_sampler[i]); 1081 rctx->hw_states.ps_sampler[i] = NULL; 1082 } 1083 rctx->hw_states.ps_nsampler = 0; 1084 1085 /* build new states */ 1086 rctx->hw_states.rasterizer = r600_rasterizer(rctx); 1087 rctx->hw_states.scissor = r600_scissor(rctx); 1088 rctx->hw_states.dsa = r600_dsa(rctx); 1089 rctx->hw_states.blend = r600_blend(rctx); 1090 rctx->hw_states.viewport = r600_viewport(rctx); 1091 rctx->hw_states.cb0 = r600_cb0(rctx); 1092 rctx->hw_states.db = r600_db(rctx); 1093 for (i = 0; i < rctx->ps_nsampler; i++) { 1094 if (rctx->ps_sampler[i]) { 1095 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx, 1096 &rctx->ps_sampler[i]->state.sampler, 1097 R600_PS_SAMPLER + i); 1098 } 1099 } 1100 rctx->hw_states.ps_nsampler = rctx->ps_nsampler; 1101 for (i = 0; i < rctx->ps_nsampler_view; i++) { 1102 if (rctx->ps_sampler_view[i]) { 1103 rctx->hw_states.ps_resource[i] = r600_resource(rctx, 1104 &rctx->ps_sampler_view[i]->state.sampler_view, 1105 R600_PS_RESOURCE + i); 1106 } 1107 } 1108 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view; 1109 1110 /* bind states */ 1111 r = radeon_draw_set(rctx->draw, rctx->hw_states.db); 1112 if (r) 1113 return r; 1114 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer); 1115 if (r) 1116 return r; 1117 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor); 1118 if (r) 1119 return r; 1120 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa); 1121 if (r) 1122 return r; 1123 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend); 1124 if (r) 1125 return r; 1126 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport); 1127 if (r) 1128 return r; 1129 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0); 1130 if (r) 1131 return r; 1132 r = radeon_draw_set(rctx->draw, rctx->hw_states.config); 1133 if (r) 1134 return r; 1135 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl); 1136 if (r) 1137 return r; 1138 for (i = 0; i < rctx->hw_states.ps_nresource; i++) { 1139 if (rctx->hw_states.ps_resource[i]) { 1140 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]); 1141 if (r) 1142 return r; 1143 } 1144 } 1145 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) { 1146 if (rctx->hw_states.ps_sampler[i]) { 1147 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]); 1148 if (r) 1149 return r; 1150 } 1151 } 1152 return 0; 1153} 1154