r600_state.c revision c76462b45f1e3a0aa2ee7971191e30e8a5f52015
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600d.h" 25 26#include "pipe/p_shader_tokens.h" 27#include "util/u_pack_color.h" 28#include "util/u_memory.h" 29#include "util/u_framebuffer.h" 30 31static uint32_t r600_translate_blend_function(int blend_func) 32{ 33 switch (blend_func) { 34 case PIPE_BLEND_ADD: 35 return V_028804_COMB_DST_PLUS_SRC; 36 case PIPE_BLEND_SUBTRACT: 37 return V_028804_COMB_SRC_MINUS_DST; 38 case PIPE_BLEND_REVERSE_SUBTRACT: 39 return V_028804_COMB_DST_MINUS_SRC; 40 case PIPE_BLEND_MIN: 41 return V_028804_COMB_MIN_DST_SRC; 42 case PIPE_BLEND_MAX: 43 return V_028804_COMB_MAX_DST_SRC; 44 default: 45 R600_ERR("Unknown blend function %d\n", blend_func); 46 assert(0); 47 break; 48 } 49 return 0; 50} 51 52static uint32_t r600_translate_blend_factor(int blend_fact) 53{ 54 switch (blend_fact) { 55 case PIPE_BLENDFACTOR_ONE: 56 return V_028804_BLEND_ONE; 57 case PIPE_BLENDFACTOR_SRC_COLOR: 58 return V_028804_BLEND_SRC_COLOR; 59 case PIPE_BLENDFACTOR_SRC_ALPHA: 60 return V_028804_BLEND_SRC_ALPHA; 61 case PIPE_BLENDFACTOR_DST_ALPHA: 62 return V_028804_BLEND_DST_ALPHA; 63 case PIPE_BLENDFACTOR_DST_COLOR: 64 return V_028804_BLEND_DST_COLOR; 65 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 66 return V_028804_BLEND_SRC_ALPHA_SATURATE; 67 case PIPE_BLENDFACTOR_CONST_COLOR: 68 return V_028804_BLEND_CONST_COLOR; 69 case PIPE_BLENDFACTOR_CONST_ALPHA: 70 return V_028804_BLEND_CONST_ALPHA; 71 case PIPE_BLENDFACTOR_ZERO: 72 return V_028804_BLEND_ZERO; 73 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 74 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 75 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 76 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 77 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 78 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 79 case PIPE_BLENDFACTOR_INV_DST_COLOR: 80 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 81 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 82 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 83 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 84 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 85 case PIPE_BLENDFACTOR_SRC1_COLOR: 86 return V_028804_BLEND_SRC1_COLOR; 87 case PIPE_BLENDFACTOR_SRC1_ALPHA: 88 return V_028804_BLEND_SRC1_ALPHA; 89 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 90 return V_028804_BLEND_INV_SRC1_COLOR; 91 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 92 return V_028804_BLEND_INV_SRC1_ALPHA; 93 default: 94 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 95 assert(0); 96 break; 97 } 98 return 0; 99} 100 101static unsigned r600_tex_dim(unsigned dim) 102{ 103 switch (dim) { 104 default: 105 case PIPE_TEXTURE_1D: 106 return V_038000_SQ_TEX_DIM_1D; 107 case PIPE_TEXTURE_1D_ARRAY: 108 return V_038000_SQ_TEX_DIM_1D_ARRAY; 109 case PIPE_TEXTURE_2D: 110 case PIPE_TEXTURE_RECT: 111 return V_038000_SQ_TEX_DIM_2D; 112 case PIPE_TEXTURE_2D_ARRAY: 113 return V_038000_SQ_TEX_DIM_2D_ARRAY; 114 case PIPE_TEXTURE_3D: 115 return V_038000_SQ_TEX_DIM_3D; 116 case PIPE_TEXTURE_CUBE: 117 return V_038000_SQ_TEX_DIM_CUBEMAP; 118 } 119} 120 121static uint32_t r600_translate_dbformat(enum pipe_format format) 122{ 123 switch (format) { 124 case PIPE_FORMAT_Z16_UNORM: 125 return V_028010_DEPTH_16; 126 case PIPE_FORMAT_Z24X8_UNORM: 127 return V_028010_DEPTH_X8_24; 128 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 129 return V_028010_DEPTH_8_24; 130 case PIPE_FORMAT_Z32_FLOAT: 131 return V_028010_DEPTH_32_FLOAT; 132 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 133 return V_028010_DEPTH_X24_8_32_FLOAT; 134 default: 135 return ~0U; 136 } 137} 138 139static uint32_t r600_translate_colorswap(enum pipe_format format) 140{ 141 switch (format) { 142 /* 8-bit buffers. */ 143 case PIPE_FORMAT_A8_UNORM: 144 case PIPE_FORMAT_A8_SNORM: 145 case PIPE_FORMAT_A8_UINT: 146 case PIPE_FORMAT_A8_SINT: 147 case PIPE_FORMAT_A16_UNORM: 148 case PIPE_FORMAT_A16_SNORM: 149 case PIPE_FORMAT_A16_UINT: 150 case PIPE_FORMAT_A16_SINT: 151 case PIPE_FORMAT_A16_FLOAT: 152 case PIPE_FORMAT_A32_UINT: 153 case PIPE_FORMAT_A32_SINT: 154 case PIPE_FORMAT_A32_FLOAT: 155 case PIPE_FORMAT_R4A4_UNORM: 156 return V_0280A0_SWAP_ALT_REV; 157 case PIPE_FORMAT_I8_UNORM: 158 case PIPE_FORMAT_I8_SNORM: 159 case PIPE_FORMAT_I8_UINT: 160 case PIPE_FORMAT_I8_SINT: 161 case PIPE_FORMAT_L8_UNORM: 162 case PIPE_FORMAT_L8_SNORM: 163 case PIPE_FORMAT_L8_UINT: 164 case PIPE_FORMAT_L8_SINT: 165 case PIPE_FORMAT_L8_SRGB: 166 case PIPE_FORMAT_L16_UNORM: 167 case PIPE_FORMAT_L16_SNORM: 168 case PIPE_FORMAT_L16_UINT: 169 case PIPE_FORMAT_L16_SINT: 170 case PIPE_FORMAT_L16_FLOAT: 171 case PIPE_FORMAT_L32_UINT: 172 case PIPE_FORMAT_L32_SINT: 173 case PIPE_FORMAT_L32_FLOAT: 174 case PIPE_FORMAT_I16_UNORM: 175 case PIPE_FORMAT_I16_SNORM: 176 case PIPE_FORMAT_I16_UINT: 177 case PIPE_FORMAT_I16_SINT: 178 case PIPE_FORMAT_I16_FLOAT: 179 case PIPE_FORMAT_I32_UINT: 180 case PIPE_FORMAT_I32_SINT: 181 case PIPE_FORMAT_I32_FLOAT: 182 case PIPE_FORMAT_R8_UNORM: 183 case PIPE_FORMAT_R8_SNORM: 184 case PIPE_FORMAT_R8_UINT: 185 case PIPE_FORMAT_R8_SINT: 186 return V_0280A0_SWAP_STD; 187 188 case PIPE_FORMAT_L4A4_UNORM: 189 case PIPE_FORMAT_A4R4_UNORM: 190 return V_0280A0_SWAP_ALT; 191 192 /* 16-bit buffers. */ 193 case PIPE_FORMAT_B5G6R5_UNORM: 194 return V_0280A0_SWAP_STD_REV; 195 196 case PIPE_FORMAT_B5G5R5A1_UNORM: 197 case PIPE_FORMAT_B5G5R5X1_UNORM: 198 return V_0280A0_SWAP_ALT; 199 200 case PIPE_FORMAT_B4G4R4A4_UNORM: 201 case PIPE_FORMAT_B4G4R4X4_UNORM: 202 return V_0280A0_SWAP_ALT; 203 204 case PIPE_FORMAT_Z16_UNORM: 205 return V_0280A0_SWAP_STD; 206 207 case PIPE_FORMAT_L8A8_UNORM: 208 case PIPE_FORMAT_L8A8_SNORM: 209 case PIPE_FORMAT_L8A8_UINT: 210 case PIPE_FORMAT_L8A8_SINT: 211 case PIPE_FORMAT_L8A8_SRGB: 212 case PIPE_FORMAT_L16A16_UNORM: 213 case PIPE_FORMAT_L16A16_SNORM: 214 case PIPE_FORMAT_L16A16_UINT: 215 case PIPE_FORMAT_L16A16_SINT: 216 case PIPE_FORMAT_L16A16_FLOAT: 217 case PIPE_FORMAT_L32A32_UINT: 218 case PIPE_FORMAT_L32A32_SINT: 219 case PIPE_FORMAT_L32A32_FLOAT: 220 return V_0280A0_SWAP_ALT; 221 case PIPE_FORMAT_R8G8_UNORM: 222 case PIPE_FORMAT_R8G8_SNORM: 223 case PIPE_FORMAT_R8G8_UINT: 224 case PIPE_FORMAT_R8G8_SINT: 225 return V_0280A0_SWAP_STD; 226 227 case PIPE_FORMAT_R16_UNORM: 228 case PIPE_FORMAT_R16_SNORM: 229 case PIPE_FORMAT_R16_UINT: 230 case PIPE_FORMAT_R16_SINT: 231 case PIPE_FORMAT_R16_FLOAT: 232 return V_0280A0_SWAP_STD; 233 234 /* 32-bit buffers. */ 235 236 case PIPE_FORMAT_A8B8G8R8_SRGB: 237 return V_0280A0_SWAP_STD_REV; 238 case PIPE_FORMAT_B8G8R8A8_SRGB: 239 return V_0280A0_SWAP_ALT; 240 241 case PIPE_FORMAT_B8G8R8A8_UNORM: 242 case PIPE_FORMAT_B8G8R8X8_UNORM: 243 return V_0280A0_SWAP_ALT; 244 245 case PIPE_FORMAT_A8R8G8B8_UNORM: 246 case PIPE_FORMAT_X8R8G8B8_UNORM: 247 return V_0280A0_SWAP_ALT_REV; 248 case PIPE_FORMAT_R8G8B8A8_SNORM: 249 case PIPE_FORMAT_R8G8B8A8_UNORM: 250 case PIPE_FORMAT_R8G8B8X8_UNORM: 251 case PIPE_FORMAT_R8G8B8A8_SINT: 252 case PIPE_FORMAT_R8G8B8A8_UINT: 253 return V_0280A0_SWAP_STD; 254 255 case PIPE_FORMAT_A8B8G8R8_UNORM: 256 case PIPE_FORMAT_X8B8G8R8_UNORM: 257 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 258 return V_0280A0_SWAP_STD_REV; 259 260 case PIPE_FORMAT_Z24X8_UNORM: 261 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 262 return V_0280A0_SWAP_STD; 263 264 case PIPE_FORMAT_X8Z24_UNORM: 265 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 266 return V_0280A0_SWAP_STD; 267 268 case PIPE_FORMAT_R10G10B10A2_UNORM: 269 case PIPE_FORMAT_R10G10B10X2_SNORM: 270 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 271 return V_0280A0_SWAP_STD; 272 273 case PIPE_FORMAT_B10G10R10A2_UNORM: 274 case PIPE_FORMAT_B10G10R10A2_UINT: 275 return V_0280A0_SWAP_ALT; 276 277 case PIPE_FORMAT_R11G11B10_FLOAT: 278 case PIPE_FORMAT_R16G16_UNORM: 279 case PIPE_FORMAT_R16G16_SNORM: 280 case PIPE_FORMAT_R16G16_FLOAT: 281 case PIPE_FORMAT_R16G16_UINT: 282 case PIPE_FORMAT_R16G16_SINT: 283 case PIPE_FORMAT_R32_UINT: 284 case PIPE_FORMAT_R32_SINT: 285 case PIPE_FORMAT_R32_FLOAT: 286 case PIPE_FORMAT_Z32_FLOAT: 287 return V_0280A0_SWAP_STD; 288 289 /* 64-bit buffers. */ 290 case PIPE_FORMAT_R32G32_FLOAT: 291 case PIPE_FORMAT_R32G32_UINT: 292 case PIPE_FORMAT_R32G32_SINT: 293 case PIPE_FORMAT_R16G16B16A16_UNORM: 294 case PIPE_FORMAT_R16G16B16A16_SNORM: 295 case PIPE_FORMAT_R16G16B16A16_UINT: 296 case PIPE_FORMAT_R16G16B16A16_SINT: 297 case PIPE_FORMAT_R16G16B16A16_FLOAT: 298 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 299 300 /* 128-bit buffers. */ 301 case PIPE_FORMAT_R32G32B32A32_FLOAT: 302 case PIPE_FORMAT_R32G32B32A32_SNORM: 303 case PIPE_FORMAT_R32G32B32A32_UNORM: 304 case PIPE_FORMAT_R32G32B32A32_SINT: 305 case PIPE_FORMAT_R32G32B32A32_UINT: 306 return V_0280A0_SWAP_STD; 307 default: 308 R600_ERR("unsupported colorswap format %d\n", format); 309 return ~0U; 310 } 311 return ~0U; 312} 313 314static uint32_t r600_translate_colorformat(enum pipe_format format) 315{ 316 switch (format) { 317 case PIPE_FORMAT_L4A4_UNORM: 318 case PIPE_FORMAT_R4A4_UNORM: 319 case PIPE_FORMAT_A4R4_UNORM: 320 return V_0280A0_COLOR_4_4; 321 322 /* 8-bit buffers. */ 323 case PIPE_FORMAT_A8_UNORM: 324 case PIPE_FORMAT_A8_SNORM: 325 case PIPE_FORMAT_A8_UINT: 326 case PIPE_FORMAT_A8_SINT: 327 case PIPE_FORMAT_I8_UNORM: 328 case PIPE_FORMAT_I8_SNORM: 329 case PIPE_FORMAT_I8_UINT: 330 case PIPE_FORMAT_I8_SINT: 331 case PIPE_FORMAT_L8_UNORM: 332 case PIPE_FORMAT_L8_SNORM: 333 case PIPE_FORMAT_L8_UINT: 334 case PIPE_FORMAT_L8_SINT: 335 case PIPE_FORMAT_L8_SRGB: 336 case PIPE_FORMAT_R8_UNORM: 337 case PIPE_FORMAT_R8_SNORM: 338 case PIPE_FORMAT_R8_UINT: 339 case PIPE_FORMAT_R8_SINT: 340 return V_0280A0_COLOR_8; 341 342 /* 16-bit buffers. */ 343 case PIPE_FORMAT_B5G6R5_UNORM: 344 return V_0280A0_COLOR_5_6_5; 345 346 case PIPE_FORMAT_B5G5R5A1_UNORM: 347 case PIPE_FORMAT_B5G5R5X1_UNORM: 348 return V_0280A0_COLOR_1_5_5_5; 349 350 case PIPE_FORMAT_B4G4R4A4_UNORM: 351 case PIPE_FORMAT_B4G4R4X4_UNORM: 352 return V_0280A0_COLOR_4_4_4_4; 353 354 case PIPE_FORMAT_Z16_UNORM: 355 return V_0280A0_COLOR_16; 356 357 case PIPE_FORMAT_L8A8_UNORM: 358 case PIPE_FORMAT_L8A8_SNORM: 359 case PIPE_FORMAT_L8A8_UINT: 360 case PIPE_FORMAT_L8A8_SINT: 361 case PIPE_FORMAT_L8A8_SRGB: 362 case PIPE_FORMAT_R8G8_UNORM: 363 case PIPE_FORMAT_R8G8_SNORM: 364 case PIPE_FORMAT_R8G8_UINT: 365 case PIPE_FORMAT_R8G8_SINT: 366 return V_0280A0_COLOR_8_8; 367 368 case PIPE_FORMAT_R16_UNORM: 369 case PIPE_FORMAT_R16_SNORM: 370 case PIPE_FORMAT_R16_UINT: 371 case PIPE_FORMAT_R16_SINT: 372 case PIPE_FORMAT_A16_UNORM: 373 case PIPE_FORMAT_A16_SNORM: 374 case PIPE_FORMAT_A16_UINT: 375 case PIPE_FORMAT_A16_SINT: 376 case PIPE_FORMAT_L16_UNORM: 377 case PIPE_FORMAT_L16_SNORM: 378 case PIPE_FORMAT_L16_UINT: 379 case PIPE_FORMAT_L16_SINT: 380 case PIPE_FORMAT_I16_UNORM: 381 case PIPE_FORMAT_I16_SNORM: 382 case PIPE_FORMAT_I16_UINT: 383 case PIPE_FORMAT_I16_SINT: 384 return V_0280A0_COLOR_16; 385 386 case PIPE_FORMAT_R16_FLOAT: 387 case PIPE_FORMAT_A16_FLOAT: 388 case PIPE_FORMAT_L16_FLOAT: 389 case PIPE_FORMAT_I16_FLOAT: 390 return V_0280A0_COLOR_16_FLOAT; 391 392 /* 32-bit buffers. */ 393 case PIPE_FORMAT_A8B8G8R8_SRGB: 394 case PIPE_FORMAT_A8B8G8R8_UNORM: 395 case PIPE_FORMAT_A8R8G8B8_UNORM: 396 case PIPE_FORMAT_B8G8R8A8_SRGB: 397 case PIPE_FORMAT_B8G8R8A8_UNORM: 398 case PIPE_FORMAT_B8G8R8X8_UNORM: 399 case PIPE_FORMAT_R8G8B8A8_SNORM: 400 case PIPE_FORMAT_R8G8B8A8_UNORM: 401 case PIPE_FORMAT_R8G8B8X8_UNORM: 402 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 403 case PIPE_FORMAT_X8B8G8R8_UNORM: 404 case PIPE_FORMAT_X8R8G8B8_UNORM: 405 case PIPE_FORMAT_R8G8B8_UNORM: 406 case PIPE_FORMAT_R8G8B8A8_SINT: 407 case PIPE_FORMAT_R8G8B8A8_UINT: 408 return V_0280A0_COLOR_8_8_8_8; 409 410 case PIPE_FORMAT_R10G10B10A2_UNORM: 411 case PIPE_FORMAT_R10G10B10X2_SNORM: 412 case PIPE_FORMAT_B10G10R10A2_UNORM: 413 case PIPE_FORMAT_B10G10R10A2_UINT: 414 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 415 return V_0280A0_COLOR_2_10_10_10; 416 417 case PIPE_FORMAT_Z24X8_UNORM: 418 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 419 return V_0280A0_COLOR_8_24; 420 421 case PIPE_FORMAT_X8Z24_UNORM: 422 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 423 return V_0280A0_COLOR_24_8; 424 425 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 426 return V_0280A0_COLOR_X24_8_32_FLOAT; 427 428 case PIPE_FORMAT_R32_UINT: 429 case PIPE_FORMAT_R32_SINT: 430 case PIPE_FORMAT_A32_UINT: 431 case PIPE_FORMAT_A32_SINT: 432 case PIPE_FORMAT_L32_UINT: 433 case PIPE_FORMAT_L32_SINT: 434 case PIPE_FORMAT_I32_UINT: 435 case PIPE_FORMAT_I32_SINT: 436 return V_0280A0_COLOR_32; 437 438 case PIPE_FORMAT_R32_FLOAT: 439 case PIPE_FORMAT_A32_FLOAT: 440 case PIPE_FORMAT_L32_FLOAT: 441 case PIPE_FORMAT_I32_FLOAT: 442 case PIPE_FORMAT_Z32_FLOAT: 443 return V_0280A0_COLOR_32_FLOAT; 444 445 case PIPE_FORMAT_R16G16_FLOAT: 446 case PIPE_FORMAT_L16A16_FLOAT: 447 return V_0280A0_COLOR_16_16_FLOAT; 448 449 case PIPE_FORMAT_R16G16_UNORM: 450 case PIPE_FORMAT_R16G16_SNORM: 451 case PIPE_FORMAT_R16G16_UINT: 452 case PIPE_FORMAT_R16G16_SINT: 453 case PIPE_FORMAT_L16A16_UNORM: 454 case PIPE_FORMAT_L16A16_SNORM: 455 case PIPE_FORMAT_L16A16_UINT: 456 case PIPE_FORMAT_L16A16_SINT: 457 return V_0280A0_COLOR_16_16; 458 459 case PIPE_FORMAT_R11G11B10_FLOAT: 460 return V_0280A0_COLOR_10_11_11_FLOAT; 461 462 /* 64-bit buffers. */ 463 case PIPE_FORMAT_R16G16B16A16_UINT: 464 case PIPE_FORMAT_R16G16B16A16_SINT: 465 case PIPE_FORMAT_R16G16B16A16_UNORM: 466 case PIPE_FORMAT_R16G16B16A16_SNORM: 467 return V_0280A0_COLOR_16_16_16_16; 468 469 case PIPE_FORMAT_R16G16B16_FLOAT: 470 case PIPE_FORMAT_R16G16B16A16_FLOAT: 471 return V_0280A0_COLOR_16_16_16_16_FLOAT; 472 473 case PIPE_FORMAT_R32G32_FLOAT: 474 case PIPE_FORMAT_L32A32_FLOAT: 475 return V_0280A0_COLOR_32_32_FLOAT; 476 477 case PIPE_FORMAT_R32G32_SINT: 478 case PIPE_FORMAT_R32G32_UINT: 479 case PIPE_FORMAT_L32A32_UINT: 480 case PIPE_FORMAT_L32A32_SINT: 481 return V_0280A0_COLOR_32_32; 482 483 /* 96-bit buffers. */ 484 case PIPE_FORMAT_R32G32B32_FLOAT: 485 return V_0280A0_COLOR_32_32_32_FLOAT; 486 487 /* 128-bit buffers. */ 488 case PIPE_FORMAT_R32G32B32A32_FLOAT: 489 return V_0280A0_COLOR_32_32_32_32_FLOAT; 490 case PIPE_FORMAT_R32G32B32A32_SNORM: 491 case PIPE_FORMAT_R32G32B32A32_UNORM: 492 case PIPE_FORMAT_R32G32B32A32_SINT: 493 case PIPE_FORMAT_R32G32B32A32_UINT: 494 return V_0280A0_COLOR_32_32_32_32; 495 496 /* YUV buffers. */ 497 case PIPE_FORMAT_UYVY: 498 case PIPE_FORMAT_YUYV: 499 default: 500 return ~0U; /* Unsupported. */ 501 } 502} 503 504static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 505{ 506 if (R600_BIG_ENDIAN) { 507 switch(colorformat) { 508 case V_0280A0_COLOR_4_4: 509 return ENDIAN_NONE; 510 511 /* 8-bit buffers. */ 512 case V_0280A0_COLOR_8: 513 return ENDIAN_NONE; 514 515 /* 16-bit buffers. */ 516 case V_0280A0_COLOR_5_6_5: 517 case V_0280A0_COLOR_1_5_5_5: 518 case V_0280A0_COLOR_4_4_4_4: 519 case V_0280A0_COLOR_16: 520 case V_0280A0_COLOR_8_8: 521 return ENDIAN_8IN16; 522 523 /* 32-bit buffers. */ 524 case V_0280A0_COLOR_8_8_8_8: 525 case V_0280A0_COLOR_2_10_10_10: 526 case V_0280A0_COLOR_8_24: 527 case V_0280A0_COLOR_24_8: 528 case V_0280A0_COLOR_32_FLOAT: 529 case V_0280A0_COLOR_16_16_FLOAT: 530 case V_0280A0_COLOR_16_16: 531 return ENDIAN_8IN32; 532 533 /* 64-bit buffers. */ 534 case V_0280A0_COLOR_16_16_16_16: 535 case V_0280A0_COLOR_16_16_16_16_FLOAT: 536 return ENDIAN_8IN16; 537 538 case V_0280A0_COLOR_32_32_FLOAT: 539 case V_0280A0_COLOR_32_32: 540 case V_0280A0_COLOR_X24_8_32_FLOAT: 541 return ENDIAN_8IN32; 542 543 /* 128-bit buffers. */ 544 case V_0280A0_COLOR_32_32_32_FLOAT: 545 case V_0280A0_COLOR_32_32_32_32_FLOAT: 546 case V_0280A0_COLOR_32_32_32_32: 547 return ENDIAN_8IN32; 548 default: 549 return ENDIAN_NONE; /* Unsupported. */ 550 } 551 } else { 552 return ENDIAN_NONE; 553 } 554} 555 556static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 557{ 558 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 559} 560 561static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 562{ 563 return r600_translate_colorformat(format) != ~0U && 564 r600_translate_colorswap(format) != ~0U; 565} 566 567static bool r600_is_zs_format_supported(enum pipe_format format) 568{ 569 return r600_translate_dbformat(format) != ~0U; 570} 571 572boolean r600_is_format_supported(struct pipe_screen *screen, 573 enum pipe_format format, 574 enum pipe_texture_target target, 575 unsigned sample_count, 576 unsigned usage) 577{ 578 unsigned retval = 0; 579 580 if (target >= PIPE_MAX_TEXTURE_TYPES) { 581 R600_ERR("r600: unsupported texture type %d\n", target); 582 return FALSE; 583 } 584 585 if (!util_format_is_supported(format, usage)) 586 return FALSE; 587 588 /* Multisample */ 589 if (sample_count > 1) 590 return FALSE; 591 592 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 593 r600_is_sampler_format_supported(screen, format)) { 594 retval |= PIPE_BIND_SAMPLER_VIEW; 595 } 596 597 if ((usage & (PIPE_BIND_RENDER_TARGET | 598 PIPE_BIND_DISPLAY_TARGET | 599 PIPE_BIND_SCANOUT | 600 PIPE_BIND_SHARED)) && 601 r600_is_colorbuffer_format_supported(format)) { 602 retval |= usage & 603 (PIPE_BIND_RENDER_TARGET | 604 PIPE_BIND_DISPLAY_TARGET | 605 PIPE_BIND_SCANOUT | 606 PIPE_BIND_SHARED); 607 } 608 609 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 610 r600_is_zs_format_supported(format)) { 611 retval |= PIPE_BIND_DEPTH_STENCIL; 612 } 613 614 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 615 r600_is_vertex_format_supported(format)) { 616 retval |= PIPE_BIND_VERTEX_BUFFER; 617 } 618 619 if (usage & PIPE_BIND_TRANSFER_READ) 620 retval |= PIPE_BIND_TRANSFER_READ; 621 if (usage & PIPE_BIND_TRANSFER_WRITE) 622 retval |= PIPE_BIND_TRANSFER_WRITE; 623 624 return retval == usage; 625} 626 627void r600_polygon_offset_update(struct r600_context *rctx) 628{ 629 struct r600_pipe_state state; 630 631 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 632 state.nregs = 0; 633 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 634 float offset_units = rctx->rasterizer->offset_units; 635 unsigned offset_db_fmt_cntl = 0, depth; 636 637 switch (rctx->framebuffer.zsbuf->texture->format) { 638 case PIPE_FORMAT_Z24X8_UNORM: 639 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 640 depth = -24; 641 offset_units *= 2.0f; 642 break; 643 case PIPE_FORMAT_Z32_FLOAT: 644 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 645 depth = -23; 646 offset_units *= 1.0f; 647 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 648 break; 649 case PIPE_FORMAT_Z16_UNORM: 650 depth = -16; 651 offset_units *= 4.0f; 652 break; 653 default: 654 return; 655 } 656 /* XXX some of those reg can be computed with cso */ 657 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 658 r600_pipe_state_add_reg(&state, 659 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 660 fui(rctx->rasterizer->offset_scale), NULL, 0); 661 r600_pipe_state_add_reg(&state, 662 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 663 fui(offset_units), NULL, 0); 664 r600_pipe_state_add_reg(&state, 665 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 666 fui(rctx->rasterizer->offset_scale), NULL, 0); 667 r600_pipe_state_add_reg(&state, 668 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 669 fui(offset_units), NULL, 0); 670 r600_pipe_state_add_reg(&state, 671 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 672 offset_db_fmt_cntl, NULL, 0); 673 r600_context_pipe_state_set(rctx, &state); 674 } 675} 676 677static void *r600_create_blend_state(struct pipe_context *ctx, 678 const struct pipe_blend_state *state) 679{ 680 struct r600_context *rctx = (struct r600_context *)ctx; 681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 682 struct r600_pipe_state *rstate; 683 uint32_t color_control = 0, target_mask; 684 685 if (blend == NULL) { 686 return NULL; 687 } 688 rstate = &blend->rstate; 689 690 rstate->id = R600_PIPE_STATE_BLEND; 691 692 target_mask = 0; 693 694 /* R600 does not support per-MRT blends */ 695 if (rctx->family > CHIP_R600) 696 color_control |= S_028808_PER_MRT_BLEND(1); 697 if (state->logicop_enable) { 698 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 699 } else { 700 color_control |= (0xcc << 16); 701 } 702 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 703 if (state->independent_blend_enable) { 704 for (int i = 0; i < 8; i++) { 705 if (state->rt[i].blend_enable) { 706 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 707 } 708 target_mask |= (state->rt[i].colormask << (4 * i)); 709 } 710 } else { 711 for (int i = 0; i < 8; i++) { 712 if (state->rt[0].blend_enable) { 713 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 714 } 715 target_mask |= (state->rt[0].colormask << (4 * i)); 716 } 717 } 718 blend->cb_target_mask = target_mask; 719 blend->cb_color_control = color_control; 720 721 for (int i = 0; i < 8; i++) { 722 /* state->rt entries > 0 only written if independent blending */ 723 const int j = state->independent_blend_enable ? i : 0; 724 725 unsigned eqRGB = state->rt[j].rgb_func; 726 unsigned srcRGB = state->rt[j].rgb_src_factor; 727 unsigned dstRGB = state->rt[j].rgb_dst_factor; 728 729 unsigned eqA = state->rt[j].alpha_func; 730 unsigned srcA = state->rt[j].alpha_src_factor; 731 unsigned dstA = state->rt[j].alpha_dst_factor; 732 uint32_t bc = 0; 733 734 if (!state->rt[j].blend_enable) 735 continue; 736 737 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 738 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 739 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 740 741 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 742 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 743 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 744 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 745 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 746 } 747 748 /* R600 does not support per-MRT blends */ 749 if (rctx->family > CHIP_R600) 750 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0); 751 if (i == 0) 752 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0); 753 } 754 return rstate; 755} 756 757static void *r600_create_dsa_state(struct pipe_context *ctx, 758 const struct pipe_depth_stencil_alpha_state *state) 759{ 760 struct r600_context *rctx = (struct r600_context *)ctx; 761 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 762 unsigned db_depth_control, alpha_test_control, alpha_ref; 763 struct r600_pipe_state *rstate; 764 765 if (dsa == NULL) { 766 return NULL; 767 } 768 769 dsa->valuemask[0] = state->stencil[0].valuemask; 770 dsa->valuemask[1] = state->stencil[1].valuemask; 771 dsa->writemask[0] = state->stencil[0].writemask; 772 dsa->writemask[1] = state->stencil[1].writemask; 773 774 rstate = &dsa->rstate; 775 776 rstate->id = R600_PIPE_STATE_DSA; 777 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 778 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 779 S_028800_ZFUNC(state->depth.func); 780 781 /* stencil */ 782 if (state->stencil[0].enabled) { 783 db_depth_control |= S_028800_STENCIL_ENABLE(1); 784 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 785 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 786 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 787 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 788 789 if (state->stencil[1].enabled) { 790 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 791 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 792 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 793 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 794 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 795 } 796 } 797 798 /* alpha */ 799 alpha_test_control = 0; 800 alpha_ref = 0; 801 if (state->alpha.enabled) { 802 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 803 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 804 alpha_ref = fui(state->alpha.ref_value); 805 } 806 dsa->alpha_ref = alpha_ref; 807 808 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0); 809 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0); 810 return rstate; 811} 812 813static void *r600_create_rs_state(struct pipe_context *ctx, 814 const struct pipe_rasterizer_state *state) 815{ 816 struct r600_context *rctx = (struct r600_context *)ctx; 817 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 818 struct r600_pipe_state *rstate; 819 unsigned tmp; 820 unsigned prov_vtx = 1, polygon_dual_mode; 821 unsigned sc_mode_cntl; 822 float psize_min, psize_max; 823 824 if (rs == NULL) { 825 return NULL; 826 } 827 828 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 829 state->fill_back != PIPE_POLYGON_MODE_FILL); 830 831 if (state->flatshade_first) 832 prov_vtx = 0; 833 834 rstate = &rs->rstate; 835 rs->flatshade = state->flatshade; 836 rs->sprite_coord_enable = state->sprite_coord_enable; 837 rs->two_side = state->light_twoside; 838 rs->clip_plane_enable = state->clip_plane_enable; 839 rs->pa_sc_line_stipple = state->line_stipple_enable ? 840 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 841 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 842 rs->pa_cl_clip_cntl = 843 S_028810_PS_UCP_MODE(3) | 844 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 845 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 846 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 847 848 /* offset */ 849 rs->offset_units = state->offset_units; 850 rs->offset_scale = state->offset_scale * 12.0f; 851 852 rstate->id = R600_PIPE_STATE_RASTERIZER; 853 tmp = S_0286D4_FLAT_SHADE_ENA(1); 854 if (state->sprite_coord_enable) { 855 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 856 S_0286D4_PNT_SPRITE_OVRD_X(2) | 857 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 858 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 859 S_0286D4_PNT_SPRITE_OVRD_W(1); 860 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 861 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 862 } 863 } 864 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0); 865 866 /* point size 12.4 fixed point */ 867 tmp = r600_pack_float_12p4(state->point_size/2); 868 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0); 869 870 if (state->point_size_per_vertex) { 871 psize_min = util_get_min_point_size(state); 872 psize_max = 8192; 873 } else { 874 /* Force the point size to be as if the vertex output was disabled. */ 875 psize_min = state->point_size; 876 psize_max = state->point_size; 877 } 878 /* Divide by two, because 0.5 = 1 pixel. */ 879 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 880 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 881 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)), 882 NULL, 0); 883 884 tmp = r600_pack_float_12p4(state->line_width/2); 885 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0); 886 887 if (rctx->chip_class >= R700) { 888 sc_mode_cntl = 889 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 890 S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 891 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 892 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); 893 } else { 894 sc_mode_cntl = 895 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 896 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); 897 rs->scissor_enable = state->scissor; 898 } 899 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 900 901 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl, 902 NULL, 0); 903 904 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 905 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 906 NULL, 0); 907 908 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0); 909 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 910 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 911 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | 912 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | 913 S_028814_FACE(!state->front_ccw) | 914 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 915 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 916 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 917 S_028814_POLY_MODE(polygon_dual_mode) | 918 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 919 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 920 NULL, 0); 921 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard), NULL, 0); 922 return rstate; 923} 924 925static void *r600_create_sampler_state(struct pipe_context *ctx, 926 const struct pipe_sampler_state *state) 927{ 928 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 929 struct r600_pipe_state *rstate; 930 union util_color uc; 931 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 932 933 if (ss == NULL) { 934 return NULL; 935 } 936 937 ss->seamless_cube_map = state->seamless_cube_map; 938 rstate = &ss->rstate; 939 rstate->id = R600_PIPE_STATE_SAMPLER; 940 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 941 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 942 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 943 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 944 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 945 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 946 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 947 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 948 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 949 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 950 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0); 951 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 952 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 953 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 954 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0); 955 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0); 956 if (uc.ui) { 957 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0); 958 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0); 959 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0); 960 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0); 961 } 962 return rstate; 963} 964 965static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 966 struct pipe_resource *texture, 967 const struct pipe_sampler_view *state) 968{ 969 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 970 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 971 struct r600_pipe_resource_state *rstate; 972 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 973 unsigned format, endian; 974 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 975 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 976 unsigned width, height, depth, offset_level, last_level; 977 978 if (view == NULL) 979 return NULL; 980 rstate = &view->state; 981 982 /* initialize base object */ 983 view->base = *state; 984 view->base.texture = NULL; 985 pipe_reference(NULL, &texture->reference); 986 view->base.texture = texture; 987 view->base.reference.count = 1; 988 view->base.context = ctx; 989 990 swizzle[0] = state->swizzle_r; 991 swizzle[1] = state->swizzle_g; 992 swizzle[2] = state->swizzle_b; 993 swizzle[3] = state->swizzle_a; 994 995 format = r600_translate_texformat(ctx->screen, state->format, 996 swizzle, 997 &word4, &yuv_format); 998 if (format == ~0) { 999 format = 0; 1000 } 1001 1002 if (tmp->is_depth && !tmp->is_flushing_texture) { 1003 r600_texture_depth_flush(ctx, texture, TRUE); 1004 tmp = tmp->flushed_depth_texture; 1005 } 1006 1007 endian = r600_colorformat_endian_swap(format); 1008 1009 offset_level = state->u.tex.first_level; 1010 last_level = state->u.tex.last_level - offset_level; 1011 if (!rscreen->use_surface_alloc) { 1012 width = u_minify(texture->width0, offset_level); 1013 height = u_minify(texture->height0, offset_level); 1014 depth = u_minify(texture->depth0, offset_level); 1015 1016 pitch = align(tmp->pitch_in_blocks[offset_level] * 1017 util_format_get_blockwidth(state->format), 8); 1018 array_mode = tmp->array_mode[offset_level]; 1019 tile_type = tmp->tile_type; 1020 1021 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1022 height = 1; 1023 depth = texture->array_size; 1024 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1025 depth = texture->array_size; 1026 } 1027 1028 rstate->bo[0] = &tmp->resource; 1029 rstate->bo[1] = &tmp->resource; 1030 rstate->bo_usage[0] = RADEON_USAGE_READ; 1031 rstate->bo_usage[1] = RADEON_USAGE_READ; 1032 1033 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1034 S_038000_TILE_MODE(array_mode) | 1035 S_038000_TILE_TYPE(tile_type) | 1036 S_038000_PITCH((pitch / 8) - 1) | 1037 S_038000_TEX_WIDTH(width - 1)); 1038 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1039 S_038004_TEX_DEPTH(depth - 1) | 1040 S_038004_DATA_FORMAT(format)); 1041 rstate->val[2] = tmp->offset[offset_level] >> 8; 1042 rstate->val[3] = tmp->offset[offset_level+1] >> 8; 1043 rstate->val[4] = (word4 | 1044 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1045 S_038010_REQUEST_SIZE(1) | 1046 S_038010_ENDIAN_SWAP(endian) | 1047 S_038010_BASE_LEVEL(0)); 1048 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1049 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1050 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1051 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1052 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1053 } else { 1054 width = tmp->surface.level[offset_level].npix_x; 1055 height = tmp->surface.level[offset_level].npix_y; 1056 depth = tmp->surface.level[offset_level].npix_z; 1057 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1058 tile_type = tmp->tile_type; 1059 1060 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1061 height = 1; 1062 depth = texture->array_size; 1063 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1064 depth = texture->array_size; 1065 } 1066 switch (tmp->surface.level[offset_level].mode) { 1067 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1068 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1069 break; 1070 case RADEON_SURF_MODE_1D: 1071 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1072 break; 1073 case RADEON_SURF_MODE_2D: 1074 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1075 break; 1076 case RADEON_SURF_MODE_LINEAR: 1077 default: 1078 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1079 break; 1080 } 1081 1082 rstate->bo[0] = &tmp->resource; 1083 rstate->bo[1] = &tmp->resource; 1084 rstate->bo_usage[0] = RADEON_USAGE_READ; 1085 rstate->bo_usage[1] = RADEON_USAGE_READ; 1086 1087 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1088 S_038000_TILE_MODE(array_mode) | 1089 S_038000_TILE_TYPE(tile_type) | 1090 S_038000_PITCH((pitch / 8) - 1) | 1091 S_038000_TEX_WIDTH(width - 1)); 1092 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1093 S_038004_TEX_DEPTH(depth - 1) | 1094 S_038004_DATA_FORMAT(format)); 1095 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8; 1096 if (offset_level >= tmp->surface.last_level) { 1097 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8; 1098 } else { 1099 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1100 } 1101 rstate->val[4] = (word4 | 1102 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1103 S_038010_REQUEST_SIZE(1) | 1104 S_038010_ENDIAN_SWAP(endian) | 1105 S_038010_BASE_LEVEL(0)); 1106 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1107 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1108 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1109 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1110 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1111 } 1112 return &view->base; 1113} 1114 1115static void r600_set_sampler_views(struct r600_context *rctx, 1116 struct r600_textures_info *dst, 1117 unsigned count, 1118 struct pipe_sampler_view **views, 1119 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned)) 1120{ 1121 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 1122 unsigned i; 1123 1124 if (count) 1125 r600_inval_texture_cache(rctx); 1126 1127 for (i = 0; i < count; i++) { 1128 if (rviews[i]) { 1129 if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth) 1130 rctx->have_depth_texture = true; 1131 1132 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */ 1133 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1134 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) 1135 dst->samplers_dirty = true; 1136 1137 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS); 1138 } else { 1139 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1140 } 1141 1142 pipe_sampler_view_reference( 1143 (struct pipe_sampler_view **)&dst->views[i], 1144 views[i]); 1145 } 1146 1147 for (i = count; i < dst->n_views; i++) { 1148 if (dst->views[i]) { 1149 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1150 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL); 1151 } 1152 } 1153 1154 dst->n_views = count; 1155} 1156 1157static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1158 struct pipe_sampler_view **views) 1159{ 1160 struct r600_context *rctx = (struct r600_context *)ctx; 1161 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views, 1162 r600_context_pipe_state_set_vs_resource); 1163} 1164 1165static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1166 struct pipe_sampler_view **views) 1167{ 1168 struct r600_context *rctx = (struct r600_context *)ctx; 1169 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views, 1170 r600_context_pipe_state_set_ps_resource); 1171} 1172 1173static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable) 1174{ 1175 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1176 if (rstate == NULL) 1177 return; 1178 1179 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP; 1180 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 1181 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) | 1182 S_009508_DISABLE_CUBE_ANISO(1) | 1183 S_009508_SYNC_GRADIENT(1) | 1184 S_009508_SYNC_WALKER(1) | 1185 S_009508_SYNC_ALIGNER(1), 1186 NULL, 0); 1187 1188 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]); 1189 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate; 1190 r600_context_pipe_state_set(rctx, rstate); 1191} 1192 1193static void r600_bind_samplers(struct r600_context *rctx, 1194 struct r600_textures_info *dst, 1195 unsigned count, void **states) 1196{ 1197 memcpy(dst->samplers, states, sizeof(void*) * count); 1198 dst->n_samplers = count; 1199 dst->samplers_dirty = true; 1200} 1201 1202static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 1203{ 1204 struct r600_context *rctx = (struct r600_context *)ctx; 1205 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states); 1206} 1207 1208static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 1209{ 1210 struct r600_context *rctx = (struct r600_context *)ctx; 1211 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states); 1212} 1213 1214static void r600_update_samplers(struct r600_context *rctx, 1215 struct r600_textures_info *tex, 1216 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned)) 1217{ 1218 unsigned i; 1219 1220 if (tex->samplers_dirty) { 1221 int seamless = -1; 1222 for (i = 0; i < tex->n_samplers; i++) { 1223 if (!tex->samplers[i]) 1224 continue; 1225 1226 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1227 * filtering between layers. 1228 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */ 1229 if (tex->views[i]) { 1230 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1231 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1232 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1233 tex->is_array_sampler[i] = true; 1234 } else { 1235 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE; 1236 tex->is_array_sampler[i] = false; 1237 } 1238 } 1239 1240 set_sampler(rctx, &tex->samplers[i]->rstate, i); 1241 1242 if (tex->samplers[i]) 1243 seamless = tex->samplers[i]->seamless_cube_map; 1244 } 1245 1246 if (seamless != -1) 1247 r600_set_seamless_cubemap(rctx, seamless); 1248 1249 tex->samplers_dirty = false; 1250 } 1251} 1252 1253void r600_update_sampler_states(struct r600_context *rctx) 1254{ 1255 r600_update_samplers(rctx, &rctx->vs_samplers, 1256 r600_context_pipe_state_set_vs_sampler); 1257 r600_update_samplers(rctx, &rctx->ps_samplers, 1258 r600_context_pipe_state_set_ps_sampler); 1259} 1260 1261static void r600_set_clip_state(struct pipe_context *ctx, 1262 const struct pipe_clip_state *state) 1263{ 1264 struct r600_context *rctx = (struct r600_context *)ctx; 1265 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1266 struct pipe_resource * cbuf; 1267 1268 if (rstate == NULL) 1269 return; 1270 1271 rctx->clip = *state; 1272 rstate->id = R600_PIPE_STATE_CLIP; 1273 for (int i = 0; i < 6; i++) { 1274 r600_pipe_state_add_reg(rstate, 1275 R_028E20_PA_CL_UCP0_X + i * 16, 1276 fui(state->ucp[i][0]), NULL, 0); 1277 r600_pipe_state_add_reg(rstate, 1278 R_028E24_PA_CL_UCP0_Y + i * 16, 1279 fui(state->ucp[i][1]) , NULL, 0); 1280 r600_pipe_state_add_reg(rstate, 1281 R_028E28_PA_CL_UCP0_Z + i * 16, 1282 fui(state->ucp[i][2]), NULL, 0); 1283 r600_pipe_state_add_reg(rstate, 1284 R_028E2C_PA_CL_UCP0_W + i * 16, 1285 fui(state->ucp[i][3]), NULL, 0); 1286 } 1287 1288 free(rctx->states[R600_PIPE_STATE_CLIP]); 1289 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1290 r600_context_pipe_state_set(rctx, rstate); 1291 1292 cbuf = pipe_user_buffer_create(ctx->screen, 1293 state->ucp, 1294 4*4*8, /* 8*4 floats */ 1295 PIPE_BIND_CONSTANT_BUFFER); 1296 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf); 1297 pipe_resource_reference(&cbuf, NULL); 1298} 1299 1300static void r600_set_polygon_stipple(struct pipe_context *ctx, 1301 const struct pipe_poly_stipple *state) 1302{ 1303} 1304 1305static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1306{ 1307} 1308 1309void r600_set_scissor_state(struct r600_context *rctx, 1310 const struct pipe_scissor_state *state) 1311{ 1312 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1313 uint32_t tl, br; 1314 1315 if (rstate == NULL) 1316 return; 1317 1318 rstate->id = R600_PIPE_STATE_SCISSOR; 1319 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1320 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1321 r600_pipe_state_add_reg(rstate, 1322 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 1323 NULL, 0); 1324 r600_pipe_state_add_reg(rstate, 1325 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 1326 NULL, 0); 1327 1328 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1329 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1330 r600_context_pipe_state_set(rctx, rstate); 1331} 1332 1333static void r600_pipe_set_scissor_state(struct pipe_context *ctx, 1334 const struct pipe_scissor_state *state) 1335{ 1336 struct r600_context *rctx = (struct r600_context *)ctx; 1337 1338 if (rctx->chip_class == R600) { 1339 rctx->scissor_state = *state; 1340 1341 if (!rctx->scissor_enable) 1342 return; 1343 } 1344 1345 r600_set_scissor_state(rctx, state); 1346} 1347 1348static void r600_set_viewport_state(struct pipe_context *ctx, 1349 const struct pipe_viewport_state *state) 1350{ 1351 struct r600_context *rctx = (struct r600_context *)ctx; 1352 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1353 1354 if (rstate == NULL) 1355 return; 1356 1357 rctx->viewport = *state; 1358 rstate->id = R600_PIPE_STATE_VIEWPORT; 1359 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0); 1360 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0); 1361 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0); 1362 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0); 1363 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0); 1364 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0); 1365 1366 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1367 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1368 r600_context_pipe_state_set(rctx, rstate); 1369} 1370 1371static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 1372 const struct pipe_framebuffer_state *state, int cb) 1373{ 1374 struct r600_screen *rscreen = rctx->screen; 1375 struct r600_resource_texture *rtex; 1376 struct r600_surface *surf; 1377 unsigned level = state->cbufs[cb]->u.tex.level; 1378 unsigned pitch, slice; 1379 unsigned color_info; 1380 unsigned format, swap, ntype, endian; 1381 unsigned offset; 1382 const struct util_format_description *desc; 1383 int i; 1384 unsigned blend_bypass = 0, blend_clamp = 1; 1385 1386 surf = (struct r600_surface *)state->cbufs[cb]; 1387 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1388 1389 if (rtex->is_depth) 1390 rctx->have_depth_fb = TRUE; 1391 1392 if (rtex->is_depth && !rtex->is_flushing_texture) { 1393 rtex = rtex->flushed_depth_texture; 1394 } 1395 1396 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1397 if (!rscreen->use_surface_alloc) { 1398 offset = r600_texture_get_offset(rtex, 1399 level, state->cbufs[cb]->u.tex.first_layer); 1400 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1401 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1402 if (slice) { 1403 slice = slice - 1; 1404 } 1405 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]); 1406 } else { 1407 offset = rtex->surface.level[level].offset; 1408 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1409 offset += rtex->surface.level[level].slice_size * 1410 state->cbufs[cb]->u.tex.first_layer; 1411 } 1412 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1413 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1414 if (slice) { 1415 slice = slice - 1; 1416 } 1417 color_info = 0; 1418 switch (rtex->surface.level[level].mode) { 1419 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1420 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1421 break; 1422 case RADEON_SURF_MODE_1D: 1423 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1424 break; 1425 case RADEON_SURF_MODE_2D: 1426 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1427 break; 1428 case RADEON_SURF_MODE_LINEAR: 1429 default: 1430 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1431 break; 1432 } 1433 } 1434 desc = util_format_description(surf->base.format); 1435 1436 for (i = 0; i < 4; i++) { 1437 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1438 break; 1439 } 1440 } 1441 1442 ntype = V_0280A0_NUMBER_UNORM; 1443 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1444 ntype = V_0280A0_NUMBER_SRGB; 1445 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1446 if (desc->channel[i].normalized) 1447 ntype = V_0280A0_NUMBER_SNORM; 1448 else if (desc->channel[i].pure_integer) 1449 ntype = V_0280A0_NUMBER_SINT; 1450 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1451 if (desc->channel[i].normalized) 1452 ntype = V_0280A0_NUMBER_UNORM; 1453 else if (desc->channel[i].pure_integer) 1454 ntype = V_0280A0_NUMBER_UINT; 1455 } 1456 1457 format = r600_translate_colorformat(surf->base.format); 1458 swap = r600_translate_colorswap(surf->base.format); 1459 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) { 1460 endian = ENDIAN_NONE; 1461 } else { 1462 endian = r600_colorformat_endian_swap(format); 1463 } 1464 1465 /* set blend bypass according to docs if SINT/UINT or 1466 8/24 COLOR variants */ 1467 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1468 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1469 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1470 blend_clamp = 0; 1471 blend_bypass = 1; 1472 } 1473 1474 color_info |= S_0280A0_FORMAT(format) | 1475 S_0280A0_COMP_SWAP(swap) | 1476 S_0280A0_BLEND_BYPASS(blend_bypass) | 1477 S_0280A0_BLEND_CLAMP(blend_clamp) | 1478 S_0280A0_NUMBER_TYPE(ntype) | 1479 S_0280A0_ENDIAN(endian); 1480 1481 /* EXPORT_NORM is an optimzation that can be enabled for better 1482 * performance in certain cases 1483 */ 1484 if (rctx->chip_class == R600) { 1485 /* EXPORT_NORM can be enabled if: 1486 * - 11-bit or smaller UNORM/SNORM/SRGB 1487 * - BLEND_CLAMP is enabled 1488 * - BLEND_FLOAT32 is disabled 1489 */ 1490 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1491 (desc->channel[i].size < 12 && 1492 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1493 ntype != V_0280A0_NUMBER_UINT && 1494 ntype != V_0280A0_NUMBER_SINT) && 1495 G_0280A0_BLEND_CLAMP(color_info) && 1496 !G_0280A0_BLEND_FLOAT32(color_info)) 1497 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1498 } else { 1499 /* EXPORT_NORM can be enabled if: 1500 * - 11-bit or smaller UNORM/SNORM/SRGB 1501 * - 16-bit or smaller FLOAT 1502 */ 1503 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1504 ((desc->channel[i].size < 12 && 1505 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1506 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1507 (desc->channel[i].size < 17 && 1508 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) 1509 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1510 } 1511 1512 r600_pipe_state_add_reg(rstate, 1513 R_028040_CB_COLOR0_BASE + cb * 4, 1514 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1515 r600_pipe_state_add_reg(rstate, 1516 R_0280A0_CB_COLOR0_INFO + cb * 4, 1517 color_info, &rtex->resource, RADEON_USAGE_READWRITE); 1518 r600_pipe_state_add_reg(rstate, 1519 R_028060_CB_COLOR0_SIZE + cb * 4, 1520 S_028060_PITCH_TILE_MAX(pitch) | 1521 S_028060_SLICE_TILE_MAX(slice), 1522 NULL, 0); 1523 if (!rscreen->use_surface_alloc) { 1524 r600_pipe_state_add_reg(rstate, 1525 R_028080_CB_COLOR0_VIEW + cb * 4, 1526 0x00000000, NULL, 0); 1527 } else { 1528 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1529 r600_pipe_state_add_reg(rstate, 1530 R_028080_CB_COLOR0_VIEW + cb * 4, 1531 0x00000000, NULL, 0); 1532 } else { 1533 r600_pipe_state_add_reg(rstate, 1534 R_028080_CB_COLOR0_VIEW + cb * 4, 1535 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1536 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer), 1537 NULL, 0); 1538 } 1539 } 1540 r600_pipe_state_add_reg(rstate, 1541 R_0280E0_CB_COLOR0_FRAG + cb * 4, 1542 0, &rtex->resource, RADEON_USAGE_READWRITE); 1543 r600_pipe_state_add_reg(rstate, 1544 R_0280C0_CB_COLOR0_TILE + cb * 4, 1545 0, &rtex->resource, RADEON_USAGE_READWRITE); 1546} 1547 1548static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate, 1549 const struct pipe_framebuffer_state *state) 1550{ 1551 struct r600_screen *rscreen = rctx->screen; 1552 struct r600_resource_texture *rtex; 1553 struct r600_surface *surf; 1554 unsigned level, pitch, slice, format, offset, array_mode; 1555 1556 if (state->zsbuf == NULL) 1557 return; 1558 1559 level = state->zsbuf->u.tex.level; 1560 1561 surf = (struct r600_surface *)state->zsbuf; 1562 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 1563 1564 if (!rscreen->use_surface_alloc) { 1565 /* XXX remove this once tiling is properly supported */ 1566 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] : 1567 V_0280A0_ARRAY_1D_TILED_THIN1; 1568 1569 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1570 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 1571 level, state->zsbuf->u.tex.first_layer); 1572 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1573 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1574 if (slice) { 1575 slice = slice - 1; 1576 } 1577 } else { 1578 offset = rtex->surface.level[level].offset; 1579 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1580 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1581 if (slice) { 1582 slice = slice - 1; 1583 } 1584 switch (rtex->surface.level[level].mode) { 1585 case RADEON_SURF_MODE_2D: 1586 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1587 break; 1588 case RADEON_SURF_MODE_1D: 1589 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1590 case RADEON_SURF_MODE_LINEAR: 1591 default: 1592 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1593 break; 1594 } 1595 } 1596 1597 format = r600_translate_dbformat(state->zsbuf->texture->format); 1598 1599 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, 1600 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1601 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, 1602 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 1603 NULL, 0); 1604 if (!rscreen->use_surface_alloc) { 1605 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0); 1606 } else { 1607 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 1608 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) | 1609 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer), 1610 NULL, 0); 1611 } 1612 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO, 1613 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format), 1614 &rtex->resource, RADEON_USAGE_READWRITE); 1615 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, 1616 (surf->aligned_height / 8) - 1, NULL, 0); 1617} 1618 1619static void r600_set_framebuffer_state(struct pipe_context *ctx, 1620 const struct pipe_framebuffer_state *state) 1621{ 1622 struct r600_context *rctx = (struct r600_context *)ctx; 1623 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1624 uint32_t shader_mask, tl, br, shader_control; 1625 1626 if (rstate == NULL) 1627 return; 1628 1629 r600_flush_framebuffer(rctx, false); 1630 1631 /* unreference old buffer and reference new one */ 1632 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1633 1634 util_copy_framebuffer_state(&rctx->framebuffer, state); 1635 1636 /* build states */ 1637 rctx->have_depth_fb = 0; 1638 for (int i = 0; i < state->nr_cbufs; i++) { 1639 r600_cb(rctx, rstate, state, i); 1640 } 1641 if (state->zsbuf) { 1642 r600_db(rctx, rstate, state); 1643 } 1644 1645 shader_mask = 0; 1646 shader_control = 0; 1647 for (int i = 0; i < state->nr_cbufs; i++) { 1648 shader_mask |= 0xf << (i * 4); 1649 shader_control |= 1 << i; 1650 } 1651 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1652 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1653 1654 r600_pipe_state_add_reg(rstate, 1655 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 1656 NULL, 0); 1657 r600_pipe_state_add_reg(rstate, 1658 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 1659 NULL, 0); 1660 1661 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1662 shader_control, NULL, 0); 1663 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 1664 shader_mask, NULL, 0); 1665 1666 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1667 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1668 r600_context_pipe_state_set(rctx, rstate); 1669 1670 if (state->zsbuf) { 1671 r600_polygon_offset_update(rctx); 1672 } 1673} 1674 1675static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1676{ 1677 struct radeon_winsys_cs *cs = rctx->cs; 1678 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 1679 unsigned db_render_control = 0; 1680 unsigned db_render_override = 1681 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 1682 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1683 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1684 1685 if (a->occlusion_query_enabled) { 1686 if (rctx->chip_class >= R700) { 1687 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1688 } 1689 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1690 } 1691 if (a->flush_depthstencil_enabled) { 1692 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) | 1693 S_028D0C_STENCIL_COPY_ENABLE(1) | 1694 S_028D0C_COPY_CENTROID(1); 1695 } 1696 1697 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1698 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1699 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1700} 1701 1702static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) 1703{ 1704 struct radeon_winsys_cs *cs = rctx->cs; 1705 struct pipe_vertex_buffer *vb = rctx->vbuf_mgr->real_vertex_buffer; 1706 unsigned count = rctx->vbuf_mgr->nr_real_vertex_buffers; 1707 unsigned i, offset; 1708 1709 for (i = 0; i < count; i++) { 1710 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer; 1711 1712 if (!rbuffer) { 1713 continue; 1714 } 1715 1716 offset = vb[i].buffer_offset; 1717 1718 /* fetch resources start at index 320 */ 1719 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1720 r600_write_value(cs, (320 + i) * 7); 1721 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1722 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1723 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1724 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1725 S_038008_STRIDE(vb[i].stride)); 1726 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1727 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1728 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1729 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1730 1731 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1732 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1733 } 1734} 1735 1736void r600_init_state_functions(struct r600_context *rctx) 1737{ 1738 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); 1739 r600_atom_dirty(rctx, &rctx->db_misc_state.atom); 1740 r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0); 1741 1742 rctx->context.create_blend_state = r600_create_blend_state; 1743 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 1744 rctx->context.create_fs_state = r600_create_shader_state; 1745 rctx->context.create_rasterizer_state = r600_create_rs_state; 1746 rctx->context.create_sampler_state = r600_create_sampler_state; 1747 rctx->context.create_sampler_view = r600_create_sampler_view; 1748 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 1749 rctx->context.create_vs_state = r600_create_shader_state; 1750 rctx->context.bind_blend_state = r600_bind_blend_state; 1751 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 1752 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 1753 rctx->context.bind_fs_state = r600_bind_ps_shader; 1754 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 1755 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 1756 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 1757 rctx->context.bind_vs_state = r600_bind_vs_shader; 1758 rctx->context.delete_blend_state = r600_delete_state; 1759 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 1760 rctx->context.delete_fs_state = r600_delete_ps_shader; 1761 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 1762 rctx->context.delete_sampler_state = r600_delete_state; 1763 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 1764 rctx->context.delete_vs_state = r600_delete_vs_shader; 1765 rctx->context.set_blend_color = r600_set_blend_color; 1766 rctx->context.set_clip_state = r600_set_clip_state; 1767 rctx->context.set_constant_buffer = r600_set_constant_buffer; 1768 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 1769 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 1770 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 1771 rctx->context.set_sample_mask = r600_set_sample_mask; 1772 rctx->context.set_scissor_state = r600_pipe_set_scissor_state; 1773 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 1774 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 1775 rctx->context.set_index_buffer = r600_set_index_buffer; 1776 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 1777 rctx->context.set_viewport_state = r600_set_viewport_state; 1778 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 1779 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 1780 rctx->context.texture_barrier = r600_texture_barrier; 1781 rctx->context.create_stream_output_target = r600_create_so_target; 1782 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 1783 rctx->context.set_stream_output_targets = r600_set_so_targets; 1784} 1785 1786void r600_adjust_gprs(struct r600_context *rctx) 1787{ 1788 struct r600_pipe_state rstate; 1789 unsigned num_ps_gprs = rctx->default_ps_gprs; 1790 unsigned num_vs_gprs = rctx->default_vs_gprs; 1791 unsigned tmp; 1792 int diff; 1793 1794 if (rctx->chip_class >= EVERGREEN) 1795 return; 1796 1797 if (!rctx->ps_shader || !rctx->vs_shader) 1798 return; 1799 1800 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs) 1801 { 1802 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs; 1803 num_vs_gprs -= diff; 1804 num_ps_gprs += diff; 1805 } 1806 1807 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs) 1808 { 1809 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs; 1810 num_ps_gprs -= diff; 1811 num_vs_gprs += diff; 1812 } 1813 1814 tmp = 0; 1815 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1816 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1817 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 1818 rstate.nregs = 0; 1819 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0); 1820 1821 r600_context_pipe_state_set(rctx, &rstate); 1822} 1823 1824void r600_init_atom_start_cs(struct r600_context *rctx) 1825{ 1826 int ps_prio; 1827 int vs_prio; 1828 int gs_prio; 1829 int es_prio; 1830 int num_ps_gprs; 1831 int num_vs_gprs; 1832 int num_gs_gprs; 1833 int num_es_gprs; 1834 int num_temp_gprs; 1835 int num_ps_threads; 1836 int num_vs_threads; 1837 int num_gs_threads; 1838 int num_es_threads; 1839 int num_ps_stack_entries; 1840 int num_vs_stack_entries; 1841 int num_gs_stack_entries; 1842 int num_es_stack_entries; 1843 enum radeon_family family; 1844 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 1845 uint32_t tmp; 1846 unsigned i; 1847 1848 r600_init_command_buffer(cb, 256, EMIT_EARLY); 1849 1850 /* R6xx requires this packet at the start of each command buffer */ 1851 if (rctx->chip_class == R600) { 1852 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 1853 r600_store_value(cb, 0); 1854 } 1855 /* All asics require this one */ 1856 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 1857 r600_store_value(cb, 0x80000000); 1858 r600_store_value(cb, 0x80000000); 1859 1860 family = rctx->family; 1861 ps_prio = 0; 1862 vs_prio = 1; 1863 gs_prio = 2; 1864 es_prio = 3; 1865 switch (family) { 1866 case CHIP_R600: 1867 num_ps_gprs = 192; 1868 num_vs_gprs = 56; 1869 num_temp_gprs = 4; 1870 num_gs_gprs = 0; 1871 num_es_gprs = 0; 1872 num_ps_threads = 136; 1873 num_vs_threads = 48; 1874 num_gs_threads = 4; 1875 num_es_threads = 4; 1876 num_ps_stack_entries = 128; 1877 num_vs_stack_entries = 128; 1878 num_gs_stack_entries = 0; 1879 num_es_stack_entries = 0; 1880 break; 1881 case CHIP_RV630: 1882 case CHIP_RV635: 1883 num_ps_gprs = 84; 1884 num_vs_gprs = 36; 1885 num_temp_gprs = 4; 1886 num_gs_gprs = 0; 1887 num_es_gprs = 0; 1888 num_ps_threads = 144; 1889 num_vs_threads = 40; 1890 num_gs_threads = 4; 1891 num_es_threads = 4; 1892 num_ps_stack_entries = 40; 1893 num_vs_stack_entries = 40; 1894 num_gs_stack_entries = 32; 1895 num_es_stack_entries = 16; 1896 break; 1897 case CHIP_RV610: 1898 case CHIP_RV620: 1899 case CHIP_RS780: 1900 case CHIP_RS880: 1901 default: 1902 num_ps_gprs = 84; 1903 num_vs_gprs = 36; 1904 num_temp_gprs = 4; 1905 num_gs_gprs = 0; 1906 num_es_gprs = 0; 1907 num_ps_threads = 136; 1908 num_vs_threads = 48; 1909 num_gs_threads = 4; 1910 num_es_threads = 4; 1911 num_ps_stack_entries = 40; 1912 num_vs_stack_entries = 40; 1913 num_gs_stack_entries = 32; 1914 num_es_stack_entries = 16; 1915 break; 1916 case CHIP_RV670: 1917 num_ps_gprs = 144; 1918 num_vs_gprs = 40; 1919 num_temp_gprs = 4; 1920 num_gs_gprs = 0; 1921 num_es_gprs = 0; 1922 num_ps_threads = 136; 1923 num_vs_threads = 48; 1924 num_gs_threads = 4; 1925 num_es_threads = 4; 1926 num_ps_stack_entries = 40; 1927 num_vs_stack_entries = 40; 1928 num_gs_stack_entries = 32; 1929 num_es_stack_entries = 16; 1930 break; 1931 case CHIP_RV770: 1932 num_ps_gprs = 192; 1933 num_vs_gprs = 56; 1934 num_temp_gprs = 4; 1935 num_gs_gprs = 0; 1936 num_es_gprs = 0; 1937 num_ps_threads = 188; 1938 num_vs_threads = 60; 1939 num_gs_threads = 0; 1940 num_es_threads = 0; 1941 num_ps_stack_entries = 256; 1942 num_vs_stack_entries = 256; 1943 num_gs_stack_entries = 0; 1944 num_es_stack_entries = 0; 1945 break; 1946 case CHIP_RV730: 1947 case CHIP_RV740: 1948 num_ps_gprs = 84; 1949 num_vs_gprs = 36; 1950 num_temp_gprs = 4; 1951 num_gs_gprs = 0; 1952 num_es_gprs = 0; 1953 num_ps_threads = 188; 1954 num_vs_threads = 60; 1955 num_gs_threads = 0; 1956 num_es_threads = 0; 1957 num_ps_stack_entries = 128; 1958 num_vs_stack_entries = 128; 1959 num_gs_stack_entries = 0; 1960 num_es_stack_entries = 0; 1961 break; 1962 case CHIP_RV710: 1963 num_ps_gprs = 192; 1964 num_vs_gprs = 56; 1965 num_temp_gprs = 4; 1966 num_gs_gprs = 0; 1967 num_es_gprs = 0; 1968 num_ps_threads = 144; 1969 num_vs_threads = 48; 1970 num_gs_threads = 0; 1971 num_es_threads = 0; 1972 num_ps_stack_entries = 128; 1973 num_vs_stack_entries = 128; 1974 num_gs_stack_entries = 0; 1975 num_es_stack_entries = 0; 1976 break; 1977 } 1978 1979 rctx->default_ps_gprs = num_ps_gprs; 1980 rctx->default_vs_gprs = num_vs_gprs; 1981 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 1982 1983 /* SQ_CONFIG */ 1984 tmp = 0; 1985 switch (family) { 1986 case CHIP_RV610: 1987 case CHIP_RV620: 1988 case CHIP_RS780: 1989 case CHIP_RS880: 1990 case CHIP_RV710: 1991 break; 1992 default: 1993 tmp |= S_008C00_VC_ENABLE(1); 1994 break; 1995 } 1996 tmp |= S_008C00_DX9_CONSTS(0); 1997 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 1998 tmp |= S_008C00_PS_PRIO(ps_prio); 1999 tmp |= S_008C00_VS_PRIO(vs_prio); 2000 tmp |= S_008C00_GS_PRIO(gs_prio); 2001 tmp |= S_008C00_ES_PRIO(es_prio); 2002 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 2003 2004 /* SQ_GPR_RESOURCE_MGMT_2 */ 2005 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 2006 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 2007 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 2008 r600_store_value(cb, tmp); 2009 2010 /* SQ_THREAD_RESOURCE_MGMT */ 2011 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 2012 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 2013 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 2014 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 2015 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 2016 2017 /* SQ_STACK_RESOURCE_MGMT_1 */ 2018 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 2019 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 2020 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 2021 2022 /* SQ_STACK_RESOURCE_MGMT_2 */ 2023 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 2024 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 2025 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2026 2027 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2028 2029 if (rctx->chip_class >= R700) { 2030 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2031 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2032 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2033 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2034 } else { 2035 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2036 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2037 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2038 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2039 } 2040 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2041 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2042 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2043 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2044 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2045 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2046 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2047 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2048 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2049 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2050 2051 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2052 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2053 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2054 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2055 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2056 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2057 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2058 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2059 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2060 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2061 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2062 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2063 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2064 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2065 2066 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2067 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2068 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2069 2070 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2071 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2072 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2073 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2074 2075 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2076 2077 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2078 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2079 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2080 2081 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2082 2083 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2); 2084 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */ 2085 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */ 2086 2087 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2088 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2089 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2090 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2091 2092 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); 2093 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2094 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2095 2096 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00); 2097 2098 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2099 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2100 2101 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2); 2102 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */ 2103 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */ 2104 2105 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6); 2106 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ 2107 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ 2108 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ 2109 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ 2110 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 2111 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */ 2112 2113 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); 2114 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ 2115 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ 2116 2117 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F); 2118 2119 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8); 2120 for (i = 0; i < 8; i++) { 2121 r600_store_value(cb, 0); 2122 } 2123 2124 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2125 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2126 2127 if (rctx->chip_class >= R700) { 2128 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2129 } 2130 2131 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2132 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2133 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2134 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2135 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2136 2137 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF); 2138 2139 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2140 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2141 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2142 2143 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2144 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2145 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2146 2147 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2); 2148 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2149 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2150 2151 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2152 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0); 2153 2154 if (rctx->chip_class == R700 && rctx->screen->info.r600_has_streamout) 2155 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2156 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2157 2158 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2159 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2160} 2161 2162void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2163{ 2164 struct r600_context *rctx = (struct r600_context *)ctx; 2165 struct r600_pipe_state *rstate = &shader->rstate; 2166 struct r600_shader *rshader = &shader->shader; 2167 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2168 int pos_index = -1, face_index = -1; 2169 unsigned tmp, sid, ufi = 0; 2170 int need_linear = 0; 2171 2172 rstate->nregs = 0; 2173 2174 for (i = 0; i < rshader->ninput; i++) { 2175 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2176 pos_index = i; 2177 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2178 face_index = i; 2179 2180 sid = rshader->input[i].spi_sid; 2181 2182 tmp = S_028644_SEMANTIC(sid); 2183 2184 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2185 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2186 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2187 rctx->rasterizer && rctx->rasterizer->flatshade)) 2188 tmp |= S_028644_FLAT_SHADE(1); 2189 2190 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2191 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2192 tmp |= S_028644_PT_SPRITE_TEX(1); 2193 } 2194 2195 if (rshader->input[i].centroid) 2196 tmp |= S_028644_SEL_CENTROID(1); 2197 2198 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2199 need_linear = 1; 2200 tmp |= S_028644_SEL_LINEAR(1); 2201 } 2202 2203 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2204 tmp, NULL, 0); 2205 } 2206 2207 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2208 for (i = 0; i < rshader->noutput; i++) { 2209 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2210 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 2211 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2212 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1); 2213 } 2214 if (rshader->uses_kill) 2215 db_shader_control |= S_02880C_KILL_ENABLE(1); 2216 2217 exports_ps = 0; 2218 num_cout = 0; 2219 for (i = 0; i < rshader->noutput; i++) { 2220 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2221 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2222 exports_ps |= 1; 2223 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { 2224 num_cout++; 2225 } 2226 } 2227 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2228 if (!exports_ps) { 2229 /* always at least export 1 component per pixel */ 2230 exports_ps = 2; 2231 } 2232 2233 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2234 S_0286CC_PERSP_GRADIENT_ENA(1)| 2235 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2236 spi_input_z = 0; 2237 if (pos_index != -1) { 2238 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2239 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2240 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2241 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2242 spi_input_z |= 1; 2243 } 2244 2245 spi_ps_in_control_1 = 0; 2246 if (face_index != -1) { 2247 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2248 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2249 } 2250 2251 /* HW bug in original R600 */ 2252 if (rctx->family == CHIP_R600) 2253 ufi = 1; 2254 2255 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0); 2256 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0); 2257 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0); 2258 r600_pipe_state_add_reg(rstate, 2259 R_028840_SQ_PGM_START_PS, 2260 0, shader->bo, RADEON_USAGE_READ); 2261 r600_pipe_state_add_reg(rstate, 2262 R_028850_SQ_PGM_RESOURCES_PS, 2263 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2264 S_028850_STACK_SIZE(rshader->bc.nstack) | 2265 S_028850_UNCACHED_FIRST_INST(ufi), 2266 NULL, 0); 2267 r600_pipe_state_add_reg(rstate, 2268 R_028854_SQ_PGM_EXPORTS_PS, 2269 exports_ps, NULL, 0); 2270 /* only set some bits here, the other bits are set in the dsa state */ 2271 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, 2272 db_shader_control, 2273 NULL, 0); 2274 2275 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2276 if (rctx->rasterizer) 2277 shader->flatshade = rctx->rasterizer->flatshade; 2278} 2279 2280void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2281{ 2282 struct r600_context *rctx = (struct r600_context *)ctx; 2283 struct r600_pipe_state *rstate = &shader->rstate; 2284 struct r600_shader *rshader = &shader->shader; 2285 unsigned spi_vs_out_id[10] = {}; 2286 unsigned i, tmp, nparams = 0; 2287 2288 /* clear previous register */ 2289 rstate->nregs = 0; 2290 2291 for (i = 0; i < rshader->noutput; i++) { 2292 if (rshader->output[i].spi_sid) { 2293 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2294 spi_vs_out_id[nparams / 4] |= tmp; 2295 nparams++; 2296 } 2297 } 2298 2299 for (i = 0; i < 10; i++) { 2300 r600_pipe_state_add_reg(rstate, 2301 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2302 spi_vs_out_id[i], NULL, 0); 2303 } 2304 2305 /* Certain attributes (position, psize, etc.) don't count as params. 2306 * VS is required to export at least one param and r600_shader_from_tgsi() 2307 * takes care of adding a dummy export. 2308 */ 2309 if (nparams < 1) 2310 nparams = 1; 2311 2312 r600_pipe_state_add_reg(rstate, 2313 R_0286C4_SPI_VS_OUT_CONFIG, 2314 S_0286C4_VS_EXPORT_COUNT(nparams - 1), 2315 NULL, 0); 2316 r600_pipe_state_add_reg(rstate, 2317 R_028868_SQ_PGM_RESOURCES_VS, 2318 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2319 S_028868_STACK_SIZE(rshader->bc.nstack), 2320 NULL, 0); 2321 r600_pipe_state_add_reg(rstate, 2322 R_028858_SQ_PGM_START_VS, 2323 0, shader->bo, RADEON_USAGE_READ); 2324 2325 shader->pa_cl_vs_out_cntl = 2326 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2327 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2328 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2329 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2330} 2331 2332void r600_fetch_shader(struct pipe_context *ctx, 2333 struct r600_vertex_element *ve) 2334{ 2335 struct r600_pipe_state *rstate; 2336 struct r600_context *rctx = (struct r600_context *)ctx; 2337 2338 rstate = &ve->rstate; 2339 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2340 rstate->nregs = 0; 2341 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS, 2342 0, 2343 ve->fetch_shader, RADEON_USAGE_READ); 2344} 2345 2346void *r600_create_db_flush_dsa(struct r600_context *rctx) 2347{ 2348 struct pipe_depth_stencil_alpha_state dsa; 2349 struct r600_pipe_state *rstate; 2350 struct r600_pipe_dsa *dsa_state; 2351 boolean quirk = false; 2352 2353 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2354 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2355 quirk = true; 2356 2357 memset(&dsa, 0, sizeof(dsa)); 2358 2359 if (quirk) { 2360 dsa.depth.enabled = 1; 2361 dsa.depth.func = PIPE_FUNC_LEQUAL; 2362 dsa.stencil[0].enabled = 1; 2363 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2364 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2365 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2366 dsa.stencil[0].writemask = 0xff; 2367 } 2368 2369 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2370 dsa_state = (struct r600_pipe_dsa*)rstate; 2371 dsa_state->is_flush = true; 2372 return rstate; 2373} 2374 2375void r600_pipe_init_buffer_resource(struct r600_context *rctx, 2376 struct r600_pipe_resource_state *rstate) 2377{ 2378 rstate->id = R600_PIPE_STATE_RESOURCE; 2379 2380 rstate->bo[0] = NULL; 2381 rstate->val[0] = 0; 2382 rstate->val[1] = 0; 2383 rstate->val[2] = 0; 2384 rstate->val[3] = 0; 2385 rstate->val[4] = 0; 2386 rstate->val[5] = 0; 2387 rstate->val[6] = 0xc0000000; 2388} 2389 2390void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 2391 struct r600_resource *rbuffer, 2392 unsigned offset, unsigned stride, 2393 enum radeon_bo_usage usage) 2394{ 2395 rstate->val[0] = offset; 2396 rstate->bo[0] = rbuffer; 2397 rstate->bo_usage[0] = usage; 2398 rstate->val[1] = rbuffer->buf->size - offset - 1; 2399 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 2400 S_038008_STRIDE(stride); 2401} 2402