r600_state.c revision d6ba70c658d05033f04dd73bc40a3e2d29892121
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include <stdio.h> 27#include <util/u_inlines.h> 28#include <util/u_format.h> 29#include <util/u_memory.h> 30#include "r600_screen.h" 31#include "r600_texture.h" 32#include "r600_context.h" 33#include "r600d.h" 34 35 36static void r600_delete_state(struct pipe_context *ctx, void *state) 37{ 38 struct radeon_state *rstate = state; 39 40 radeon_state_decref(rstate); 41} 42 43static void *r600_create_blend_state(struct pipe_context *ctx, 44 const struct pipe_blend_state *state) 45{ 46 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 47 struct radeon_state *rstate; 48 49 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND); 50 if (rstate == NULL) 51 return NULL; 52 rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000; 53 rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000; 54 rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000; 55 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000; 56 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001; 57 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; 58 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; 59 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; 60 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; 61 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; 62 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; 63 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; 64 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; 65 if (radeon_state_pm4(rstate)) { 66 radeon_state_decref(rstate); 67 return NULL; 68 } 69 return rstate; 70} 71 72static void r600_bind_blend_state(struct pipe_context *ctx, void *state) 73{ 74 struct r600_context *rctx = (struct r600_context*)ctx; 75 radeon_draw_set(rctx->draw, state); 76} 77 78static void r600_set_blend_color(struct pipe_context *ctx, 79 const struct pipe_blend_color *color) 80{ 81} 82 83static void r600_set_clip_state(struct pipe_context *ctx, 84 const struct pipe_clip_state *state) 85{ 86} 87 88static void r600_set_framebuffer_state(struct pipe_context *ctx, 89 const struct pipe_framebuffer_state *state) 90{ 91 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 92 struct r600_context *rctx = (struct r600_context*)ctx; 93 struct r600_texture *rtex; 94 struct r600_buffer *rbuffer; 95 struct radeon_state *rstate; 96 unsigned level = state->cbufs[0]->level; 97 unsigned pitch, slice; 98 99 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0); 100 if (rstate == NULL) 101 return; 102 rtex = (struct r600_texture*)state->cbufs[0]->texture; 103 rbuffer = (struct r600_buffer*)rtex->buffer; 104 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 105 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 106 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 107 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 108 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 109 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; 110 rstate->nbo = 3; 111 pitch = rtex->pitch[level] / 8 - 1; 112 slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1; 113 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000; 114 rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068; 115 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | 116 S_028060_SLICE_TILE_MAX(slice); 117 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; 118 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; 119 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; 120 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; 121 if (radeon_state_pm4(rstate)) { 122 radeon_state_decref(rstate); 123 return; 124 } 125 radeon_draw_set_new(rctx->draw, rstate); 126 rctx->db = radeon_state_decref(rctx->db); 127 if(state->zsbuf) { 128 rtex = (struct r600_texture*)state->zsbuf->texture; 129 rbuffer = (struct r600_buffer*)rtex->buffer; 130 rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB); 131 if(rctx->db == NULL) 132 return; 133 rctx->db->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 134 rctx->db->nbo = 1; 135 rctx->db->placement[0] = RADEON_GEM_DOMAIN_VRAM; 136 level = state->zsbuf->level; 137 pitch = rtex->pitch[level] / 8 - 1; 138 slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1; 139 140 rctx->db->states[R600_DB__DB_DEPTH_BASE] = 0x00000000; 141 rctx->db->states[R600_DB__DB_DEPTH_INFO] = 0x00010006; 142 rctx->db->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000; 143 rctx->db->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1; 144 rctx->db->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | 145 S_028000_SLICE_TILE_MAX(slice); 146 } else 147 rctx->db = NULL; 148 rctx->fb_state = *state; 149} 150 151static void *r600_create_fs_state(struct pipe_context *ctx, 152 const struct pipe_shader_state *shader) 153{ 154 return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_FS, shader->tokens); 155} 156 157static void r600_bind_fs_state(struct pipe_context *ctx, void *state) 158{ 159 struct r600_context *rctx = (struct r600_context*)ctx; 160 161 rctx->ps_shader = state; 162} 163 164static void *r600_create_vs_state(struct pipe_context *ctx, 165 const struct pipe_shader_state *shader) 166{ 167 return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_VS, shader->tokens); 168} 169 170static void r600_bind_vs_state(struct pipe_context *ctx, void *state) 171{ 172 struct r600_context *rctx = (struct r600_context*)ctx; 173 174 rctx->vs_shader = state; 175} 176 177static void r600_set_polygon_stipple(struct pipe_context *ctx, 178 const struct pipe_poly_stipple *state) 179{ 180} 181 182static void *r600_create_rs_state(struct pipe_context *ctx, 183 const struct pipe_rasterizer_state *state) 184{ 185 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 186 struct r600_context *rctx = (struct r600_context*)ctx; 187 struct radeon_state *rstate; 188 189 rctx->flat_shade = state->flatshade; 190 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); 191 if (rstate == NULL) 192 return NULL; 193 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; 194 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000; 195 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000; 196 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000; 197 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; 198 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008; 199 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000; 200 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; 201 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; 202 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; 203 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; 204 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; 205 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; 206 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; 207 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; 208 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000; 209 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; 210 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000; 211 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000; 212 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000; 213 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000; 214 if (radeon_state_pm4(rstate)) { 215 radeon_state_decref(rstate); 216 return NULL; 217 } 218 return rstate; 219} 220 221static void r600_bind_rs_state(struct pipe_context *ctx, void *state) 222{ 223 struct r600_context *rctx = (struct r600_context*)ctx; 224 radeon_draw_set(rctx->draw, state); 225} 226 227static void *r600_create_sampler_state(struct pipe_context *ctx, 228 const struct pipe_sampler_state *state) 229{ 230 return NULL; 231} 232 233static void r600_bind_sampler_states(struct pipe_context *ctx, 234 unsigned count, void **states) 235{ 236} 237 238static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 239 struct pipe_resource *texture, 240 const struct pipe_sampler_view *templ) 241{ 242 struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view); 243 244 *view = *templ; 245 return view; 246} 247 248static void r600_sampler_view_destroy(struct pipe_context *ctx, 249 struct pipe_sampler_view *view) 250{ 251 FREE(view); 252} 253 254static void r600_set_fragment_sampler_views(struct pipe_context *ctx, 255 unsigned count, 256 struct pipe_sampler_view **views) 257{ 258} 259 260static void r600_set_vertex_sampler_views(struct pipe_context *ctx, 261 unsigned count, 262 struct pipe_sampler_view **views) 263{ 264} 265 266static void r600_set_scissor_state(struct pipe_context *ctx, 267 const struct pipe_scissor_state *state) 268{ 269 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 270 struct r600_context *rctx = (struct r600_context*)ctx; 271 struct radeon_state *rstate; 272 u32 tl, br; 273 274 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 275 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 276 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); 277 if (rstate == NULL) 278 return; 279 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; 280 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; 281 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; 282 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; 283 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; 284 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; 285 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; 286 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; 287 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; 288 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; 289 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; 290 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; 291 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; 292 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; 293 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; 294 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; 295 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; 296 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; 297 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; 298 if (radeon_state_pm4(rstate)) { 299 radeon_state_decref(rstate); 300 return; 301 } 302 radeon_draw_set_new(rctx->draw, rstate); 303} 304 305static void r600_set_viewport_state(struct pipe_context *ctx, 306 const struct pipe_viewport_state *state) 307{ 308 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 309 struct r600_context *rctx = (struct r600_context*)ctx; 310 struct radeon_state *rstate; 311 312 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); 313 if (rstate == NULL) 314 return; 315 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; 316 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; 317 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = r600_float_to_u32(state->scale[0]); 318 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = r600_float_to_u32(state->scale[1]); 319 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = r600_float_to_u32(state->scale[2]); 320 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = r600_float_to_u32(state->translate[0]); 321 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = r600_float_to_u32(state->translate[1]); 322 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = r600_float_to_u32(state->translate[2]); 323 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; 324 if (radeon_state_pm4(rstate)) { 325 radeon_state_decref(rstate); 326 return; 327 } 328 radeon_draw_set_new(rctx->draw, rstate); 329 rctx->viewport = *state; 330} 331 332static void r600_set_vertex_buffers(struct pipe_context *ctx, 333 unsigned count, 334 const struct pipe_vertex_buffer *buffers) 335{ 336 struct r600_context *rctx = (struct r600_context*)ctx; 337 338 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count); 339 rctx->nvertex_buffer = count; 340} 341 342 343static void *r600_create_vertex_elements_state(struct pipe_context *ctx, 344 unsigned count, 345 const struct pipe_vertex_element *elements) 346{ 347 struct r600_vertex_elements_state *v = CALLOC_STRUCT(r600_vertex_elements_state); 348 349 assert(count < 32); 350 v->count = count; 351 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element)); 352 return v; 353} 354 355static void r600_bind_vertex_elements_state(struct pipe_context *ctx, void *state) 356{ 357 struct r600_context *rctx = (struct r600_context*)ctx; 358 struct r600_vertex_elements_state *v = (struct r600_vertex_elements_state*)state; 359 360 rctx->vertex_elements = v; 361} 362 363static void r600_delete_vertex_elements_state(struct pipe_context *ctx, void *state) 364{ 365 FREE(state); 366} 367 368static void *r600_create_dsa_state(struct pipe_context *ctx, 369 const struct pipe_depth_stencil_alpha_state *state) 370{ 371 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 372 struct radeon_state *rstate; 373 374 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA); 375 if (rstate == NULL) 376 return NULL; 377 unsigned db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); 378 379 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; 380 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; 381 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000; 382 rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00; 383 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00; 384 rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000; 385 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; 386 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; 387 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; 388 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control; 389 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; 390 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; 391 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; 392 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; 393 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; 394 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; 395 if (radeon_state_pm4(rstate)) { 396 radeon_state_decref(rstate); 397 return NULL; 398 } 399 return rstate; 400} 401 402static void r600_bind_dsa_state(struct pipe_context *ctx, void *state) 403{ 404 struct r600_context *rctx = (struct r600_context*)ctx; 405 radeon_draw_set(rctx->draw, state); 406} 407 408static void r600_set_constant_buffer(struct pipe_context *ctx, 409 uint shader, uint index, 410 struct pipe_resource *buffer) 411{ 412 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 413 struct r600_context *rctx = (struct r600_context*)ctx; 414 unsigned nconstant = 0, i, type, id; 415 struct radeon_state *rstate; 416 struct pipe_transfer *transfer; 417 u32 *ptr; 418 419 switch (shader) { 420 case PIPE_SHADER_VERTEX: 421 id = R600_VS_CONSTANT; 422 type = R600_VS_CONSTANT_TYPE; 423 break; 424 case PIPE_SHADER_FRAGMENT: 425 id = R600_PS_CONSTANT; 426 type = R600_PS_CONSTANT_TYPE; 427 break; 428 default: 429 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader); 430 return; 431 } 432 if (buffer && buffer->width0 > 0) { 433 nconstant = buffer->width0 / 16; 434 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer); 435 if (ptr == NULL) 436 return; 437 for (i = 0; i < nconstant; i++) { 438 rstate = radeon_state(rscreen->rw, type, id + i); 439 if (rstate == NULL) 440 return; 441 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; 442 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; 443 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; 444 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; 445 if (radeon_state_pm4(rstate)) 446 return; 447 if (radeon_draw_set_new(rctx->draw, rstate)) 448 return; 449 } 450 pipe_buffer_unmap(ctx, buffer, transfer); 451 } 452} 453 454static void r600_set_stencil_ref(struct pipe_context *ctx, 455 const struct pipe_stencil_ref *sr) 456{ 457 struct r600_context *rctx = (struct r600_context*)ctx; 458 rctx->stencil_ref = *sr; 459} 460 461static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 462{ 463} 464 465void r600_init_state_functions(struct r600_context *rctx) 466{ 467 rctx->context.set_sample_mask = r600_set_sample_mask; 468 rctx->context.create_blend_state = r600_create_blend_state; 469 rctx->context.bind_blend_state = r600_bind_blend_state; 470 rctx->context.delete_blend_state = r600_delete_state; 471 rctx->context.set_blend_color = r600_set_blend_color; 472 rctx->context.set_clip_state = r600_set_clip_state; 473 rctx->context.set_constant_buffer = r600_set_constant_buffer; 474 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 475 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 476 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 477 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 478 rctx->context.create_fs_state = r600_create_fs_state; 479 rctx->context.bind_fs_state = r600_bind_fs_state; 480 rctx->context.delete_fs_state = r600_delete_state; 481 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 482 rctx->context.create_rasterizer_state = r600_create_rs_state; 483 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 484 rctx->context.delete_rasterizer_state = r600_delete_state; 485 rctx->context.create_sampler_state = r600_create_sampler_state; 486 rctx->context.bind_fragment_sampler_states = r600_bind_sampler_states; 487 rctx->context.bind_vertex_sampler_states = r600_bind_sampler_states; 488 rctx->context.delete_sampler_state = r600_delete_state; 489 rctx->context.create_sampler_view = r600_create_sampler_view; 490 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 491 rctx->context.set_fragment_sampler_views = r600_set_fragment_sampler_views; 492 rctx->context.set_vertex_sampler_views = r600_set_vertex_sampler_views; 493 rctx->context.set_scissor_state = r600_set_scissor_state; 494 rctx->context.set_viewport_state = r600_set_viewport_state; 495 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 496 rctx->context.create_vertex_elements_state = r600_create_vertex_elements_state; 497 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements_state; 498 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements_state; 499 rctx->context.create_vs_state = r600_create_vs_state; 500 rctx->context.bind_vs_state = r600_bind_vs_state; 501 rctx->context.delete_vs_state = r600_delete_state; 502 rctx->context.set_stencil_ref = r600_set_stencil_ref; 503} 504