r600_state.c revision f126253040654d52db134063a69ebaf0c417d410
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24/* TODO: 25 * - fix mask for depth control & cull for query 26 */ 27#include <stdio.h> 28#include <errno.h> 29#include "pipe/p_defines.h" 30#include "pipe/p_state.h" 31#include "pipe/p_context.h" 32#include "tgsi/tgsi_scan.h" 33#include "tgsi/tgsi_parse.h" 34#include "tgsi/tgsi_util.h" 35#include "util/u_double_list.h" 36#include "util/u_pack_color.h" 37#include "util/u_memory.h" 38#include "util/u_inlines.h" 39#include "util/u_framebuffer.h" 40#include "util/u_transfer.h" 41#include "pipebuffer/pb_buffer.h" 42#include "r600.h" 43#include "r600d.h" 44#include "r600_resource.h" 45#include "r600_shader.h" 46#include "r600_pipe.h" 47#include "r600_formats.h" 48 49static uint32_t r600_translate_blend_function(int blend_func) 50{ 51 switch (blend_func) { 52 case PIPE_BLEND_ADD: 53 return V_028804_COMB_DST_PLUS_SRC; 54 case PIPE_BLEND_SUBTRACT: 55 return V_028804_COMB_SRC_MINUS_DST; 56 case PIPE_BLEND_REVERSE_SUBTRACT: 57 return V_028804_COMB_DST_MINUS_SRC; 58 case PIPE_BLEND_MIN: 59 return V_028804_COMB_MIN_DST_SRC; 60 case PIPE_BLEND_MAX: 61 return V_028804_COMB_MAX_DST_SRC; 62 default: 63 R600_ERR("Unknown blend function %d\n", blend_func); 64 assert(0); 65 break; 66 } 67 return 0; 68} 69 70static uint32_t r600_translate_blend_factor(int blend_fact) 71{ 72 switch (blend_fact) { 73 case PIPE_BLENDFACTOR_ONE: 74 return V_028804_BLEND_ONE; 75 case PIPE_BLENDFACTOR_SRC_COLOR: 76 return V_028804_BLEND_SRC_COLOR; 77 case PIPE_BLENDFACTOR_SRC_ALPHA: 78 return V_028804_BLEND_SRC_ALPHA; 79 case PIPE_BLENDFACTOR_DST_ALPHA: 80 return V_028804_BLEND_DST_ALPHA; 81 case PIPE_BLENDFACTOR_DST_COLOR: 82 return V_028804_BLEND_DST_COLOR; 83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 84 return V_028804_BLEND_SRC_ALPHA_SATURATE; 85 case PIPE_BLENDFACTOR_CONST_COLOR: 86 return V_028804_BLEND_CONST_COLOR; 87 case PIPE_BLENDFACTOR_CONST_ALPHA: 88 return V_028804_BLEND_CONST_ALPHA; 89 case PIPE_BLENDFACTOR_ZERO: 90 return V_028804_BLEND_ZERO; 91 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 95 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 97 case PIPE_BLENDFACTOR_INV_DST_COLOR: 98 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 99 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 103 case PIPE_BLENDFACTOR_SRC1_COLOR: 104 return V_028804_BLEND_SRC1_COLOR; 105 case PIPE_BLENDFACTOR_SRC1_ALPHA: 106 return V_028804_BLEND_SRC1_ALPHA; 107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 108 return V_028804_BLEND_INV_SRC1_COLOR; 109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 110 return V_028804_BLEND_INV_SRC1_ALPHA; 111 default: 112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 113 assert(0); 114 break; 115 } 116 return 0; 117} 118 119static unsigned r600_tex_dim(unsigned dim) 120{ 121 switch (dim) { 122 default: 123 case PIPE_TEXTURE_1D: 124 return V_038000_SQ_TEX_DIM_1D; 125 case PIPE_TEXTURE_1D_ARRAY: 126 return V_038000_SQ_TEX_DIM_1D_ARRAY; 127 case PIPE_TEXTURE_2D: 128 case PIPE_TEXTURE_RECT: 129 return V_038000_SQ_TEX_DIM_2D; 130 case PIPE_TEXTURE_2D_ARRAY: 131 return V_038000_SQ_TEX_DIM_2D_ARRAY; 132 case PIPE_TEXTURE_3D: 133 return V_038000_SQ_TEX_DIM_3D; 134 case PIPE_TEXTURE_CUBE: 135 return V_038000_SQ_TEX_DIM_CUBEMAP; 136 } 137} 138 139static uint32_t r600_translate_dbformat(enum pipe_format format) 140{ 141 switch (format) { 142 case PIPE_FORMAT_Z16_UNORM: 143 return V_028010_DEPTH_16; 144 case PIPE_FORMAT_Z24X8_UNORM: 145 return V_028010_DEPTH_X8_24; 146 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 147 return V_028010_DEPTH_8_24; 148 case PIPE_FORMAT_Z32_FLOAT: 149 return V_028010_DEPTH_32_FLOAT; 150 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 151 return V_028010_DEPTH_X24_8_32_FLOAT; 152 default: 153 return ~0U; 154 } 155} 156 157static uint32_t r600_translate_colorswap(enum pipe_format format) 158{ 159 switch (format) { 160 /* 8-bit buffers. */ 161 case PIPE_FORMAT_A8_UNORM: 162 case PIPE_FORMAT_A8_UINT: 163 case PIPE_FORMAT_A8_SINT: 164 case PIPE_FORMAT_R4A4_UNORM: 165 return V_0280A0_SWAP_ALT_REV; 166 case PIPE_FORMAT_I8_UNORM: 167 case PIPE_FORMAT_L8_UNORM: 168 case PIPE_FORMAT_I8_UINT: 169 case PIPE_FORMAT_I8_SINT: 170 case PIPE_FORMAT_L8_UINT: 171 case PIPE_FORMAT_L8_SINT: 172 case PIPE_FORMAT_L8_SRGB: 173 case PIPE_FORMAT_R8_UNORM: 174 case PIPE_FORMAT_R8_SNORM: 175 case PIPE_FORMAT_R8_UINT: 176 case PIPE_FORMAT_R8_SINT: 177 return V_0280A0_SWAP_STD; 178 179 case PIPE_FORMAT_L4A4_UNORM: 180 case PIPE_FORMAT_A4R4_UNORM: 181 return V_0280A0_SWAP_ALT; 182 183 /* 16-bit buffers. */ 184 case PIPE_FORMAT_B5G6R5_UNORM: 185 return V_0280A0_SWAP_STD_REV; 186 187 case PIPE_FORMAT_B5G5R5A1_UNORM: 188 case PIPE_FORMAT_B5G5R5X1_UNORM: 189 return V_0280A0_SWAP_ALT; 190 191 case PIPE_FORMAT_B4G4R4A4_UNORM: 192 case PIPE_FORMAT_B4G4R4X4_UNORM: 193 return V_0280A0_SWAP_ALT; 194 195 case PIPE_FORMAT_Z16_UNORM: 196 return V_0280A0_SWAP_STD; 197 198 case PIPE_FORMAT_L8A8_UNORM: 199 case PIPE_FORMAT_L8A8_UINT: 200 case PIPE_FORMAT_L8A8_SINT: 201 case PIPE_FORMAT_L8A8_SRGB: 202 return V_0280A0_SWAP_ALT; 203 case PIPE_FORMAT_R8G8_UNORM: 204 case PIPE_FORMAT_R8G8_UINT: 205 case PIPE_FORMAT_R8G8_SINT: 206 return V_0280A0_SWAP_STD; 207 208 case PIPE_FORMAT_R16_UNORM: 209 case PIPE_FORMAT_R16_UINT: 210 case PIPE_FORMAT_R16_SINT: 211 case PIPE_FORMAT_R16_FLOAT: 212 return V_0280A0_SWAP_STD; 213 214 /* 32-bit buffers. */ 215 216 case PIPE_FORMAT_A8B8G8R8_SRGB: 217 return V_0280A0_SWAP_STD_REV; 218 case PIPE_FORMAT_B8G8R8A8_SRGB: 219 return V_0280A0_SWAP_ALT; 220 221 case PIPE_FORMAT_B8G8R8A8_UNORM: 222 case PIPE_FORMAT_B8G8R8X8_UNORM: 223 return V_0280A0_SWAP_ALT; 224 225 case PIPE_FORMAT_A8R8G8B8_UNORM: 226 case PIPE_FORMAT_X8R8G8B8_UNORM: 227 return V_0280A0_SWAP_ALT_REV; 228 case PIPE_FORMAT_R8G8B8A8_SNORM: 229 case PIPE_FORMAT_R8G8B8A8_UNORM: 230 case PIPE_FORMAT_R8G8B8X8_UNORM: 231 case PIPE_FORMAT_R8G8B8A8_SSCALED: 232 case PIPE_FORMAT_R8G8B8A8_USCALED: 233 case PIPE_FORMAT_R8G8B8A8_SINT: 234 case PIPE_FORMAT_R8G8B8A8_UINT: 235 return V_0280A0_SWAP_STD; 236 237 case PIPE_FORMAT_A8B8G8R8_UNORM: 238 case PIPE_FORMAT_X8B8G8R8_UNORM: 239 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 240 return V_0280A0_SWAP_STD_REV; 241 242 case PIPE_FORMAT_Z24X8_UNORM: 243 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 244 return V_0280A0_SWAP_STD; 245 246 case PIPE_FORMAT_X8Z24_UNORM: 247 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 248 return V_0280A0_SWAP_STD; 249 250 case PIPE_FORMAT_R10G10B10A2_UNORM: 251 case PIPE_FORMAT_R10G10B10X2_SNORM: 252 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 253 return V_0280A0_SWAP_STD; 254 255 case PIPE_FORMAT_B10G10R10A2_UNORM: 256 case PIPE_FORMAT_B10G10R10A2_UINT: 257 return V_0280A0_SWAP_ALT; 258 259 case PIPE_FORMAT_R11G11B10_FLOAT: 260 case PIPE_FORMAT_R16G16_UNORM: 261 case PIPE_FORMAT_R16G16_FLOAT: 262 case PIPE_FORMAT_R16G16_UINT: 263 case PIPE_FORMAT_R16G16_SINT: 264 case PIPE_FORMAT_R32_UINT: 265 case PIPE_FORMAT_R32_SINT: 266 case PIPE_FORMAT_R32_FLOAT: 267 case PIPE_FORMAT_Z32_FLOAT: 268 return V_0280A0_SWAP_STD; 269 270 /* 64-bit buffers. */ 271 case PIPE_FORMAT_R32G32_FLOAT: 272 case PIPE_FORMAT_R32G32_UINT: 273 case PIPE_FORMAT_R32G32_SINT: 274 case PIPE_FORMAT_R16G16B16A16_UNORM: 275 case PIPE_FORMAT_R16G16B16A16_SNORM: 276 case PIPE_FORMAT_R16G16B16A16_USCALED: 277 case PIPE_FORMAT_R16G16B16A16_SSCALED: 278 case PIPE_FORMAT_R16G16B16A16_UINT: 279 case PIPE_FORMAT_R16G16B16A16_SINT: 280 case PIPE_FORMAT_R16G16B16A16_FLOAT: 281 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 282 283 /* 128-bit buffers. */ 284 case PIPE_FORMAT_R32G32B32A32_FLOAT: 285 case PIPE_FORMAT_R32G32B32A32_SNORM: 286 case PIPE_FORMAT_R32G32B32A32_UNORM: 287 case PIPE_FORMAT_R32G32B32A32_USCALED: 288 case PIPE_FORMAT_R32G32B32A32_SSCALED: 289 case PIPE_FORMAT_R32G32B32A32_SINT: 290 case PIPE_FORMAT_R32G32B32A32_UINT: 291 return V_0280A0_SWAP_STD; 292 default: 293 R600_ERR("unsupported colorswap format %d\n", format); 294 return ~0U; 295 } 296 return ~0U; 297} 298 299static uint32_t r600_translate_colorformat(enum pipe_format format) 300{ 301 switch (format) { 302 case PIPE_FORMAT_L4A4_UNORM: 303 case PIPE_FORMAT_R4A4_UNORM: 304 case PIPE_FORMAT_A4R4_UNORM: 305 return V_0280A0_COLOR_4_4; 306 307 /* 8-bit buffers. */ 308 case PIPE_FORMAT_A8_UNORM: 309 case PIPE_FORMAT_A8_UINT: 310 case PIPE_FORMAT_A8_SINT: 311 case PIPE_FORMAT_I8_UNORM: 312 case PIPE_FORMAT_I8_UINT: 313 case PIPE_FORMAT_I8_SINT: 314 case PIPE_FORMAT_L8_UNORM: 315 case PIPE_FORMAT_L8_UINT: 316 case PIPE_FORMAT_L8_SINT: 317 case PIPE_FORMAT_L8_SRGB: 318 case PIPE_FORMAT_R8_UNORM: 319 case PIPE_FORMAT_R8_SNORM: 320 case PIPE_FORMAT_R8_UINT: 321 case PIPE_FORMAT_R8_SINT: 322 return V_0280A0_COLOR_8; 323 324 /* 16-bit buffers. */ 325 case PIPE_FORMAT_B5G6R5_UNORM: 326 return V_0280A0_COLOR_5_6_5; 327 328 case PIPE_FORMAT_B5G5R5A1_UNORM: 329 case PIPE_FORMAT_B5G5R5X1_UNORM: 330 return V_0280A0_COLOR_1_5_5_5; 331 332 case PIPE_FORMAT_B4G4R4A4_UNORM: 333 case PIPE_FORMAT_B4G4R4X4_UNORM: 334 return V_0280A0_COLOR_4_4_4_4; 335 336 case PIPE_FORMAT_Z16_UNORM: 337 return V_0280A0_COLOR_16; 338 339 case PIPE_FORMAT_L8A8_UNORM: 340 case PIPE_FORMAT_L8A8_UINT: 341 case PIPE_FORMAT_L8A8_SINT: 342 case PIPE_FORMAT_L8A8_SRGB: 343 case PIPE_FORMAT_R8G8_UNORM: 344 case PIPE_FORMAT_R8G8_UINT: 345 case PIPE_FORMAT_R8G8_SINT: 346 return V_0280A0_COLOR_8_8; 347 348 case PIPE_FORMAT_R16_UNORM: 349 case PIPE_FORMAT_R16_UINT: 350 case PIPE_FORMAT_R16_SINT: 351 return V_0280A0_COLOR_16; 352 353 case PIPE_FORMAT_R16_FLOAT: 354 return V_0280A0_COLOR_16_FLOAT; 355 356 /* 32-bit buffers. */ 357 case PIPE_FORMAT_A8B8G8R8_SRGB: 358 case PIPE_FORMAT_A8B8G8R8_UNORM: 359 case PIPE_FORMAT_A8R8G8B8_UNORM: 360 case PIPE_FORMAT_B8G8R8A8_SRGB: 361 case PIPE_FORMAT_B8G8R8A8_UNORM: 362 case PIPE_FORMAT_B8G8R8X8_UNORM: 363 case PIPE_FORMAT_R8G8B8A8_SNORM: 364 case PIPE_FORMAT_R8G8B8A8_UNORM: 365 case PIPE_FORMAT_R8G8B8A8_SSCALED: 366 case PIPE_FORMAT_R8G8B8A8_USCALED: 367 case PIPE_FORMAT_R8G8B8X8_UNORM: 368 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 369 case PIPE_FORMAT_X8B8G8R8_UNORM: 370 case PIPE_FORMAT_X8R8G8B8_UNORM: 371 case PIPE_FORMAT_R8G8B8_UNORM: 372 case PIPE_FORMAT_R8G8B8A8_SINT: 373 case PIPE_FORMAT_R8G8B8A8_UINT: 374 return V_0280A0_COLOR_8_8_8_8; 375 376 case PIPE_FORMAT_R10G10B10A2_UNORM: 377 case PIPE_FORMAT_R10G10B10X2_SNORM: 378 case PIPE_FORMAT_B10G10R10A2_UNORM: 379 case PIPE_FORMAT_B10G10R10A2_UINT: 380 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 381 return V_0280A0_COLOR_2_10_10_10; 382 383 case PIPE_FORMAT_Z24X8_UNORM: 384 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 385 return V_0280A0_COLOR_8_24; 386 387 case PIPE_FORMAT_X8Z24_UNORM: 388 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 389 return V_0280A0_COLOR_24_8; 390 391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 392 return V_0280A0_COLOR_X24_8_32_FLOAT; 393 394 case PIPE_FORMAT_R32_UINT: 395 case PIPE_FORMAT_R32_SINT: 396 return V_0280A0_COLOR_32; 397 398 case PIPE_FORMAT_R32_FLOAT: 399 case PIPE_FORMAT_Z32_FLOAT: 400 return V_0280A0_COLOR_32_FLOAT; 401 402 case PIPE_FORMAT_R16G16_FLOAT: 403 return V_0280A0_COLOR_16_16_FLOAT; 404 405 case PIPE_FORMAT_R16G16_SSCALED: 406 case PIPE_FORMAT_R16G16_UNORM: 407 case PIPE_FORMAT_R16G16_UINT: 408 case PIPE_FORMAT_R16G16_SINT: 409 return V_0280A0_COLOR_16_16; 410 411 case PIPE_FORMAT_R11G11B10_FLOAT: 412 return V_0280A0_COLOR_10_11_11_FLOAT; 413 414 /* 64-bit buffers. */ 415 case PIPE_FORMAT_R16G16B16_USCALED: 416 case PIPE_FORMAT_R16G16B16A16_USCALED: 417 case PIPE_FORMAT_R16G16B16_SSCALED: 418 case PIPE_FORMAT_R16G16B16A16_UINT: 419 case PIPE_FORMAT_R16G16B16A16_SINT: 420 case PIPE_FORMAT_R16G16B16A16_SSCALED: 421 case PIPE_FORMAT_R16G16B16A16_UNORM: 422 case PIPE_FORMAT_R16G16B16A16_SNORM: 423 return V_0280A0_COLOR_16_16_16_16; 424 425 case PIPE_FORMAT_R16G16B16_FLOAT: 426 case PIPE_FORMAT_R16G16B16A16_FLOAT: 427 return V_0280A0_COLOR_16_16_16_16_FLOAT; 428 429 case PIPE_FORMAT_R32G32_FLOAT: 430 return V_0280A0_COLOR_32_32_FLOAT; 431 432 case PIPE_FORMAT_R32G32_USCALED: 433 case PIPE_FORMAT_R32G32_SSCALED: 434 case PIPE_FORMAT_R32G32_SINT: 435 case PIPE_FORMAT_R32G32_UINT: 436 return V_0280A0_COLOR_32_32; 437 438 /* 96-bit buffers. */ 439 case PIPE_FORMAT_R32G32B32_FLOAT: 440 return V_0280A0_COLOR_32_32_32_FLOAT; 441 442 /* 128-bit buffers. */ 443 case PIPE_FORMAT_R32G32B32A32_FLOAT: 444 return V_0280A0_COLOR_32_32_32_32_FLOAT; 445 case PIPE_FORMAT_R32G32B32A32_SNORM: 446 case PIPE_FORMAT_R32G32B32A32_UNORM: 447 case PIPE_FORMAT_R32G32B32A32_SSCALED: 448 case PIPE_FORMAT_R32G32B32A32_USCALED: 449 case PIPE_FORMAT_R32G32B32A32_SINT: 450 case PIPE_FORMAT_R32G32B32A32_UINT: 451 return V_0280A0_COLOR_32_32_32_32; 452 453 /* YUV buffers. */ 454 case PIPE_FORMAT_UYVY: 455 case PIPE_FORMAT_YUYV: 456 default: 457 return ~0U; /* Unsupported. */ 458 } 459} 460 461static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 462{ 463 if (R600_BIG_ENDIAN) { 464 switch(colorformat) { 465 case V_0280A0_COLOR_4_4: 466 return ENDIAN_NONE; 467 468 /* 8-bit buffers. */ 469 case V_0280A0_COLOR_8: 470 return ENDIAN_NONE; 471 472 /* 16-bit buffers. */ 473 case V_0280A0_COLOR_5_6_5: 474 case V_0280A0_COLOR_1_5_5_5: 475 case V_0280A0_COLOR_4_4_4_4: 476 case V_0280A0_COLOR_16: 477 case V_0280A0_COLOR_8_8: 478 return ENDIAN_8IN16; 479 480 /* 32-bit buffers. */ 481 case V_0280A0_COLOR_8_8_8_8: 482 case V_0280A0_COLOR_2_10_10_10: 483 case V_0280A0_COLOR_8_24: 484 case V_0280A0_COLOR_24_8: 485 case V_0280A0_COLOR_32_FLOAT: 486 case V_0280A0_COLOR_16_16_FLOAT: 487 case V_0280A0_COLOR_16_16: 488 return ENDIAN_8IN32; 489 490 /* 64-bit buffers. */ 491 case V_0280A0_COLOR_16_16_16_16: 492 case V_0280A0_COLOR_16_16_16_16_FLOAT: 493 return ENDIAN_8IN16; 494 495 case V_0280A0_COLOR_32_32_FLOAT: 496 case V_0280A0_COLOR_32_32: 497 case V_0280A0_COLOR_X24_8_32_FLOAT: 498 return ENDIAN_8IN32; 499 500 /* 128-bit buffers. */ 501 case V_0280A0_COLOR_32_32_32_FLOAT: 502 case V_0280A0_COLOR_32_32_32_32_FLOAT: 503 case V_0280A0_COLOR_32_32_32_32: 504 return ENDIAN_8IN32; 505 default: 506 return ENDIAN_NONE; /* Unsupported. */ 507 } 508 } else { 509 return ENDIAN_NONE; 510 } 511} 512 513static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 514{ 515 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 516} 517 518static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 519{ 520 return r600_translate_colorformat(format) != ~0U && 521 r600_translate_colorswap(format) != ~0U; 522} 523 524static bool r600_is_zs_format_supported(enum pipe_format format) 525{ 526 return r600_translate_dbformat(format) != ~0U; 527} 528 529boolean r600_is_format_supported(struct pipe_screen *screen, 530 enum pipe_format format, 531 enum pipe_texture_target target, 532 unsigned sample_count, 533 unsigned usage) 534{ 535 unsigned retval = 0; 536 537 if (target >= PIPE_MAX_TEXTURE_TYPES) { 538 R600_ERR("r600: unsupported texture type %d\n", target); 539 return FALSE; 540 } 541 542 if (!util_format_is_supported(format, usage)) 543 return FALSE; 544 545 /* Multisample */ 546 if (sample_count > 1) 547 return FALSE; 548 549 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 550 r600_is_sampler_format_supported(screen, format)) { 551 retval |= PIPE_BIND_SAMPLER_VIEW; 552 } 553 554 if ((usage & (PIPE_BIND_RENDER_TARGET | 555 PIPE_BIND_DISPLAY_TARGET | 556 PIPE_BIND_SCANOUT | 557 PIPE_BIND_SHARED)) && 558 r600_is_colorbuffer_format_supported(format)) { 559 retval |= usage & 560 (PIPE_BIND_RENDER_TARGET | 561 PIPE_BIND_DISPLAY_TARGET | 562 PIPE_BIND_SCANOUT | 563 PIPE_BIND_SHARED); 564 } 565 566 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 567 r600_is_zs_format_supported(format)) { 568 retval |= PIPE_BIND_DEPTH_STENCIL; 569 } 570 571 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 572 r600_is_vertex_format_supported(format)) { 573 retval |= PIPE_BIND_VERTEX_BUFFER; 574 } 575 576 if (usage & PIPE_BIND_TRANSFER_READ) 577 retval |= PIPE_BIND_TRANSFER_READ; 578 if (usage & PIPE_BIND_TRANSFER_WRITE) 579 retval |= PIPE_BIND_TRANSFER_WRITE; 580 581 return retval == usage; 582} 583 584void r600_polygon_offset_update(struct r600_context *rctx) 585{ 586 struct r600_pipe_state state; 587 588 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 589 state.nregs = 0; 590 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 591 float offset_units = rctx->rasterizer->offset_units; 592 unsigned offset_db_fmt_cntl = 0, depth; 593 594 switch (rctx->framebuffer.zsbuf->texture->format) { 595 case PIPE_FORMAT_Z24X8_UNORM: 596 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 597 depth = -24; 598 offset_units *= 2.0f; 599 break; 600 case PIPE_FORMAT_Z32_FLOAT: 601 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 602 depth = -23; 603 offset_units *= 1.0f; 604 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 605 break; 606 case PIPE_FORMAT_Z16_UNORM: 607 depth = -16; 608 offset_units *= 4.0f; 609 break; 610 default: 611 return; 612 } 613 /* FIXME some of those reg can be computed with cso */ 614 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 615 r600_pipe_state_add_reg(&state, 616 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 617 fui(rctx->rasterizer->offset_scale), NULL, 0); 618 r600_pipe_state_add_reg(&state, 619 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 620 fui(offset_units), NULL, 0); 621 r600_pipe_state_add_reg(&state, 622 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 623 fui(rctx->rasterizer->offset_scale), NULL, 0); 624 r600_pipe_state_add_reg(&state, 625 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 626 fui(offset_units), NULL, 0); 627 r600_pipe_state_add_reg(&state, 628 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 629 offset_db_fmt_cntl, NULL, 0); 630 r600_context_pipe_state_set(rctx, &state); 631 } 632} 633 634static void *r600_create_blend_state(struct pipe_context *ctx, 635 const struct pipe_blend_state *state) 636{ 637 struct r600_context *rctx = (struct r600_context *)ctx; 638 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 639 struct r600_pipe_state *rstate; 640 uint32_t color_control = 0, target_mask; 641 642 if (blend == NULL) { 643 return NULL; 644 } 645 rstate = &blend->rstate; 646 647 rstate->id = R600_PIPE_STATE_BLEND; 648 649 target_mask = 0; 650 651 /* R600 does not support per-MRT blends */ 652 if (rctx->family > CHIP_R600) 653 color_control |= S_028808_PER_MRT_BLEND(1); 654 if (state->logicop_enable) { 655 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 656 } else { 657 color_control |= (0xcc << 16); 658 } 659 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 660 if (state->independent_blend_enable) { 661 for (int i = 0; i < 8; i++) { 662 if (state->rt[i].blend_enable) { 663 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 664 } 665 target_mask |= (state->rt[i].colormask << (4 * i)); 666 } 667 } else { 668 for (int i = 0; i < 8; i++) { 669 if (state->rt[0].blend_enable) { 670 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 671 } 672 target_mask |= (state->rt[0].colormask << (4 * i)); 673 } 674 } 675 blend->cb_target_mask = target_mask; 676 blend->cb_color_control = color_control; 677 678 for (int i = 0; i < 8; i++) { 679 /* state->rt entries > 0 only written if independent blending */ 680 const int j = state->independent_blend_enable ? i : 0; 681 682 unsigned eqRGB = state->rt[j].rgb_func; 683 unsigned srcRGB = state->rt[j].rgb_src_factor; 684 unsigned dstRGB = state->rt[j].rgb_dst_factor; 685 686 unsigned eqA = state->rt[j].alpha_func; 687 unsigned srcA = state->rt[j].alpha_src_factor; 688 unsigned dstA = state->rt[j].alpha_dst_factor; 689 uint32_t bc = 0; 690 691 if (!state->rt[j].blend_enable) 692 continue; 693 694 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 695 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 696 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 697 698 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 699 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 700 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 701 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 702 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 703 } 704 705 /* R600 does not support per-MRT blends */ 706 if (rctx->family > CHIP_R600) 707 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0); 708 if (i == 0) 709 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0); 710 } 711 return rstate; 712} 713 714static void *r600_create_dsa_state(struct pipe_context *ctx, 715 const struct pipe_depth_stencil_alpha_state *state) 716{ 717 struct r600_context *rctx = (struct r600_context *)ctx; 718 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 719 unsigned db_depth_control, alpha_test_control, alpha_ref; 720 unsigned db_render_override, db_render_control; 721 struct r600_pipe_state *rstate; 722 723 if (dsa == NULL) { 724 return NULL; 725 } 726 727 dsa->valuemask[0] = state->stencil[0].valuemask; 728 dsa->valuemask[1] = state->stencil[1].valuemask; 729 dsa->writemask[0] = state->stencil[0].writemask; 730 dsa->writemask[1] = state->stencil[1].writemask; 731 732 rstate = &dsa->rstate; 733 734 rstate->id = R600_PIPE_STATE_DSA; 735 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 736 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 737 S_028800_ZFUNC(state->depth.func); 738 739 /* stencil */ 740 if (state->stencil[0].enabled) { 741 db_depth_control |= S_028800_STENCIL_ENABLE(1); 742 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 743 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 744 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 745 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 746 747 if (state->stencil[1].enabled) { 748 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 749 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 750 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 751 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 752 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 753 } 754 } 755 756 /* alpha */ 757 alpha_test_control = 0; 758 alpha_ref = 0; 759 if (state->alpha.enabled) { 760 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 761 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 762 alpha_ref = fui(state->alpha.ref_value); 763 } 764 dsa->alpha_ref = alpha_ref; 765 766 /* misc */ 767 db_render_control = 0; 768 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 769 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 770 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 771 /* TODO db_render_override depends on query */ 772 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0); 773 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0); 774 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0); 775 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, NULL, 0); 776 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, NULL, 0); 777 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0); 778 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0); 779 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0); 780 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, NULL, 0); 781 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, NULL, 0); 782 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, NULL, 0); 783 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0); 784 785 dsa->db_render_override = db_render_override; 786 dsa->db_render_control = db_render_control; 787 788 return rstate; 789} 790 791static void *r600_create_rs_state(struct pipe_context *ctx, 792 const struct pipe_rasterizer_state *state) 793{ 794 struct r600_context *rctx = (struct r600_context *)ctx; 795 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 796 struct r600_pipe_state *rstate; 797 unsigned tmp; 798 unsigned prov_vtx = 1, polygon_dual_mode; 799 unsigned clip_rule; 800 unsigned sc_mode_cntl; 801 float psize_min, psize_max; 802 803 if (rs == NULL) { 804 return NULL; 805 } 806 807 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 808 state->fill_back != PIPE_POLYGON_MODE_FILL); 809 810 if (state->flatshade_first) 811 prov_vtx = 0; 812 813 rstate = &rs->rstate; 814 rs->flatshade = state->flatshade; 815 rs->sprite_coord_enable = state->sprite_coord_enable; 816 rs->two_side = state->light_twoside; 817 rs->clip_plane_enable = state->clip_plane_enable; 818 rs->pa_sc_line_stipple = state->line_stipple_enable ? 819 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 820 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 821 rs->pa_cl_clip_cntl = 822 S_028810_PS_UCP_MODE(3) | 823 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 824 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 825 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 826 827 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 828 /* offset */ 829 rs->offset_units = state->offset_units; 830 rs->offset_scale = state->offset_scale * 12.0f; 831 832 rstate->id = R600_PIPE_STATE_RASTERIZER; 833 tmp = S_0286D4_FLAT_SHADE_ENA(1); 834 if (state->sprite_coord_enable) { 835 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 836 S_0286D4_PNT_SPRITE_OVRD_X(2) | 837 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 838 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 839 S_0286D4_PNT_SPRITE_OVRD_W(1); 840 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 841 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 842 } 843 } 844 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0); 845 846 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0); 847 /* point size 12.4 fixed point */ 848 tmp = (unsigned)(state->point_size * 8.0); 849 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0); 850 851 if (state->point_size_per_vertex) { 852 psize_min = util_get_min_point_size(state); 853 psize_max = 8192; 854 } else { 855 /* Force the point size to be as if the vertex output was disabled. */ 856 psize_min = state->point_size; 857 psize_max = state->point_size; 858 } 859 /* Divide by two, because 0.5 = 1 pixel. */ 860 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 861 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 862 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)), 863 NULL, 0); 864 865 tmp = (unsigned)state->line_width * 8; 866 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0); 867 868 if (rctx->chip_class >= R700) 869 sc_mode_cntl = 0x514002; 870 else 871 sc_mode_cntl = 0x4102; 872 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 873 874 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl, 875 NULL, 0); 876 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, NULL, 0); 877 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0); 878 879 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 880 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 881 NULL, 0); 882 883 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0); 884 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0); 885 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0); 886 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0); 887 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0); 888 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0); 889 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 890 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 891 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 892 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 893 S_028814_FACE(!state->front_ccw) | 894 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 895 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 896 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 897 S_028814_POLY_MODE(polygon_dual_mode) | 898 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 899 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 900 NULL, 0); 901 return rstate; 902} 903 904static void *r600_create_sampler_state(struct pipe_context *ctx, 905 const struct pipe_sampler_state *state) 906{ 907 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 908 struct r600_pipe_state *rstate; 909 union util_color uc; 910 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 911 912 if (ss == NULL) { 913 return NULL; 914 } 915 916 ss->seamless_cube_map = state->seamless_cube_map; 917 rstate = &ss->rstate; 918 rstate->id = R600_PIPE_STATE_SAMPLER; 919 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 920 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 921 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 922 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 923 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 924 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 925 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 926 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 927 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 928 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 929 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0); 930 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 931 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 932 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 933 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0); 934 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0); 935 if (uc.ui) { 936 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0); 937 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0); 938 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0); 939 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0); 940 } 941 return rstate; 942} 943 944static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 945 struct pipe_resource *texture, 946 const struct pipe_sampler_view *state) 947{ 948 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 949 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 950 struct r600_pipe_resource_state *rstate; 951 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 952 unsigned format, endian; 953 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 954 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 955 unsigned width, height, depth, offset_level, last_level; 956 957 if (view == NULL) 958 return NULL; 959 rstate = &view->state; 960 961 /* initialize base object */ 962 view->base = *state; 963 view->base.texture = NULL; 964 pipe_reference(NULL, &texture->reference); 965 view->base.texture = texture; 966 view->base.reference.count = 1; 967 view->base.context = ctx; 968 969 swizzle[0] = state->swizzle_r; 970 swizzle[1] = state->swizzle_g; 971 swizzle[2] = state->swizzle_b; 972 swizzle[3] = state->swizzle_a; 973 974 format = r600_translate_texformat(ctx->screen, state->format, 975 swizzle, 976 &word4, &yuv_format); 977 if (format == ~0) { 978 format = 0; 979 } 980 981 if (tmp->depth && !tmp->is_flushing_texture) { 982 r600_texture_depth_flush(ctx, texture, TRUE); 983 tmp = tmp->flushed_depth_texture; 984 } 985 986 endian = r600_colorformat_endian_swap(format); 987 988 offset_level = state->u.tex.first_level; 989 last_level = state->u.tex.last_level - offset_level; 990 if (!rscreen->use_surface) { 991 width = u_minify(texture->width0, offset_level); 992 height = u_minify(texture->height0, offset_level); 993 depth = u_minify(texture->depth0, offset_level); 994 995 pitch = align(tmp->pitch_in_blocks[offset_level] * 996 util_format_get_blockwidth(state->format), 8); 997 array_mode = tmp->array_mode[offset_level]; 998 tile_type = tmp->tile_type; 999 1000 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1001 height = 1; 1002 depth = texture->array_size; 1003 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1004 depth = texture->array_size; 1005 } 1006 1007 rstate->bo[0] = &tmp->resource; 1008 rstate->bo[1] = &tmp->resource; 1009 rstate->bo_usage[0] = RADEON_USAGE_READ; 1010 rstate->bo_usage[1] = RADEON_USAGE_READ; 1011 1012 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1013 S_038000_TILE_MODE(array_mode) | 1014 S_038000_TILE_TYPE(tile_type) | 1015 S_038000_PITCH((pitch / 8) - 1) | 1016 S_038000_TEX_WIDTH(width - 1)); 1017 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1018 S_038004_TEX_DEPTH(depth - 1) | 1019 S_038004_DATA_FORMAT(format)); 1020 rstate->val[2] = tmp->offset[offset_level] >> 8; 1021 rstate->val[3] = tmp->offset[offset_level+1] >> 8; 1022 rstate->val[4] = (word4 | 1023 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1024 S_038010_REQUEST_SIZE(1) | 1025 S_038010_ENDIAN_SWAP(endian) | 1026 S_038010_BASE_LEVEL(0)); 1027 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1028 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1029 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1030 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1031 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1032 } else { 1033 width = tmp->surface.level[offset_level].npix_x; 1034 height = tmp->surface.level[offset_level].npix_y; 1035 depth = tmp->surface.level[offset_level].npix_z; 1036 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1037 tile_type = tmp->tile_type; 1038 1039 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1040 height = 1; 1041 depth = texture->array_size; 1042 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1043 depth = texture->array_size; 1044 } 1045 switch (tmp->surface.level[offset_level].mode) { 1046 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1047 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1048 break; 1049 case RADEON_SURF_MODE_1D: 1050 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1051 break; 1052 case RADEON_SURF_MODE_2D: 1053 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1054 break; 1055 case RADEON_SURF_MODE_LINEAR: 1056 default: 1057 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1058 break; 1059 } 1060 1061 rstate->bo[0] = &tmp->resource; 1062 rstate->bo[1] = &tmp->resource; 1063 rstate->bo_usage[0] = RADEON_USAGE_READ; 1064 rstate->bo_usage[1] = RADEON_USAGE_READ; 1065 1066 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1067 S_038000_TILE_MODE(array_mode) | 1068 S_038000_TILE_TYPE(tile_type) | 1069 S_038000_PITCH((pitch / 8) - 1) | 1070 S_038000_TEX_WIDTH(width - 1)); 1071 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1072 S_038004_TEX_DEPTH(depth - 1) | 1073 S_038004_DATA_FORMAT(format)); 1074 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8; 1075 if (offset_level >= tmp->surface.last_level) { 1076 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8; 1077 } else { 1078 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1079 } 1080 rstate->val[4] = (word4 | 1081 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1082 S_038010_REQUEST_SIZE(1) | 1083 S_038010_ENDIAN_SWAP(endian) | 1084 S_038010_BASE_LEVEL(0)); 1085 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1086 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1087 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1088 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1089 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1090 } 1091 return &view->base; 1092} 1093 1094static void r600_set_sampler_views(struct r600_context *rctx, 1095 struct r600_textures_info *dst, 1096 unsigned count, 1097 struct pipe_sampler_view **views, 1098 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned)) 1099{ 1100 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 1101 unsigned i; 1102 1103 if (count) 1104 r600_inval_texture_cache(rctx); 1105 1106 for (i = 0; i < count; i++) { 1107 if (rviews[i]) { 1108 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth) 1109 rctx->have_depth_texture = true; 1110 1111 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */ 1112 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1113 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) 1114 dst->samplers_dirty = true; 1115 1116 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS); 1117 } else { 1118 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1119 } 1120 1121 pipe_sampler_view_reference( 1122 (struct pipe_sampler_view **)&dst->views[i], 1123 views[i]); 1124 } 1125 1126 for (i = count; i < dst->n_views; i++) { 1127 if (dst->views[i]) { 1128 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1129 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL); 1130 } 1131 } 1132 1133 dst->n_views = count; 1134} 1135 1136static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1137 struct pipe_sampler_view **views) 1138{ 1139 struct r600_context *rctx = (struct r600_context *)ctx; 1140 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views, 1141 r600_context_pipe_state_set_vs_resource); 1142} 1143 1144static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1145 struct pipe_sampler_view **views) 1146{ 1147 struct r600_context *rctx = (struct r600_context *)ctx; 1148 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views, 1149 r600_context_pipe_state_set_ps_resource); 1150} 1151 1152static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable) 1153{ 1154 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1155 if (rstate == NULL) 1156 return; 1157 1158 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP; 1159 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 1160 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) | 1161 S_009508_DISABLE_CUBE_ANISO(1) | 1162 S_009508_SYNC_GRADIENT(1) | 1163 S_009508_SYNC_WALKER(1) | 1164 S_009508_SYNC_ALIGNER(1), 1165 NULL, 0); 1166 1167 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]); 1168 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate; 1169 r600_context_pipe_state_set(rctx, rstate); 1170} 1171 1172static void r600_bind_samplers(struct r600_context *rctx, 1173 struct r600_textures_info *dst, 1174 unsigned count, void **states) 1175{ 1176 memcpy(dst->samplers, states, sizeof(void*) * count); 1177 dst->n_samplers = count; 1178 dst->samplers_dirty = true; 1179} 1180 1181static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 1182{ 1183 struct r600_context *rctx = (struct r600_context *)ctx; 1184 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states); 1185} 1186 1187static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 1188{ 1189 struct r600_context *rctx = (struct r600_context *)ctx; 1190 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states); 1191} 1192 1193static void r600_update_samplers(struct r600_context *rctx, 1194 struct r600_textures_info *tex, 1195 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned)) 1196{ 1197 unsigned i; 1198 1199 if (tex->samplers_dirty) { 1200 int seamless = -1; 1201 for (i = 0; i < tex->n_samplers; i++) { 1202 if (!tex->samplers[i]) 1203 continue; 1204 1205 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1206 * filtering between layers. 1207 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */ 1208 if (tex->views[i]) { 1209 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1210 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1211 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1212 tex->is_array_sampler[i] = true; 1213 } else { 1214 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE; 1215 tex->is_array_sampler[i] = false; 1216 } 1217 } 1218 1219 set_sampler(rctx, &tex->samplers[i]->rstate, i); 1220 1221 if (tex->samplers[i]) 1222 seamless = tex->samplers[i]->seamless_cube_map; 1223 } 1224 1225 if (seamless != -1) 1226 r600_set_seamless_cubemap(rctx, seamless); 1227 1228 tex->samplers_dirty = false; 1229 } 1230} 1231 1232void r600_update_sampler_states(struct r600_context *rctx) 1233{ 1234 r600_update_samplers(rctx, &rctx->vs_samplers, 1235 r600_context_pipe_state_set_vs_sampler); 1236 r600_update_samplers(rctx, &rctx->ps_samplers, 1237 r600_context_pipe_state_set_ps_sampler); 1238} 1239 1240static void r600_set_clip_state(struct pipe_context *ctx, 1241 const struct pipe_clip_state *state) 1242{ 1243 struct r600_context *rctx = (struct r600_context *)ctx; 1244 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1245 struct pipe_resource * cbuf; 1246 1247 if (rstate == NULL) 1248 return; 1249 1250 rctx->clip = *state; 1251 rstate->id = R600_PIPE_STATE_CLIP; 1252 for (int i = 0; i < 6; i++) { 1253 r600_pipe_state_add_reg(rstate, 1254 R_028E20_PA_CL_UCP0_X + i * 16, 1255 fui(state->ucp[i][0]), NULL, 0); 1256 r600_pipe_state_add_reg(rstate, 1257 R_028E24_PA_CL_UCP0_Y + i * 16, 1258 fui(state->ucp[i][1]) , NULL, 0); 1259 r600_pipe_state_add_reg(rstate, 1260 R_028E28_PA_CL_UCP0_Z + i * 16, 1261 fui(state->ucp[i][2]), NULL, 0); 1262 r600_pipe_state_add_reg(rstate, 1263 R_028E2C_PA_CL_UCP0_W + i * 16, 1264 fui(state->ucp[i][3]), NULL, 0); 1265 } 1266 1267 free(rctx->states[R600_PIPE_STATE_CLIP]); 1268 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1269 r600_context_pipe_state_set(rctx, rstate); 1270 1271 cbuf = pipe_user_buffer_create(ctx->screen, 1272 state->ucp, 1273 4*4*8, /* 8*4 floats */ 1274 PIPE_BIND_CONSTANT_BUFFER); 1275 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf); 1276 pipe_resource_reference(&cbuf, NULL); 1277} 1278 1279static void r600_set_polygon_stipple(struct pipe_context *ctx, 1280 const struct pipe_poly_stipple *state) 1281{ 1282} 1283 1284static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1285{ 1286} 1287 1288static void r600_set_scissor_state(struct pipe_context *ctx, 1289 const struct pipe_scissor_state *state) 1290{ 1291 struct r600_context *rctx = (struct r600_context *)ctx; 1292 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1293 uint32_t tl, br; 1294 1295 if (rstate == NULL) 1296 return; 1297 1298 rstate->id = R600_PIPE_STATE_SCISSOR; 1299 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1300 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1301 r600_pipe_state_add_reg(rstate, 1302 R_028210_PA_SC_CLIPRECT_0_TL, tl, 1303 NULL, 0); 1304 r600_pipe_state_add_reg(rstate, 1305 R_028214_PA_SC_CLIPRECT_0_BR, br, 1306 NULL, 0); 1307 r600_pipe_state_add_reg(rstate, 1308 R_028218_PA_SC_CLIPRECT_1_TL, tl, 1309 NULL, 0); 1310 r600_pipe_state_add_reg(rstate, 1311 R_02821C_PA_SC_CLIPRECT_1_BR, br, 1312 NULL, 0); 1313 r600_pipe_state_add_reg(rstate, 1314 R_028220_PA_SC_CLIPRECT_2_TL, tl, 1315 NULL, 0); 1316 r600_pipe_state_add_reg(rstate, 1317 R_028224_PA_SC_CLIPRECT_2_BR, br, 1318 NULL, 0); 1319 r600_pipe_state_add_reg(rstate, 1320 R_028228_PA_SC_CLIPRECT_3_TL, tl, 1321 NULL, 0); 1322 r600_pipe_state_add_reg(rstate, 1323 R_02822C_PA_SC_CLIPRECT_3_BR, br, 1324 NULL, 0); 1325 1326 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1327 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1328 r600_context_pipe_state_set(rctx, rstate); 1329} 1330 1331static void r600_set_viewport_state(struct pipe_context *ctx, 1332 const struct pipe_viewport_state *state) 1333{ 1334 struct r600_context *rctx = (struct r600_context *)ctx; 1335 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1336 1337 if (rstate == NULL) 1338 return; 1339 1340 rctx->viewport = *state; 1341 rstate->id = R600_PIPE_STATE_VIEWPORT; 1342 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0); 1343 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0); 1344 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0); 1345 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0); 1346 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0); 1347 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0); 1348 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0); 1349 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0); 1350 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0); 1351 1352 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1353 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1354 r600_context_pipe_state_set(rctx, rstate); 1355} 1356 1357static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 1358 const struct pipe_framebuffer_state *state, int cb) 1359{ 1360 struct r600_screen *rscreen = rctx->screen; 1361 struct r600_resource_texture *rtex; 1362 struct r600_surface *surf; 1363 unsigned level = state->cbufs[cb]->u.tex.level; 1364 unsigned pitch, slice; 1365 unsigned color_info; 1366 unsigned format, swap, ntype, endian; 1367 unsigned offset; 1368 const struct util_format_description *desc; 1369 int i; 1370 unsigned blend_bypass = 0, blend_clamp = 1; 1371 1372 surf = (struct r600_surface *)state->cbufs[cb]; 1373 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1374 1375 if (rtex->depth) 1376 rctx->have_depth_fb = TRUE; 1377 1378 if (rtex->depth && !rtex->is_flushing_texture) { 1379 rtex = rtex->flushed_depth_texture; 1380 } 1381 1382 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1383 if (!rscreen->use_surface) { 1384 offset = r600_texture_get_offset(rtex, 1385 level, state->cbufs[cb]->u.tex.first_layer); 1386 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1387 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1388 if (slice) { 1389 slice = slice - 1; 1390 } 1391 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]); 1392 } else { 1393 offset = rtex->surface.level[level].offset; 1394 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1395 offset += rtex->surface.level[level].slice_size * 1396 state->cbufs[cb]->u.tex.first_layer; 1397 } 1398 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1399 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1400 if (slice) { 1401 slice = slice - 1; 1402 } 1403 color_info = 0; 1404 switch (rtex->surface.level[level].mode) { 1405 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1406 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1407 break; 1408 case RADEON_SURF_MODE_1D: 1409 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1410 break; 1411 case RADEON_SURF_MODE_2D: 1412 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1413 break; 1414 case RADEON_SURF_MODE_LINEAR: 1415 default: 1416 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1417 break; 1418 } 1419 } 1420 desc = util_format_description(surf->base.format); 1421 1422 for (i = 0; i < 4; i++) { 1423 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1424 break; 1425 } 1426 } 1427 1428 ntype = V_0280A0_NUMBER_UNORM; 1429 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1430 ntype = V_0280A0_NUMBER_SRGB; 1431 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1432 if (desc->channel[i].normalized) 1433 ntype = V_0280A0_NUMBER_SNORM; 1434 else if (desc->channel[i].pure_integer) 1435 ntype = V_0280A0_NUMBER_SINT; 1436 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1437 if (desc->channel[i].normalized) 1438 ntype = V_0280A0_NUMBER_UNORM; 1439 else if (desc->channel[i].pure_integer) 1440 ntype = V_0280A0_NUMBER_UINT; 1441 } 1442 1443 format = r600_translate_colorformat(surf->base.format); 1444 swap = r600_translate_colorswap(surf->base.format); 1445 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) { 1446 endian = ENDIAN_NONE; 1447 } else { 1448 endian = r600_colorformat_endian_swap(format); 1449 } 1450 1451 /* set blend bypass according to docs if SINT/UINT or 1452 8/24 COLOR variants */ 1453 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1454 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1455 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1456 blend_clamp = 0; 1457 blend_bypass = 1; 1458 } 1459 1460 color_info |= S_0280A0_FORMAT(format) | 1461 S_0280A0_COMP_SWAP(swap) | 1462 S_0280A0_BLEND_BYPASS(blend_bypass) | 1463 S_0280A0_BLEND_CLAMP(blend_clamp) | 1464 S_0280A0_NUMBER_TYPE(ntype) | 1465 S_0280A0_ENDIAN(endian); 1466 1467 /* EXPORT_NORM is an optimzation that can be enabled for better 1468 * performance in certain cases 1469 */ 1470 if (rctx->chip_class == R600) { 1471 /* EXPORT_NORM can be enabled if: 1472 * - 11-bit or smaller UNORM/SNORM/SRGB 1473 * - BLEND_CLAMP is enabled 1474 * - BLEND_FLOAT32 is disabled 1475 */ 1476 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1477 (desc->channel[i].size < 12 && 1478 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1479 ntype != V_0280A0_NUMBER_UINT && 1480 ntype != V_0280A0_NUMBER_SINT) && 1481 G_0280A0_BLEND_CLAMP(color_info) && 1482 !G_0280A0_BLEND_FLOAT32(color_info)) 1483 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1484 } else { 1485 /* EXPORT_NORM can be enabled if: 1486 * - 11-bit or smaller UNORM/SNORM/SRGB 1487 * - 16-bit or smaller FLOAT 1488 */ 1489 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1490 ((desc->channel[i].size < 12 && 1491 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1492 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1493 (desc->channel[i].size < 17 && 1494 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) 1495 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1496 } 1497 1498 r600_pipe_state_add_reg(rstate, 1499 R_028040_CB_COLOR0_BASE + cb * 4, 1500 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1501 r600_pipe_state_add_reg(rstate, 1502 R_0280A0_CB_COLOR0_INFO + cb * 4, 1503 color_info, &rtex->resource, RADEON_USAGE_READWRITE); 1504 r600_pipe_state_add_reg(rstate, 1505 R_028060_CB_COLOR0_SIZE + cb * 4, 1506 S_028060_PITCH_TILE_MAX(pitch) | 1507 S_028060_SLICE_TILE_MAX(slice), 1508 NULL, 0); 1509 if (!rscreen->use_surface) { 1510 r600_pipe_state_add_reg(rstate, 1511 R_028080_CB_COLOR0_VIEW + cb * 4, 1512 0x00000000, NULL, 0); 1513 } else { 1514 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1515 r600_pipe_state_add_reg(rstate, 1516 R_028080_CB_COLOR0_VIEW + cb * 4, 1517 0x00000000, NULL, 0); 1518 } else { 1519 r600_pipe_state_add_reg(rstate, 1520 R_028080_CB_COLOR0_VIEW + cb * 4, 1521 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1522 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer), 1523 NULL, 0); 1524 } 1525 } 1526 r600_pipe_state_add_reg(rstate, 1527 R_0280E0_CB_COLOR0_FRAG + cb * 4, 1528 0, &rtex->resource, RADEON_USAGE_READWRITE); 1529 r600_pipe_state_add_reg(rstate, 1530 R_0280C0_CB_COLOR0_TILE + cb * 4, 1531 0, &rtex->resource, RADEON_USAGE_READWRITE); 1532 r600_pipe_state_add_reg(rstate, 1533 R_028100_CB_COLOR0_MASK + cb * 4, 1534 0x00000000, NULL, 0); 1535} 1536 1537static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate, 1538 const struct pipe_framebuffer_state *state) 1539{ 1540 struct r600_screen *rscreen = rctx->screen; 1541 struct r600_resource_texture *rtex; 1542 struct r600_surface *surf; 1543 unsigned level, pitch, slice, format, offset, array_mode; 1544 1545 if (state->zsbuf == NULL) 1546 return; 1547 1548 level = state->zsbuf->u.tex.level; 1549 1550 surf = (struct r600_surface *)state->zsbuf; 1551 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 1552 1553 if (!rscreen->use_surface) { 1554 /* XXX remove this once tiling is properly supported */ 1555 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] : 1556 V_0280A0_ARRAY_1D_TILED_THIN1; 1557 1558 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1559 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 1560 level, state->zsbuf->u.tex.first_layer); 1561 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1562 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1563 if (slice) { 1564 slice = slice - 1; 1565 } 1566 } else { 1567 offset = rtex->surface.level[level].offset; 1568 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1569 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1570 if (slice) { 1571 slice = slice - 1; 1572 } 1573 switch (rtex->surface.level[level].mode) { 1574 case RADEON_SURF_MODE_2D: 1575 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1576 break; 1577 case RADEON_SURF_MODE_1D: 1578 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1579 case RADEON_SURF_MODE_LINEAR: 1580 default: 1581 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1582 break; 1583 } 1584 } 1585 1586 format = r600_translate_dbformat(state->zsbuf->texture->format); 1587 1588 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, 1589 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1590 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, 1591 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 1592 NULL, 0); 1593 if (!rscreen->use_surface) { 1594 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0); 1595 } else { 1596 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 1597 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) | 1598 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer), 1599 NULL, 0); 1600 } 1601 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO, 1602 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format), 1603 &rtex->resource, RADEON_USAGE_READWRITE); 1604 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, 1605 (surf->aligned_height / 8) - 1, NULL, 0); 1606} 1607 1608static void r600_set_framebuffer_state(struct pipe_context *ctx, 1609 const struct pipe_framebuffer_state *state) 1610{ 1611 struct r600_context *rctx = (struct r600_context *)ctx; 1612 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1613 uint32_t shader_mask, tl, br, shader_control; 1614 1615 if (rstate == NULL) 1616 return; 1617 1618 r600_flush_framebuffer(rctx, false); 1619 1620 /* unreference old buffer and reference new one */ 1621 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1622 1623 util_copy_framebuffer_state(&rctx->framebuffer, state); 1624 1625 /* build states */ 1626 rctx->have_depth_fb = 0; 1627 for (int i = 0; i < state->nr_cbufs; i++) { 1628 r600_cb(rctx, rstate, state, i); 1629 } 1630 if (state->zsbuf) { 1631 r600_db(rctx, rstate, state); 1632 } 1633 1634 shader_mask = 0; 1635 shader_control = 0; 1636 for (int i = 0; i < state->nr_cbufs; i++) { 1637 shader_mask |= 0xf << (i * 4); 1638 shader_control |= 1 << i; 1639 } 1640 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1641 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1642 1643 r600_pipe_state_add_reg(rstate, 1644 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, 1645 NULL, 0); 1646 r600_pipe_state_add_reg(rstate, 1647 R_028034_PA_SC_SCREEN_SCISSOR_BR, br, 1648 NULL, 0); 1649 r600_pipe_state_add_reg(rstate, 1650 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 1651 NULL, 0); 1652 r600_pipe_state_add_reg(rstate, 1653 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 1654 NULL, 0); 1655 r600_pipe_state_add_reg(rstate, 1656 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, 1657 NULL, 0); 1658 r600_pipe_state_add_reg(rstate, 1659 R_028244_PA_SC_GENERIC_SCISSOR_BR, br, 1660 NULL, 0); 1661 r600_pipe_state_add_reg(rstate, 1662 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 1663 NULL, 0); 1664 r600_pipe_state_add_reg(rstate, 1665 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 1666 NULL, 0); 1667 r600_pipe_state_add_reg(rstate, 1668 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, 1669 NULL, 0); 1670 if (rctx->chip_class >= R700) { 1671 r600_pipe_state_add_reg(rstate, 1672 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, 1673 NULL, 0); 1674 } 1675 1676 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1677 shader_control, NULL, 0); 1678 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 1679 shader_mask, NULL, 0); 1680 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 1681 0x00000000, NULL, 0); 1682 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 1683 0x00000000, NULL, 0); 1684 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 1685 0x00000000, NULL, 0); 1686 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL, 1687 0x01000000, NULL, 0); 1688 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC, 1689 0x00000000, NULL, 0); 1690 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST, 1691 0x000000FF, NULL, 0); 1692 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK, 1693 0xFFFFFFFF, NULL, 0); 1694 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK, 1695 0xFFFFFFFF, NULL, 0); 1696 1697 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1698 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1699 r600_context_pipe_state_set(rctx, rstate); 1700 1701 if (state->zsbuf) { 1702 r600_polygon_offset_update(rctx); 1703 } 1704} 1705 1706void r600_init_state_functions(struct r600_context *rctx) 1707{ 1708 rctx->context.create_blend_state = r600_create_blend_state; 1709 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 1710 rctx->context.create_fs_state = r600_create_shader_state; 1711 rctx->context.create_rasterizer_state = r600_create_rs_state; 1712 rctx->context.create_sampler_state = r600_create_sampler_state; 1713 rctx->context.create_sampler_view = r600_create_sampler_view; 1714 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 1715 rctx->context.create_vs_state = r600_create_shader_state; 1716 rctx->context.bind_blend_state = r600_bind_blend_state; 1717 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 1718 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 1719 rctx->context.bind_fs_state = r600_bind_ps_shader; 1720 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 1721 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 1722 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 1723 rctx->context.bind_vs_state = r600_bind_vs_shader; 1724 rctx->context.delete_blend_state = r600_delete_state; 1725 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 1726 rctx->context.delete_fs_state = r600_delete_ps_shader; 1727 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 1728 rctx->context.delete_sampler_state = r600_delete_state; 1729 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 1730 rctx->context.delete_vs_state = r600_delete_vs_shader; 1731 rctx->context.set_blend_color = r600_set_blend_color; 1732 rctx->context.set_clip_state = r600_set_clip_state; 1733 rctx->context.set_constant_buffer = r600_set_constant_buffer; 1734 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 1735 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 1736 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 1737 rctx->context.set_sample_mask = r600_set_sample_mask; 1738 rctx->context.set_scissor_state = r600_set_scissor_state; 1739 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 1740 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 1741 rctx->context.set_index_buffer = r600_set_index_buffer; 1742 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 1743 rctx->context.set_viewport_state = r600_set_viewport_state; 1744 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 1745 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 1746 rctx->context.texture_barrier = r600_texture_barrier; 1747 rctx->context.create_stream_output_target = r600_create_so_target; 1748 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 1749 rctx->context.set_stream_output_targets = r600_set_so_targets; 1750} 1751 1752void r600_adjust_gprs(struct r600_context *rctx) 1753{ 1754 struct r600_pipe_state rstate; 1755 unsigned num_ps_gprs = rctx->default_ps_gprs; 1756 unsigned num_vs_gprs = rctx->default_vs_gprs; 1757 unsigned tmp; 1758 int diff; 1759 1760 if (rctx->chip_class >= EVERGREEN) 1761 return; 1762 1763 if (!rctx->ps_shader || !rctx->vs_shader) 1764 return; 1765 1766 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs) 1767 { 1768 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs; 1769 num_vs_gprs -= diff; 1770 num_ps_gprs += diff; 1771 } 1772 1773 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs) 1774 { 1775 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs; 1776 num_ps_gprs -= diff; 1777 num_vs_gprs += diff; 1778 } 1779 1780 tmp = 0; 1781 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1782 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1783 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 1784 rstate.nregs = 0; 1785 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0); 1786 1787 r600_context_pipe_state_set(rctx, &rstate); 1788} 1789 1790void r600_init_atom_start_cs(struct r600_context *rctx) 1791{ 1792 int ps_prio; 1793 int vs_prio; 1794 int gs_prio; 1795 int es_prio; 1796 int num_ps_gprs; 1797 int num_vs_gprs; 1798 int num_gs_gprs; 1799 int num_es_gprs; 1800 int num_temp_gprs; 1801 int num_ps_threads; 1802 int num_vs_threads; 1803 int num_gs_threads; 1804 int num_es_threads; 1805 int num_ps_stack_entries; 1806 int num_vs_stack_entries; 1807 int num_gs_stack_entries; 1808 int num_es_stack_entries; 1809 enum radeon_family family; 1810 struct r600_command_buffer *cb = &rctx->atom_start_cs; 1811 uint32_t tmp; 1812 1813 r600_init_command_buffer(cb, 256, EMIT_EARLY); 1814 1815 /* R6xx requires this packet at the start of each command buffer */ 1816 if (rctx->chip_class == R600) { 1817 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 1818 r600_store_value(cb, 0); 1819 } 1820 /* All asics require this one */ 1821 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 1822 r600_store_value(cb, 0x80000000); 1823 r600_store_value(cb, 0x80000000); 1824 1825 family = rctx->family; 1826 ps_prio = 0; 1827 vs_prio = 1; 1828 gs_prio = 2; 1829 es_prio = 3; 1830 switch (family) { 1831 case CHIP_R600: 1832 num_ps_gprs = 192; 1833 num_vs_gprs = 56; 1834 num_temp_gprs = 4; 1835 num_gs_gprs = 0; 1836 num_es_gprs = 0; 1837 num_ps_threads = 136; 1838 num_vs_threads = 48; 1839 num_gs_threads = 4; 1840 num_es_threads = 4; 1841 num_ps_stack_entries = 128; 1842 num_vs_stack_entries = 128; 1843 num_gs_stack_entries = 0; 1844 num_es_stack_entries = 0; 1845 break; 1846 case CHIP_RV630: 1847 case CHIP_RV635: 1848 num_ps_gprs = 84; 1849 num_vs_gprs = 36; 1850 num_temp_gprs = 4; 1851 num_gs_gprs = 0; 1852 num_es_gprs = 0; 1853 num_ps_threads = 144; 1854 num_vs_threads = 40; 1855 num_gs_threads = 4; 1856 num_es_threads = 4; 1857 num_ps_stack_entries = 40; 1858 num_vs_stack_entries = 40; 1859 num_gs_stack_entries = 32; 1860 num_es_stack_entries = 16; 1861 break; 1862 case CHIP_RV610: 1863 case CHIP_RV620: 1864 case CHIP_RS780: 1865 case CHIP_RS880: 1866 default: 1867 num_ps_gprs = 84; 1868 num_vs_gprs = 36; 1869 num_temp_gprs = 4; 1870 num_gs_gprs = 0; 1871 num_es_gprs = 0; 1872 num_ps_threads = 136; 1873 num_vs_threads = 48; 1874 num_gs_threads = 4; 1875 num_es_threads = 4; 1876 num_ps_stack_entries = 40; 1877 num_vs_stack_entries = 40; 1878 num_gs_stack_entries = 32; 1879 num_es_stack_entries = 16; 1880 break; 1881 case CHIP_RV670: 1882 num_ps_gprs = 144; 1883 num_vs_gprs = 40; 1884 num_temp_gprs = 4; 1885 num_gs_gprs = 0; 1886 num_es_gprs = 0; 1887 num_ps_threads = 136; 1888 num_vs_threads = 48; 1889 num_gs_threads = 4; 1890 num_es_threads = 4; 1891 num_ps_stack_entries = 40; 1892 num_vs_stack_entries = 40; 1893 num_gs_stack_entries = 32; 1894 num_es_stack_entries = 16; 1895 break; 1896 case CHIP_RV770: 1897 num_ps_gprs = 192; 1898 num_vs_gprs = 56; 1899 num_temp_gprs = 4; 1900 num_gs_gprs = 0; 1901 num_es_gprs = 0; 1902 num_ps_threads = 188; 1903 num_vs_threads = 60; 1904 num_gs_threads = 0; 1905 num_es_threads = 0; 1906 num_ps_stack_entries = 256; 1907 num_vs_stack_entries = 256; 1908 num_gs_stack_entries = 0; 1909 num_es_stack_entries = 0; 1910 break; 1911 case CHIP_RV730: 1912 case CHIP_RV740: 1913 num_ps_gprs = 84; 1914 num_vs_gprs = 36; 1915 num_temp_gprs = 4; 1916 num_gs_gprs = 0; 1917 num_es_gprs = 0; 1918 num_ps_threads = 188; 1919 num_vs_threads = 60; 1920 num_gs_threads = 0; 1921 num_es_threads = 0; 1922 num_ps_stack_entries = 128; 1923 num_vs_stack_entries = 128; 1924 num_gs_stack_entries = 0; 1925 num_es_stack_entries = 0; 1926 break; 1927 case CHIP_RV710: 1928 num_ps_gprs = 192; 1929 num_vs_gprs = 56; 1930 num_temp_gprs = 4; 1931 num_gs_gprs = 0; 1932 num_es_gprs = 0; 1933 num_ps_threads = 144; 1934 num_vs_threads = 48; 1935 num_gs_threads = 0; 1936 num_es_threads = 0; 1937 num_ps_stack_entries = 128; 1938 num_vs_stack_entries = 128; 1939 num_gs_stack_entries = 0; 1940 num_es_stack_entries = 0; 1941 break; 1942 } 1943 1944 rctx->default_ps_gprs = num_ps_gprs; 1945 rctx->default_vs_gprs = num_vs_gprs; 1946 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 1947 1948 /* SQ_CONFIG */ 1949 tmp = 0; 1950 switch (family) { 1951 case CHIP_RV610: 1952 case CHIP_RV620: 1953 case CHIP_RS780: 1954 case CHIP_RS880: 1955 case CHIP_RV710: 1956 break; 1957 default: 1958 tmp |= S_008C00_VC_ENABLE(1); 1959 break; 1960 } 1961 tmp |= S_008C00_DX9_CONSTS(0); 1962 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 1963 tmp |= S_008C00_PS_PRIO(ps_prio); 1964 tmp |= S_008C00_VS_PRIO(vs_prio); 1965 tmp |= S_008C00_GS_PRIO(gs_prio); 1966 tmp |= S_008C00_ES_PRIO(es_prio); 1967 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 1968 1969 /* SQ_GPR_RESOURCE_MGMT_2 */ 1970 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 1971 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 1972 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 1973 r600_store_value(cb, tmp); 1974 1975 /* SQ_THREAD_RESOURCE_MGMT */ 1976 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 1977 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 1978 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 1979 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 1980 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 1981 1982 /* SQ_STACK_RESOURCE_MGMT_1 */ 1983 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 1984 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 1985 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 1986 1987 /* SQ_STACK_RESOURCE_MGMT_2 */ 1988 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 1989 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 1990 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 1991 1992 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 1993 1994 r600_store_context_reg(cb, R_028350_SX_MISC, 0); 1995 1996 if (rctx->chip_class >= R700) { 1997 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 1998 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 1999 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2000 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2001 } else { 2002 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2003 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2004 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2005 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2006 } 2007 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2008 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2009 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2010 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2011 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2012 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2013 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2014 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2015 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2016 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2017 2018 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2019 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2020 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2021 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2022 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2023 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2024 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2025 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2026 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2027 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2028 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2029 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2030 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2031 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2032 2033 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2034 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2035 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2036 2037 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2038 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2039 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2040 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2041 2042 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2043} 2044 2045void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2046{ 2047 struct r600_context *rctx = (struct r600_context *)ctx; 2048 struct r600_pipe_state *rstate = &shader->rstate; 2049 struct r600_shader *rshader = &shader->shader; 2050 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2051 int pos_index = -1, face_index = -1; 2052 unsigned tmp, sid, ufi = 0; 2053 int need_linear = 0; 2054 2055 rstate->nregs = 0; 2056 2057 for (i = 0; i < rshader->ninput; i++) { 2058 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2059 pos_index = i; 2060 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2061 face_index = i; 2062 2063 sid = rshader->input[i].spi_sid; 2064 2065 tmp = S_028644_SEMANTIC(sid); 2066 2067 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2068 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2069 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2070 rctx->rasterizer && rctx->rasterizer->flatshade)) 2071 tmp |= S_028644_FLAT_SHADE(1); 2072 2073 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2074 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2075 tmp |= S_028644_PT_SPRITE_TEX(1); 2076 } 2077 2078 if (rshader->input[i].centroid) 2079 tmp |= S_028644_SEL_CENTROID(1); 2080 2081 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2082 need_linear = 1; 2083 tmp |= S_028644_SEL_LINEAR(1); 2084 } 2085 2086 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2087 tmp, NULL, 0); 2088 } 2089 2090 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2091 for (i = 0; i < rshader->noutput; i++) { 2092 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2093 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 2094 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2095 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1); 2096 } 2097 if (rshader->uses_kill) 2098 db_shader_control |= S_02880C_KILL_ENABLE(1); 2099 2100 exports_ps = 0; 2101 num_cout = 0; 2102 for (i = 0; i < rshader->noutput; i++) { 2103 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2104 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2105 exports_ps |= 1; 2106 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { 2107 num_cout++; 2108 } 2109 } 2110 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2111 if (!exports_ps) { 2112 /* always at least export 1 component per pixel */ 2113 exports_ps = 2; 2114 } 2115 2116 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2117 S_0286CC_PERSP_GRADIENT_ENA(1)| 2118 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2119 spi_input_z = 0; 2120 if (pos_index != -1) { 2121 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2122 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2123 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2124 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2125 spi_input_z |= 1; 2126 } 2127 2128 spi_ps_in_control_1 = 0; 2129 if (face_index != -1) { 2130 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2131 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2132 } 2133 2134 /* HW bug in original R600 */ 2135 if (rctx->family == CHIP_R600) 2136 ufi = 1; 2137 2138 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0); 2139 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0); 2140 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0); 2141 r600_pipe_state_add_reg(rstate, 2142 R_028840_SQ_PGM_START_PS, 2143 0, shader->bo, RADEON_USAGE_READ); 2144 r600_pipe_state_add_reg(rstate, 2145 R_028850_SQ_PGM_RESOURCES_PS, 2146 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2147 S_028850_STACK_SIZE(rshader->bc.nstack) | 2148 S_028850_UNCACHED_FIRST_INST(ufi), 2149 NULL, 0); 2150 r600_pipe_state_add_reg(rstate, 2151 R_028854_SQ_PGM_EXPORTS_PS, 2152 exports_ps, NULL, 0); 2153 r600_pipe_state_add_reg(rstate, 2154 R_0288CC_SQ_PGM_CF_OFFSET_PS, 2155 0x00000000, NULL, 0); 2156 /* only set some bits here, the other bits are set in the dsa state */ 2157 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, 2158 db_shader_control, 2159 NULL, 0); 2160 2161 r600_pipe_state_add_reg(rstate, 2162 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF, 2163 NULL, 0); 2164 2165 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2166 if (rctx->rasterizer) 2167 shader->flatshade = rctx->rasterizer->flatshade; 2168} 2169 2170void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2171{ 2172 struct r600_context *rctx = (struct r600_context *)ctx; 2173 struct r600_pipe_state *rstate = &shader->rstate; 2174 struct r600_shader *rshader = &shader->shader; 2175 unsigned spi_vs_out_id[10] = {}; 2176 unsigned i, tmp, nparams = 0; 2177 2178 /* clear previous register */ 2179 rstate->nregs = 0; 2180 2181 for (i = 0; i < rshader->noutput; i++) { 2182 if (rshader->output[i].spi_sid) { 2183 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2184 spi_vs_out_id[nparams / 4] |= tmp; 2185 nparams++; 2186 } 2187 } 2188 2189 for (i = 0; i < 10; i++) { 2190 r600_pipe_state_add_reg(rstate, 2191 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2192 spi_vs_out_id[i], NULL, 0); 2193 } 2194 2195 /* Certain attributes (position, psize, etc.) don't count as params. 2196 * VS is required to export at least one param and r600_shader_from_tgsi() 2197 * takes care of adding a dummy export. 2198 */ 2199 if (nparams < 1) 2200 nparams = 1; 2201 2202 r600_pipe_state_add_reg(rstate, 2203 R_0286C4_SPI_VS_OUT_CONFIG, 2204 S_0286C4_VS_EXPORT_COUNT(nparams - 1), 2205 NULL, 0); 2206 r600_pipe_state_add_reg(rstate, 2207 R_028868_SQ_PGM_RESOURCES_VS, 2208 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2209 S_028868_STACK_SIZE(rshader->bc.nstack), 2210 NULL, 0); 2211 r600_pipe_state_add_reg(rstate, 2212 R_0288D0_SQ_PGM_CF_OFFSET_VS, 2213 0x00000000, NULL, 0); 2214 r600_pipe_state_add_reg(rstate, 2215 R_028858_SQ_PGM_START_VS, 2216 0, shader->bo, RADEON_USAGE_READ); 2217 2218 r600_pipe_state_add_reg(rstate, 2219 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, 2220 NULL, 0); 2221 2222 shader->pa_cl_vs_out_cntl = 2223 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2224 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2225 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2226 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2227} 2228 2229void r600_fetch_shader(struct pipe_context *ctx, 2230 struct r600_vertex_element *ve) 2231{ 2232 struct r600_pipe_state *rstate; 2233 struct r600_context *rctx = (struct r600_context *)ctx; 2234 2235 rstate = &ve->rstate; 2236 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2237 rstate->nregs = 0; 2238 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS, 2239 0x00000000, NULL, 0); 2240 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS, 2241 0x00000000, NULL, 0); 2242 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS, 2243 0, 2244 ve->fetch_shader, RADEON_USAGE_READ); 2245} 2246 2247void *r600_create_db_flush_dsa(struct r600_context *rctx) 2248{ 2249 struct pipe_depth_stencil_alpha_state dsa; 2250 struct r600_pipe_state *rstate; 2251 struct r600_pipe_dsa *dsa_state; 2252 unsigned db_render_control; 2253 boolean quirk = false; 2254 2255 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2256 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2257 quirk = true; 2258 2259 memset(&dsa, 0, sizeof(dsa)); 2260 2261 if (quirk) { 2262 dsa.depth.enabled = 1; 2263 dsa.depth.func = PIPE_FUNC_LEQUAL; 2264 dsa.stencil[0].enabled = 1; 2265 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2266 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2267 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2268 dsa.stencil[0].writemask = 0xff; 2269 } 2270 2271 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2272 dsa_state = (struct r600_pipe_dsa*)rstate; 2273 2274 db_render_control = 2275 S_028D0C_DEPTH_COPY_ENABLE(1) | 2276 S_028D0C_STENCIL_COPY_ENABLE(1) | 2277 S_028D0C_COPY_CENTROID(1); 2278 2279 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0); 2280 2281 dsa_state->db_render_control = db_render_control; 2282 2283 return rstate; 2284} 2285 2286void r600_pipe_init_buffer_resource(struct r600_context *rctx, 2287 struct r600_pipe_resource_state *rstate) 2288{ 2289 rstate->id = R600_PIPE_STATE_RESOURCE; 2290 2291 rstate->bo[0] = NULL; 2292 rstate->val[0] = 0; 2293 rstate->val[1] = 0; 2294 rstate->val[2] = 0; 2295 rstate->val[3] = 0; 2296 rstate->val[4] = 0; 2297 rstate->val[5] = 0; 2298 rstate->val[6] = 0xc0000000; 2299} 2300 2301void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 2302 struct r600_resource *rbuffer, 2303 unsigned offset, unsigned stride, 2304 enum radeon_bo_usage usage) 2305{ 2306 rstate->val[0] = offset; 2307 rstate->bo[0] = rbuffer; 2308 rstate->bo_usage[0] = usage; 2309 rstate->val[1] = rbuffer->buf->size - offset - 1; 2310 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 2311 S_038008_STRIDE(stride); 2312} 2313