14637235183b80963536f2364e4d50fcb894886ddDave Airlie 24637235183b80963536f2364e4d50fcb894886ddDave Airlie#ifndef COMMON_CONTEXT_H 34637235183b80963536f2364e4d50fcb894886ddDave Airlie#define COMMON_CONTEXT_H 461da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie 561da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie#include "main/mm.h" 661da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie#include "math/m_vector.h" 761da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie#include "tnl/t_context.h" 861da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie#include "main/colormac.h" 961da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie 104e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen#include "radeon_debug.h" 118c6a7d01744fe6164a868c5f691bb119109773c0Dave Airlie#include "radeon_screen.h" 128c6a7d01744fe6164a868c5f691bb119109773c0Dave Airlie#include "radeon_drm.h" 138c6a7d01744fe6164a868c5f691bb119109773c0Dave Airlie#include "dri_util.h" 14f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie#include "tnl/t_vertex.h" 15abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul#include "swrast/s_context.h" 1661da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie 1705304d41f2d9ab7a66a8b976580c156b7b93a9d3Dave Airliestruct radeon_context; 1805304d41f2d9ab7a66a8b976580c156b7b93a9d3Dave Airlie 1909a92e376bf954603dad4a6ad9a18cce3c52b484Dave Airlie#include "radeon_bo_gem.h" 2009a92e376bf954603dad4a6ad9a18cce3c52b484Dave Airlie#include "radeon_cs_gem.h" 2105304d41f2d9ab7a66a8b976580c156b7b93a9d3Dave Airlie 22692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* This union is used to avoid warnings/miscompilation 23692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie with float to uint32_t casts due to strict-aliasing */ 24692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlietypedef union { GLfloat f; uint32_t ui32; } float_ui32_type; 25692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 264637235183b80963536f2364e4d50fcb894886ddDave Airliestruct radeon_context; 274637235183b80963536f2364e4d50fcb894886ddDave Airlietypedef struct radeon_context radeonContextRec; 284637235183b80963536f2364e4d50fcb894886ddDave Airlietypedef struct radeon_context *radeonContextPtr; 294637235183b80963536f2364e4d50fcb894886ddDave Airlie 30692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 31692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_0 0x1 32692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_1 0x2 33692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_2 0x4 34692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_3 0x8 35692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_4 0x10 36692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TEX_5 0x20 37692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 38692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* Rasterizing fallbacks */ 39692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* See correponding strings in r200_swtcl.c */ 40692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_TEXTURE 0x0001 41692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 42692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_STENCIL 0x0004 43692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_RENDER_MODE 0x0008 44692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_BLEND_EQ 0x0010 45692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_BLEND_FUNC 0x0020 46692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_DISABLE 0x0040 47692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_FALLBACK_BORDER_MODE 0x0080 482b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie#define RADEON_FALLBACK_DEPTH_BUFFER 0x0100 492b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie#define RADEON_FALLBACK_STENCIL_BUFFER 0x0200 50692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 51692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_TEXTURE 0x01 52692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_DRAW_BUFFER 0x02 53692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_STENCIL 0x04 54692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_RENDER_MODE 0x08 55692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_DISABLE 0x10 56692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_FALLBACK_BORDER_MODE 0x20 57692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 58ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ 59ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ 60ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ 61ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ 62ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ 63ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ 64ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ 65ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ 66ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ 67ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie 68692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* The blit width for texture uploads 69692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie */ 70692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define BLIT_WIDTH_BYTES 1024 71692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 72692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* Use the templated vertex format: 73692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie */ 74692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define COLOR_IS_RGBA 75692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define TAG(x) radeon##x 76692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#include "tnl_dd/t_dd_vertex.h" 77692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#undef TAG 78692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 79bdaa0341caffc353fd26bbd91865c2d86eed11c1Dave Airlie#define RADEON_RB_CLASS 0xdeadbeef 80bdaa0341caffc353fd26bbd91865c2d86eed11c1Dave Airlie 81dc8a707c672918b88dd4135930bef60ed148d8ceDave Airliestruct radeon_renderbuffer 82dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie{ 83c080202db5363a18a759a9a7c82b40ac558c8abeBrian Paul struct swrast_renderbuffer base; 84c080202db5363a18a759a9a7c82b40ac558c8abeBrian Paul 85dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie struct radeon_bo *bo; 86dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie unsigned int cpp; 87dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie /* unsigned int offset; */ 88dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie unsigned int pitch; 89dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie 90425b8d54b8c97bcbd433393f34a27027e4ff8c4dEric Anholt struct radeon_bo *map_bo; 91425b8d54b8c97bcbd433393f34a27027e4ff8c4dEric Anholt GLbitfield map_mode; 92425b8d54b8c97bcbd433393f34a27027e4ff8c4dEric Anholt int map_x, map_y, map_w, map_h; 93b2596c36c8f73e8bb7a0b1679b491662aeb2f9d9Dave Airlie int map_pitch; 947d91ecf7a3a08c01a704f2d427444f7a97991680Dave Airlie void *map_buffer; 95425b8d54b8c97bcbd433393f34a27027e4ff8c4dEric Anholt 96c607a664dd005c001afda1fff1a68d41925fa86eDave Airlie uint32_t draw_offset; /* FBO */ 97dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie /* boo Xorg 6.8.2 compat */ 98dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie int has_surface; 99dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie 1002b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie GLuint pf_pending; /**< sequence number of pending flip */ 101d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIdrawable *dPriv; 102dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie}; 103dc8a707c672918b88dd4135930bef60ed148d8ceDave Airlie 1042b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airliestruct radeon_framebuffer 1052b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie{ 1062b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie struct gl_framebuffer base; 1072b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie 1082b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie struct radeon_renderbuffer *color_rb[2]; 1092b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie}; 1102b85fccae5ba33748846f74f90fe0f72c673a4b1Dave Airlie 1117dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 112692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_colorbuffer_state { 113692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie int roundEnable; 11401daeadf8cd8c56820585c3da88cc626dcdc33d0Michel Dänzer struct gl_renderbuffer *rb; 115c607a664dd005c001afda1fff1a68d41925fa86eDave Airlie uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ 116692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 117692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 118692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_depthbuffer_state { 11901daeadf8cd8c56820585c3da88cc626dcdc33d0Michel Dänzer struct gl_renderbuffer *rb; 120692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 121692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 122692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_scissor_state { 123692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie drm_clip_rect_t rect; 124692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLboolean enabled; 125692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 126692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 127692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_state_atom { 128692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_state_atom *next, *prev; 129692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie const char *name; /* for debug */ 130692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie int cmd_size; /* size in bytes */ 131b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie GLuint idx; 132692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint is_tcl; 1334637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint *cmd; /* one or more cmd's */ 1344637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint *lastcmd; /* one or more cmd's */ 135692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLboolean dirty; /* dirty-mark in emit_state_list */ 136f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */ 137f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*emit) (struct gl_context *, struct radeon_state_atom *atom); 138692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 139692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 1401090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airliestruct radeon_hw_state { 1411090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie /* Head of the linked list of state atoms. */ 1421090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie struct radeon_state_atom atomlist; 1431090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie int max_state_size; /* Number of bytes necessary for a full state emit. */ 1449ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie int max_post_flush_size; /* Number of bytes necessary for post flushing emits */ 1451090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie GLboolean is_dirty, all_dirty; 1461090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie}; 1471090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie 148ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 149ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie/* Texture related */ 150ddbd6ed326275de0c22011a2700f342409beee76Dave Airlietypedef struct _radeon_texture_image radeon_texture_image; 151ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 152abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul 153abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul/** 154abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul * This is a subclass of swrast_texture_image since we use swrast 155abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul * for software fallback rendering. 156abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul */ 157ddbd6ed326275de0c22011a2700f342409beee76Dave Airliestruct _radeon_texture_image { 158abdfa0b4f1e5ae0bd3d71ae7099b6bb7c2bfae71Brian Paul struct swrast_texture_image base; 159ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 160ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie /** 161ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * If mt != 0, the image is stored in hardware format in the 162ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * given mipmap tree. In this case, base.Data may point into the 163ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * mapping of the buffer object that contains the mipmap tree. 164ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * 165ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * If mt == 0, the image is stored in normal memory pointed to 166ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie * by base.Data. 167ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie */ 168ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie struct _radeon_mipmap_tree *mt; 169ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie struct radeon_bo *bo; 170b2596c36c8f73e8bb7a0b1679b491662aeb2f9d9Dave Airlie GLboolean used_as_render_target; 171ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie}; 172ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 173ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 174ddbd6ed326275de0c22011a2700f342409beee76Dave Airliestatic INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) 175ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie{ 176ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie return (radeon_texture_image*)image; 177ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie} 178ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 179ddbd6ed326275de0c22011a2700f342409beee76Dave Airlie 180692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlietypedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 181692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 18233dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie#define RADEON_TXO_MICRO_TILE (1 << 3) 18333dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie 184692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* Texture object in locally shared texture space. 185692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie */ 186692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_tex_obj { 18733dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie struct gl_texture_object base; 18833dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie struct _radeon_mipmap_tree *mt; 18933dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie 19033dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie /** 19133dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie * This is true if we've verified that the mipmap tree above is complete 19233dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie * and so on. 19333dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie */ 19433dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie GLboolean validated; 19523ec7c457483aae1e0d399e9b570f1860c27c780Maciej Cencora /* Minimum LOD to be used during rendering */ 19623ec7c457483aae1e0d399e9b570f1860c27c780Maciej Cencora unsigned minLod; 19723ec7c457483aae1e0d399e9b570f1860c27c780Maciej Cencora /* Miximum LOD to be used during rendering */ 19823ec7c457483aae1e0d399e9b570f1860c27c780Maciej Cencora unsigned maxLod; 19933dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie 20033dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie GLuint override_offset; 20133dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ 20233dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie GLuint tile_bits; /* hw texture tile bits used on this texture */ 20333dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie struct radeon_bo *bo; 204692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 205692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_txfilter; /* hardware register values */ 206692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_txformat; 20762d504d818f1ab1836a134658b1661ceabb65f1fDave Airlie GLuint pp_txformat_x; 208692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_txsize; /* npot only */ 209692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_txpitch; /* npot only */ 210692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_border_color; 211692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 212692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 213692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLboolean border_fallback; 214692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 21533dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie 21633dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airliestatic INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) 21733dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie{ 21833dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie return (radeonTexObj*)texObj; 21933dc14c707734df37fb02b7bcc278ddeb94036f1Dave Airlie} 220692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 2219ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie/* occlusion query */ 2229ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airliestruct radeon_query_object { 2239ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct gl_query_object Base; 2249ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct radeon_bo *bo; 2259ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie int curr_offset; 2269ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie GLboolean emitted_begin; 2279ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie 2289ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie /* Double linked list of not flushed query objects */ 2299ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct radeon_query_object *prev, *next; 2309ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie}; 2319ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie 232692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie/* Need refcounting on dma buffers: 233692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie */ 234692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_dma_buffer { 235692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie int refcount; /* the number of retained regions in buf */ 236692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie drmBufPtr buf; 237692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 238692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 239ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airliestruct radeon_aos { 240ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie struct radeon_bo *bo; /** Buffer object where vertex data is stored */ 241ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie int offset; /** Offset into buffer object, in bytes */ 242ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie int components; /** Number of components per vertex */ 243ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie int stride; /** Stride in dwords (may be 0 for repeating) */ 244ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie int count; /** Number of vertices */ 245ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie}; 246692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 247bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen#define DMA_BO_FREE_TIME 100 248bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen 249bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminenstruct radeon_dma_bo { 250bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen struct radeon_dma_bo *next, *prev; 251bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen struct radeon_bo *bo; 252bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen int expire_counter; 253bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen}; 254bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen 255692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_dma { 2565ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie /* Active dma region. Allocations for vertices and retained 2575ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie * regions come from here. Also used for emitting random vertices, 2585ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie * these may be flushed by calling flush_current(); 2595ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie */ 260bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen struct radeon_dma_bo free; 261bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen struct radeon_dma_bo wait; 262bbf2b5c4ffcb6755d34a5b698445aecf604e45fbPauli Nieminen struct radeon_dma_bo reserved; 26366e019c6c91e6ae3fb9e26a12d7b7782a0095a8dPauli Nieminen size_t current_used; /** Number of bytes allocated and forgotten about */ 26466e019c6c91e6ae3fb9e26a12d7b7782a0095a8dPauli Nieminen size_t current_vertexptr; /** End of active vertex region */ 26566e019c6c91e6ae3fb9e26a12d7b7782a0095a8dPauli Nieminen size_t minimum_size; 2665ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie 2675ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie /** 2685ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie * If current_vertexptr != current_used then flush must be non-zero. 2695ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie * flush must be called before non-active vertex allocations can be 2705ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie * performed. 2715ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie */ 272f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*flush) (struct gl_context *); 273692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 274692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 27570661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie/* radeon_swtcl.c 27670661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie */ 27770661f678edcc9b6dd5005016e3355ec4546e716Dave Airliestruct radeon_swtcl_info { 27870661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie 279f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLuint RenderIndex; 280f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLuint vertex_size; 281f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLubyte *verts; 282f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie 283f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie /* Fallback rasterization functions 284f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie */ 285f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLuint hw_primitive; 286f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLenum render_primitive; 287f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLuint numverts; 288f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie 289f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 290f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie GLuint vertex_attr_count; 29170661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie 292570d4e375a327787441c2c7c4ae698e8993a5d6bPauli Nieminen GLuint emit_prediction; 293bd13e6e5e2403ada2098e3a07c0af4b4ba989ab7Dave Airlie struct radeon_bo *bo; 29470661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie}; 29570661f678edcc9b6dd5005016e3355ec4546e716Dave Airlie 296e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie#define RADEON_MAX_AOS_ARRAYS 16 297e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airliestruct radeon_tcl_info { 298e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS]; 299e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie GLuint aos_count; 300e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ 301e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie int elt_dma_offset; /** Offset into this buffer object, in bytes */ 302e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie}; 303e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie 304692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_ioctl { 305692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint vertex_offset; 30620d9204fbd71aebf870834b612579419d2c278b5Dave Airlie GLuint vertex_max; 30720d9204fbd71aebf870834b612579419d2c278b5Dave Airlie struct radeon_bo *bo; 308692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint vertex_size; 309692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 310692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 311692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define RADEON_MAX_PRIMS 64 312692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 313692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestruct radeon_prim { 314692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint start; 315692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint end; 316692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLuint prim; 317692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie}; 318692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 319692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airliestatic INLINE GLuint radeonPackColor(GLuint cpp, 320692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLubyte r, GLubyte g, 321692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie GLubyte b, GLubyte a) 322692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie{ 323692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie switch (cpp) { 324692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie case 2: 325692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie return PACK_COLOR_565(r, g, b); 326692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie case 4: 327692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie return PACK_COLOR_8888(a, r, g, b); 328692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie default: 329692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie return 0; 330692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie } 331692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie} 332b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 3330217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie#define MAX_CMD_BUF_SZ (16*1024) 3340217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie 3355ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie#define MAX_DMA_BUF_SZ (64*1024) 3365ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie 3370217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airliestruct radeon_store { 3380217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie GLuint statenr; 3390217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie GLuint primnr; 3400217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie char cmd_buf[MAX_CMD_BUF_SZ]; 3410217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie int cmd_used; 3420217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie int elts_start; 3430217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie}; 3440217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie 345b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airliestruct radeon_dri_mirror { 346d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIcontext *context; /* DRI context */ 347d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIscreen *screen; /* DRI screen */ 348b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 349b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie drm_context_t hwContext; 350b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie drm_hw_lock_t *hwLock; 35129173d3d5cf02d58e720b5c7fe48a0630c7d5d5fPauli Nieminen int hwLockCount; 352b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie int fd; 353b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie int drmMinor; 354b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie}; 355b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 3564637235183b80963536f2364e4d50fcb894886ddDave Airlietypedef void (*radeon_tri_func) (radeonContextPtr, 3574637235183b80963536f2364e4d50fcb894886ddDave Airlie radeonVertex *, 3584637235183b80963536f2364e4d50fcb894886ddDave Airlie radeonVertex *, radeonVertex *); 3594637235183b80963536f2364e4d50fcb894886ddDave Airlie 3604637235183b80963536f2364e4d50fcb894886ddDave Airlietypedef void (*radeon_line_func) (radeonContextPtr, 3614637235183b80963536f2364e4d50fcb894886ddDave Airlie radeonVertex *, radeonVertex *); 3624637235183b80963536f2364e4d50fcb894886ddDave Airlie 3634637235183b80963536f2364e4d50fcb894886ddDave Airlietypedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); 3644637235183b80963536f2364e4d50fcb894886ddDave Airlie 365e21e82f42549aa78214f3339a13b79791406dde0Maciej Cencora#define RADEON_MAX_BOS 32 366d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airliestruct radeon_state { 3674637235183b80963536f2364e4d50fcb894886ddDave Airlie struct radeon_colorbuffer_state color; 368d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie struct radeon_depthbuffer_state depth; 3694637235183b80963536f2364e4d50fcb894886ddDave Airlie struct radeon_scissor_state scissor; 3704637235183b80963536f2364e4d50fcb894886ddDave Airlie}; 3714637235183b80963536f2364e4d50fcb894886ddDave Airlie 37261da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie/** 37361da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie * This structure holds the command buffer while it is being constructed. 37461da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie * 37561da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie * The first batch of commands in the buffer is always the state that needs 37661da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie * to be re-emitted when the context is lost. This batch can be skipped 37761da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie * otherwise. 37861da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie */ 37961da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airliestruct radeon_cmdbuf { 38061da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie struct radeon_cs_manager *csm; 38161da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie struct radeon_cs *cs; 38261da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie int size; /** # of dwords total */ 38361da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ 38461da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie}; 38561da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie 3864637235183b80963536f2364e4d50fcb894886ddDave Airliestruct radeon_context { 387f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg struct gl_context *glCtx; 3884637235183b80963536f2364e4d50fcb894886ddDave Airlie radeonScreenPtr radeonScreen; /* Screen private DRI data */ 3897dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 3904637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Texture object bookkeeping 3914637235183b80963536f2364e4d50fcb894886ddDave Airlie */ 3924637235183b80963536f2364e4d50fcb894886ddDave Airlie int texture_depth; 3934637235183b80963536f2364e4d50fcb894886ddDave Airlie float initialMaxAnisotropy; 3940b22615c2c860968a027c04519e25864ae69f6cdMaciej Cencora uint32_t texture_row_align; 395b116f57bacb79205a1f80c7055964c60b402a19dAlex Deucher uint32_t texture_rect_row_align; 396b116f57bacb79205a1f80c7055964c60b402a19dAlex Deucher uint32_t texture_compressed_row_align; 3974637235183b80963536f2364e4d50fcb894886ddDave Airlie 3985ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie struct radeon_dma dma; 3991090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie struct radeon_hw_state hw; 4004637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Rasterization and vertex state: 4014637235183b80963536f2364e4d50fcb894886ddDave Airlie */ 4024637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint TclFallback; 4034637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint Fallback; 4044637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint NewGLState; 40545cd15bfae2f6c66c9e4356fb8dd7cad1829f659Mathias Fröhlich GLbitfield64 tnl_index_bitset; /* index of bits for last tnl_install_attrs */ 4064637235183b80963536f2364e4d50fcb894886ddDave Airlie 407339c1731c346f21bf212e4d94d57d09d8cbfc9f4Eric Anholt /* Drawable information */ 4084637235183b80963536f2364e4d50fcb894886ddDave Airlie unsigned int lastStamp; 4094637235183b80963536f2364e4d50fcb894886ddDave Airlie drm_radeon_sarea_t *sarea; /* Private SAREA data */ 4104637235183b80963536f2364e4d50fcb894886ddDave Airlie 4114637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Mirrors of some DRI state */ 4124637235183b80963536f2364e4d50fcb894886ddDave Airlie struct radeon_dri_mirror dri; 4134637235183b80963536f2364e4d50fcb894886ddDave Airlie 4144637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Busy waiting */ 4154637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint do_usleeps; 4164637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint do_irqs; 4174637235183b80963536f2364e4d50fcb894886ddDave Airlie GLuint irqsEmitted; 4184637235183b80963536f2364e4d50fcb894886ddDave Airlie drm_radeon_irq_wait_t iw; 4194637235183b80963536f2364e4d50fcb894886ddDave Airlie 4204637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Derived state - for r300 only */ 421d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie struct radeon_state state; 4224637235183b80963536f2364e4d50fcb894886ddDave Airlie 423f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie struct radeon_swtcl_info swtcl; 424e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie struct radeon_tcl_info tcl; 4254637235183b80963536f2364e4d50fcb894886ddDave Airlie /* Configuration cache 4264637235183b80963536f2364e4d50fcb894886ddDave Airlie */ 4274637235183b80963536f2364e4d50fcb894886ddDave Airlie driOptionCache optionCache; 4284637235183b80963536f2364e4d50fcb894886ddDave Airlie 42961da612a4f8862e0aac4ff4fc87c133cb8a1c4a5Dave Airlie struct radeon_cmdbuf cmdbuf; 4307dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 431fde929c4fdee2e998542f071ff7165d87f572593Pauli Nieminen struct radeon_debug debug; 432fde929c4fdee2e998542f071ff7165d87f572593Pauli Nieminen 4338c7e30fb950c83f5e9e29e60735e999ac608145aDave Airlie drm_clip_rect_t fboRect; 4348c7e30fb950c83f5e9e29e60735e999ac608145aDave Airlie GLboolean front_cliprects; 4358c7e30fb950c83f5e9e29e60735e999ac608145aDave Airlie 43698bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld /** 43798bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * Set if rendering has occured to the drawable's front buffer. 43898bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * 43998bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * This is used in the DRI2 case to detect that glFlush should also copy 44098bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * the contents of the fake front buffer to the real front buffer. 44198bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld */ 44298bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld GLboolean front_buffer_dirty; 44398bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld 44498bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld /** 44598bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * Track whether front-buffer rendering is currently enabled 44698bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * 44798bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * A separate flag is used to track this in order to support MRT more 44898bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld * easily. 44998bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld */ 45098bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld GLboolean is_front_buffer_rendering; 45198bb5c610dc68d8e9a185216ce9d2dc6d278c114Joel Bosveld 452bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie /** 453bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie * Track whether front-buffer is the current read target. 454bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie * 455bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie * This is closely associated with is_front_buffer_rendering, but may 456bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie * be set separately. The DRI2 fake front buffer must be referenced 457bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie * either way. 458bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie */ 459bb4c70358778f28f644ae493b5d8163e76e9fddbDave Airlie GLboolean is_front_buffer_reading; 4608c7e30fb950c83f5e9e29e60735e999ac608145aDave Airlie 461d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie struct { 4629ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct radeon_query_object *current; 4639ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct radeon_state_atom queryobj; 4649ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie } query; 4659ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie 4669ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie struct { 467f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie void (*get_lock)(radeonContextPtr radeon); 468f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*update_viewport_offset)(struct gl_context *ctx); 469f68a61d88398fe8eb3eb41b929dcb4483354a81eDave Airlie void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); 470f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset); 4711090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie void (*pre_emit_atoms)(radeonContextPtr rmesa); 4721090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie void (*pre_emit_state)(radeonContextPtr rmesa); 473f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode); 474f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*free_context)(struct gl_context *ctx); 4759ad76e9479c9c3cb8b2947d5144de33bb31197b8Dave Airlie void (*emit_query_finish)(radeonContextPtr radeon); 476f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg void (*update_scissor)(struct gl_context *ctx); 477b2596c36c8f73e8bb7a0b1679b491662aeb2f9d9Dave Airlie unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch); 478f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg unsigned (*blit)(struct gl_context *ctx, 479f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora struct radeon_bo *src_bo, 480f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora intptr_t src_offset, 481f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora gl_format src_mesaformat, 482f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned src_pitch, 483f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned src_width, 484f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned src_height, 485f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned src_x_offset, 486f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned src_y_offset, 487f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora struct radeon_bo *dst_bo, 488f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora intptr_t dst_offset, 489f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora gl_format dst_mesaformat, 490f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned dst_pitch, 491f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned dst_width, 492f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned dst_height, 493f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned dst_x_offset, 494f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned dst_y_offset, 495f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned reg_width, 496f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned reg_height, 497f542fde77effbc3c780940e139fc2572e818a179Maciej Cencora unsigned flip_y); 498a17563c7ddfa58fe7f09d22a62a10f3488ef3147Maciej Cencora unsigned (*is_format_renderable)(gl_format mesa_format); 499d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie } vtbl; 5004637235183b80963536f2364e4d50fcb894886ddDave Airlie}; 5014637235183b80963536f2364e4d50fcb894886ddDave Airlie 5024637235183b80963536f2364e4d50fcb894886ddDave Airlie#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) 5034637235183b80963536f2364e4d50fcb894886ddDave Airlie 504d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergstatic inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon) 5057dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle{ 5067dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle return radeon->dri.context->driDrawablePriv; 5077dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle} 5087dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 509d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergstatic inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon) 5107dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle{ 5117dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle return radeon->dri.context->driReadablePriv; 5127dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle} 5137dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 51423d3559bd4ece1fcab5513ebdaa38600d6654374Dave AirlieGLboolean radeonInitContext(radeonContextPtr radeon, 51523d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlie struct dd_function_table* functions, 516d3491e775fb07f891463b2185d74bbad62f3ed24Kristian Høgsberg const struct gl_config * glVisual, 517d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIcontext * driContextPriv, 51823d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlie void *sharedContextPrivate); 51923d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlie 52023d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlievoid radeonCleanupContext(radeonContextPtr radeon); 521d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian HøgsbergGLboolean radeonUnbindContext(__DRIcontext * driContextPriv); 522433f0a82f5a4696e6b0c4061f645485ec8079bb4Michel Dänzervoid radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable, 523433f0a82f5a4696e6b0c4061f645485ec8079bb4Michel Dänzer GLboolean front_only); 524d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian HøgsbergGLboolean radeonMakeCurrent(__DRIcontext * driContextPriv, 525d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIdrawable * driDrawPriv, 526d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsberg __DRIdrawable * driReadPriv); 527d61f07318c8678901b948fdaa8ccdf37aa3203e9Kristian Høgsbergextern void radeonDestroyContext(__DRIcontext * driContextPriv); 528646d2e9fbc41bf49075013009e9583bec4a51168Mario Kleinervoid radeon_prepare_render(radeonContextPtr radeon); 52923d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlie 5304637235183b80963536f2364e4d50fcb894886ddDave Airlie#endif 531