1b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch// Copyright 2013 the V8 project authors. All rights reserved. 2b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch// Use of this source code is governed by a BSD-style license that can be 3b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch// found in the LICENSE file. 4b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 5b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch// CPU specific code for arm independent of OS goes here. 6b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 7b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#if V8_TARGET_ARCH_ARM64 8b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 9b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#include "src/arm64/utils-arm64.h" 10b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#include "src/assembler.h" 11b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 12b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdochnamespace v8 { 13b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdochnamespace internal { 14b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 15b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdochclass CacheLineSizes { 16b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch public: 17b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch CacheLineSizes() { 18b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#ifdef USE_SIMULATOR 19b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch cache_type_register_ = 0; 20b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#else 21b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Copy the content of the cache type register to a core register. 22b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT 23b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch : [ctr] "=r" (cache_type_register_)); 24b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#endif 25b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch } 26b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 27b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uint32_t icache_line_size() const { return ExtractCacheLineSize(0); } 28b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); } 29b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 30b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch private: 31b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uint32_t ExtractCacheLineSize(int cache_line_size_shift) const { 32b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // The cache type register holds the size of cache lines in words as a 33b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // power of two. 34b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf); 35b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch } 36b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 37b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uint32_t cache_type_register_; 38b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch}; 39b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 40b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 41b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdochvoid CpuFeatures::FlushICache(void* address, size_t length) { 42014dc512cdd3e367bee49a713fdc5ed92584a3e5Ben Murdoch#ifdef V8_HOST_ARCH_ARM64 43b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // The code below assumes user space cache operations are allowed. The goal 44b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // of this routine is to make sure the code generated is visible to the I 45b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // side of the CPU. 46b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 47b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t start = reinterpret_cast<uintptr_t>(address); 48b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Sizes will be used to generate a mask big enough to cover a pointer. 49b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch CacheLineSizes sizes; 50b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t dsize = sizes.dcache_line_size(); 51b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t isize = sizes.icache_line_size(); 52b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Cache line sizes are always a power of 2. 53b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch DCHECK(CountSetBits(dsize, 64) == 1); 54b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch DCHECK(CountSetBits(isize, 64) == 1); 55b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t dstart = start & ~(dsize - 1); 56b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t istart = start & ~(isize - 1); 57b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch uintptr_t end = start + length; 58b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 59b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch __asm__ __volatile__ ( // NOLINT 60b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Clean every line of the D cache containing the target data. 61b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "0: \n\t" 62b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // dc : Data Cache maintenance 63b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // c : Clean 64b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // va : by (Virtual) Address 65b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // u : to the point of Unification 66b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // The point of unification for a processor is the point by which the 67b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // instruction and data caches are guaranteed to see the same copy of a 68b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // memory location. See ARM DDI 0406B page B2-12 for more information. 69b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "dc cvau, %[dline] \n\t" 70b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "add %[dline], %[dline], %[dsize] \n\t" 71b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "cmp %[dline], %[end] \n\t" 72b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "b.lt 0b \n\t" 73b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Barrier to make sure the effect of the code above is visible to the rest 74b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // of the world. 75b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // dsb : Data Synchronisation Barrier 76b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // ish : Inner SHareable domain 77b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // The point of unification for an Inner Shareable shareability domain is 78b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // the point by which the instruction and data caches of all the processors 79b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // in that Inner Shareable shareability domain are guaranteed to see the 80b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // same copy of a memory location. See ARM DDI 0406B page B2-12 for more 81b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // information. 82b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "dsb ish \n\t" 83b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Invalidate every line of the I cache containing the target data. 84b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "1: \n\t" 85b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // ic : instruction cache maintenance 86b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // i : invalidate 87b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // va : by address 88b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // u : to the point of unification 89b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "ic ivau, %[iline] \n\t" 90b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "add %[iline], %[iline], %[isize] \n\t" 91b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "cmp %[iline], %[end] \n\t" 92b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "b.lt 1b \n\t" 93b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Barrier to make sure the effect of the code above is visible to the rest 94b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // of the world. 95b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "dsb ish \n\t" 96b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // Barrier to ensure any prefetching which happened before this code is 97b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // discarded. 98b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // isb : Instruction Synchronisation Barrier 99b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch "isb \n\t" 100b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch : [dline] "+r" (dstart), 101b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch [iline] "+r" (istart) 102b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch : [dsize] "r" (dsize), 103b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch [isize] "r" (isize), 104b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch [end] "r" (end) 105b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // This code does not write to memory but without the dependency gcc might 106b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch // move this code before the code is generated. 107b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch : "cc", "memory" 108b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch ); // NOLINT 109014dc512cdd3e367bee49a713fdc5ed92584a3e5Ben Murdoch#endif // V8_HOST_ARCH_ARM64 110b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch} 111b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 112014dc512cdd3e367bee49a713fdc5ed92584a3e5Ben Murdoch} // namespace internal 113014dc512cdd3e367bee49a713fdc5ed92584a3e5Ben Murdoch} // namespace v8 114b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch 115b8a8cc1952d61a2f3a2568848933943a543b5d3eBen Murdoch#endif // V8_TARGET_ARCH_ARM64 116