pred_lt4_1_neon.s revision 74bc3e133bd59a65dbed70b5fc89549f04a545e2 
1@/*
2@ ** Copyright 2003-2010, VisualOn, Inc.
3@ **
4@ ** Licensed under the Apache License, Version 2.0 (the "License");
5@ ** you may not use this file except in compliance with the License.
6@ ** You may obtain a copy of the License at
7@ **
8@ **     http://www.apache.org/licenses/LICENSE-2.0
9@ **
10@ ** Unless required by applicable law or agreed to in writing, software
11@ ** distributed under the License is distributed on an "AS IS" BASIS,
12@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13@ ** See the License for the specific language governing permissions and
14@ ** limitations under the License.
15@ */
16@
17@void Pred_lt4(
18@     Word16 exc[],                         /* in/out: excitation buffer */
19@     Word16 T0,                            /* input : integer pitch lag */
20@     Word16 frac,                          /* input : fraction of lag   */
21@     Word16 L_subfr                        /* input : subframe size     */
22@)
23@***********************************************************************
24@ r0    ---  exc[]
25@ r1    ---  T0
26@ r2    ---  frac
27@ r3    ---  L_subfr
28
29          .section  .text
30          .global   pred_lt4_asm
31          .extern   inter4_2
32
33pred_lt4_asm:
34
35          STMFD   	r13!, {r4 - r12, r14}
36          SUB           r4, r0, r1, LSL #1                        @ x = exc - T0
37          RSB           r2, r2, #0                                @ frac = - frac
38          SUB           r4, r4, #30                               @ x -= L_INTERPOL2 - 1
39          CMP           r2, #0
40          ADDLT         r2, r2, #4                                @ frac += UP_SAMP
41          SUBLT         r4, r4, #2                                @ x--
42
43          ADR           r8, Lable1
44          LDR           r11, [r8]
45          ADD           r11, r8
46          RSB           r2, r2, #3                                @ k = UP_SAMP - 1 - frac
47          MOV           r8, #0                                    @ j = 0
48	  ADD           r11, r11, r2, LSL #6                      @ get inter4_2[k][]
49
50	  VLD1.S16      {Q0, Q1}, [r11]!
51	  VLD1.S16      {Q2, Q3}, [r11]!
52
53	  MOV           r6, #0x8000
54
55          VLD1.S16      {Q4, Q5}, [r4]!                           @load 16 x[]
56          VLD1.S16      {Q6, Q7}, [r4]!                           @load 16 x[]
57
58LOOP:
59          VQDMULL.S16   Q15, D8, D0
60          VQDMLAL.S16   Q15, D9, D1
61          VQDMLAL.S16   Q15, D10, D2
62          VQDMLAL.S16   Q15, D11, D3
63
64          VQDMLAL.S16   Q15, D12, D4
65          VQDMLAL.S16   Q15, D13, D5
66          VQDMLAL.S16   Q15, D14, D6
67          VQDMLAL.S16   Q15, D15, D7
68
69          LDRSH         r12, [r4], #2
70
71          VEXT.S16      D8, D8, D9, #1
72          VEXT.S16      D9, D9, D10, #1
73          VEXT.S16      D10, D10, D11, #1
74          VEXT.S16      D11, D11, D12, #1
75          VDUP.S16      D24, r12
76          VEXT.S16      D12, D12, D13, #1
77          VEXT.S16      D13, D13, D14, #1
78
79          VQADD.S32     D30, D30, D31
80	  MOV           r11, #0x8000
81          VPADD.S32     D30, D30, D30
82          ADD           r8, r8, #1
83          VMOV.S32      r12, D30[0]
84          VEXT.S16      D14, D14, D15, #1
85
86          QADD          r1, r12, r12                              @ L_sum = (L_sum << 2)
87          VEXT.S16      D15, D15, D24, #1
88          QADD          r5, r1, r6
89          MOV           r1, r5, ASR #16
90          CMP           r8, r3
91          STRH          r1, [r0], #2                              @ exc[j] = (L_sum + 0x8000) >> 16
92          BLT           LOOP
93
94pred_lt4_end:
95
96          LDMFD   	r13!, {r4 - r12, r15}
97
98Lable1:
99          .word   	inter4_2-Lable1
100          @ENDFUNC
101          .END
102
103