1/* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
13 * express or implied.
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
17 */
18/*********************************************************************************/
19/*  Filename: sad_halfpel_inline.h                                                      */
20/*  Description: Implementation for in-line functions used in dct.cpp           */
21/*  Modified:                                                                   */
22/*********************************************************************************/
23
24#ifndef _SAD_HALFPEL_INLINE_H_
25#define _SAD_HALFPEL_INLINE_H_
26
27#ifdef __cplusplus
28extern "C"
29{
30#endif
31
32#if !defined(PV_ARM_GCC_V5) && !defined(PV_ARM_GCC_V4) /* ARM GNU COMPILER  */
33
34    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
35    {
36        tmp = (tmp2 >> 1) - tmp;
37        if (tmp > 0) sad += tmp;
38        else sad -= tmp;
39
40        return sad;
41    }
42
43    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
44    {
45        tmp = (tmp >> 2) - tmp2;
46        if (tmp > 0) sad += tmp;
47        else sad -= tmp;
48
49        return sad;
50    }
51
52#elif defined(__CC_ARM)  /* only work with arm v5 */
53
54    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
55    {
56        __asm
57        {
58            rsbs    tmp, tmp, tmp2, asr #1 ;
59            rsbmi   tmp, tmp, #0 ;
60            add     sad, sad, tmp ;
61        }
62
63        return sad;
64    }
65
66    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
67    {
68        __asm
69        {
70            rsbs    tmp, tmp2, tmp, asr #2 ;
71            rsbmi   tmp, tmp, #0 ;
72            add     sad, sad, tmp ;
73        }
74
75        return sad;
76    }
77
78#elif ( defined(PV_ARM_GCC_V5) || defined(PV_ARM_GCC_V4) ) /* ARM GNU COMPILER  */
79
80
81    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
82    {
83        register int32 out;
84        register int32 temp1;
85        register int32 ss = sad;
86        register int32 tt = tmp;
87        register int32 uu = tmp2;
88
89        asm volatile("rsbs	%1, %3, %4, asr #1\n\t"
90                     "rsbmi %1, %1, #0\n\t"
91                     "add  %0, %2, %1"
92             : "=&r"(out),
93                     "=&r"(temp1)
94                             : "r"(ss),
95                             "r"(tt),
96                             "r"(uu));
97        return out;
98    }
99
100
101    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
102{
103        register int32 out;
104        register int32 temp1;
105        register int32 ss = sad;
106        register int32 tt = tmp;
107        register int32 uu = tmp2;
108
109        asm volatile("rsbs      %1, %4, %3, asr #2\n\t"
110                     "rsbmi %1, %1, #0\n\t"
111                     "add  %0, %2, %1"
112             : "=&r"(out),
113                     "=&r"(temp1)
114                             : "r"(ss),
115                             "r"(tt),
116                             "r"(uu));
117        return out;
118    }
119
120
121#endif // Diff OS
122
123
124
125#ifdef __cplusplus
126}
127#endif
128
129#endif //_SAD_HALFPEL_INLINE_H_
130
131