armVCM4P10_DecodeCoeffsToPair_s.S revision 97e3e847179c17eb9059fb322413b6facd3e5a03 
1/*
2 * (c) Copyright 2007-2008 ARM Limited. All Rights Reserved.
3 *
4 */
5
6    .eabi_attribute 24, 1
7    .eabi_attribute 25, 1
8
9    .arm
10    .fpu neon
11    .text
12
13    .extern   armVCM4P10_CAVLCCoeffTokenTables
14    .extern   armVCM4P10_SuffixToLevel
15    .extern   armVCM4P10_CAVLCTotalZeros2x2Tables
16    .extern   armVCM4P10_CAVLCTotalZeroTables
17    .extern   armVCM4P10_CAVLCRunBeforeTables
18    .extern   armVCM4P10_ZigZag_2x2
19    .extern   armVCM4P10_ZigZag_4x4
20
21    .hidden   armVCM4P10_CAVLCCoeffTokenTables
22    .hidden   armVCM4P10_SuffixToLevel
23    .hidden   armVCM4P10_CAVLCTotalZeros2x2Tables
24    .hidden   armVCM4P10_CAVLCTotalZeroTables
25    .hidden   armVCM4P10_CAVLCRunBeforeTables
26    .hidden   armVCM4P10_ZigZag_2x2
27    .hidden   armVCM4P10_ZigZag_4x4
28
29    .global armVCM4P10_DecodeCoeffsToPair
30    .func   armVCM4P10_DecodeCoeffsToPair
31armVCM4P10_DecodeCoeffsToPair:
32    PUSH     {r4-r12,lr}
33    SUB      sp,sp,#0x40
34    LDR      r10,[r0,#0]
35    LDR      r12,[r1,#0]
36    LDR      r6, .LarmVCM4P10_CAVLCCoeffTokenTables
37P0: ADD      r6, pc
38    LDR      r4,[sp,#0x68]
39    LDRB     r9,[r10,#2]
40    LDRB     r8,[r10,#1]
41    LDRB     r11,[r10],#3
42    ADD      r12,r12,#8
43    LDR      r6,[r6,r4,LSL #2]
44    ORR      r9,r9,r8,LSL #8
45    ORR      r11,r9,r11,LSL #16
46    LSLS     r8,r11,r12
47    MOVS     r7,#0x1e
48    AND      r7,r7,r8,LSR #27
49    SUBS     r12,r12,#8
50L0x44:
51    BCC      L1
52    LDRB     r8,[r10],#1
53L1:
54    LDRH     r7,[r6,r7]
55    ADDCC    r12,r12,#8
56    ADD      r12,r12,#4
57    ORRCS    r11,r8,r11,LSL #8
58    LSRS     r8,r7,#1
59    BCS      L0x74
60    LSLS     r8,r11,r12
61    SUBS     r12,r12,#0xa
62    ADD      r7,r7,r8,LSR #29
63    BIC      r7,r7,#1
64    B        L0x44
65L0x74:
66    SUB      r12,r12,r7,LSR #13
67    BIC      r7,r8,#0xf000
68    LSRS     r5,r7,#2
69    STRB     r5,[r2,#0]
70    BEQ      L0x344
71    CMP      r7,#0x44
72    BGE      L0x33c
73    STR      r0,[sp,#0]
74    STR      r1,[sp,#4]
75    STR      r3,[sp,#8]
76    ANDS     r1,r7,#3
77    ADD      r2,sp,#0xc
78    BEQ      L0xd8
79    MOV      r0,r1
80L0xac:
81    LSLS     r7,r11,r12
82    SUBS     r12,r12,#7
83    BCC      L2
84    LDRB     r8,[r10],#1
85L2:
86    ADDCC    r12,r12,#8
87    LSR      r7,r7,#31
88    ORRCS    r11,r8,r11,LSL #8
89    SUBS     r0,r0,#1
90    MOV      r8,#1
91    SUB      r8,r8,r7,LSL #1
92    STRH     r8,[r2],#2
93    BGT      L0xac
94L0xd8:
95    SUBS     r0,r5,r1
96    BEQ      L0x1b8
97    MOV      r4,#1
98    CMP      r5,#0xa
99    MOVLE    r4,#0
100    CMP      r1,#3
101    MOVLT    r1,#4
102    MOVGE    r1,#2
103    MOVGE    r4,#0
104L0xfc:
105    LSLS     r7,r11,r12
106    CLZ      r7,r7
107    ADD      r12,r12,r7
108    SUBS     r12,r12,#7
109    BCC      L3
110    LDRB     r8,[r10],#1
111    ORR      r11,r8,r11,LSL #8
112    SUBS     r12,r12,#8
113    BCC      L3
114    LDRB     r8,[r10],#1
115L3:
116    ADDCC    r12,r12,#8
117    ORRCS    r11,r8,r11,LSL #8
118    CMP      r7,#0x10
119    BGE      L0x33c
120    MOVS     lr,r4
121    TEQEQ    r7,#0xe
122    MOVEQ    lr,#4
123    TEQ      r7,#0xf
124    MOVEQ    lr,#0xc
125    TEQEQ    r4,#0
126    ADDEQ    r7,r7,#0xf
127    TEQ      lr,#0
128    BEQ      L0x184
129    LSL      r3,r11,r12
130    ADD      r12,r12,lr
131    SUBS     r12,r12,#8
132    RSB      r9,lr,#0x20
133    BCC      L4
134    LDRB     r8,[r10],#1
135    ORR      r11,r8,r11,LSL #8
136    SUBS     r12,r12,#8
137    BCC      L4
138    LDRB     r8,[r10],#1
139L4:
140    ADDCC    r12,r12,#8
141    LSR      r3,r3,r9
142    ORRCS    r11,r8,r11,LSL #8
143    LSL      r7,r7,r4
144    ADD      r7,r3,r7
145L0x184:
146    ADD      r7,r7,r1
147    MOV      r1,#2
148    LSRS     r8,r7,#1
149    RSBCS    r8,r8,#0
150    STRH     r8,[r2],#2
151    LDR      r9, .LarmVCM4P10_SuffixToLevel
152P1: ADD      r9, pc
153    LDRSB    r8,[r9,r4]
154    TEQ      r4,#0
155    MOVEQ    r4,#1
156    CMP      r7,r8
157    ADDCS    r4,r4,#1
158    SUBS     r0,r0,#1
159    BGT      L0xfc
160L0x1b8:
161    LDR      r8,[sp,#0x6c]
162    SUB      r0,r5,#1
163    SUBS     r1,r8,r5
164    ADD      r4,sp,#0x2c
165    MOV      lr,r5
166    SUB      lr,lr,#1
167    BEQ      L0x2b0
168    TEQ      r8,#4
169    LDREQ    r6, .LarmVCM4P10_CAVLCTotalZeros2x2Tables
170    LDRNE    r6, .LarmVCM4P10_CAVLCTotalZeroTables
171P2: ADD      r6, pc
172    LDR      r6,[r6,r5,LSL #2]
173    LSLS     r8,r11,r12
174    MOVS     r7,#0x1e
175    AND      r7,r7,r8,LSR #27
176    SUBS     r12,r12,#8
177L0x1f4:
178    BCC      L5
179    LDRB     r8,[r10],#1
180L5:
181    LDRH     r7,[r6,r7]
182    ADDCC    r12,r12,#8
183    ADD      r12,r12,#4
184    ORRCS    r11,r8,r11,LSL #8
185    LSRS     r8,r7,#1
186    BCS      L0x224
187    LSLS     r8,r11,r12
188    SUBS     r12,r12,#0xa
189    ADD      r7,r7,r8,LSR #29
190    BIC      r7,r7,#1
191    B        L0x1f4
192L0x224:
193    SUB      r12,r12,r7,LSR #13
194    BIC      r7,r8,#0xf000
195    CMP      r7,#0x10
196    BGE      L0x33c
197    LDR      r3, .LarmVCM4P10_CAVLCRunBeforeTables
198P3: ADD      r3, pc
199    ADD      r4,sp,#0x2c
200    MOVS     r1,r7
201    ADD      lr,lr,r1
202    BEQ      L0x2b0
203L0x248:
204    SUBS     r0,r0,#1
205    LDR      r6,[r3,r1,LSL #2]
206    BLT      L0x2bc
207    LSLS     r8,r11,r12
208    MOVS     r7,#0xe
209    AND      r7,r7,r8,LSR #28
210    SUBS     r12,r12,#8
211L0x264:
212    BCC      L6
213    LDRB     r8,[r10],#1
214L6:
215    LDRH     r7,[r6,r7]
216    ADDCC    r12,r12,#8
217    ADD      r12,r12,#3
218    ORRCS    r11,r8,r11,LSL #8
219    LSRS     r8,r7,#1
220    BCS      L0x294
221    LSLS     r8,r11,r12
222    SUBS     r12,r12,#9
223    ADD      r7,r7,r8,LSR #29
224    BIC      r7,r7,#1
225    B        L0x264
226L0x294:
227    SUB      r12,r12,r7,LSR #13
228    BIC      r7,r8,#0xf000
229    CMP      r7,#0xf
230    BGE      L0x33c
231    SUBS     r1,r1,r7
232    STRB     r7,[r4],#1
233    BGT      L0x248
234L0x2b0:
235    SUBS     r0,r0,#1
236    BLT      L7
237    STRB     r1,[r4],#1
238L7:
239    BGT      L0x2b0
240L0x2bc:
241    STRB     r1,[r4],#1
242    LDR      r8,[sp,#0x6c]
243    TEQ      r8,#0xf
244    ADDEQ    lr,lr,#1
245    SUB      r4,r4,r5
246    SUB      r2,r2,r5
247    SUB      r2,r2,r5
248    LDR      r3,[sp,#8]
249    LDR      r0,[r3,#0]
250    TEQ      r8,#4
251    LDREQ    r6, .LarmVCM4P10_ZigZag_2x2
252    LDRNE    r6, .LarmVCM4P10_ZigZag_4x4
253P4: ADD      r6, pc
254L0x2ec:
255    LDRB     r9,[r4],#1
256    LDRB     r8,[r6,lr]
257    SUB      lr,lr,#1
258    SUB      lr,lr,r9
259    LDRSH    r9,[r2],#2
260    SUBS     r5,r5,#1
261    ORREQ    r8,r8,#0x20
262    ADD      r1,r9,#0x80
263    CMP      r1,#0x100
264    ORRCS    r8,r8,#0x10
265    TEQ      r5,#0
266    STRB     r8,[r0],#1
267    STRB     r9,[r0],#1
268    LSR      r9,r9,#8
269    BCC      L8
270    STRB     r9,[r0],#1
271L8:
272    BNE      L0x2ec
273    STR      r0,[r3,#0]
274    LDR      r0,[sp,#0]
275    LDR      r1,[sp,#4]
276    B        L0x344
277L0x33c:
278    MVN      r0,#1
279    B        L0x35c
280L0x344:
281    ADD      r10,r10,r12,LSR #3
282    AND      r12,r12,#7
283    SUB      r10,r10,#4
284    STR      r12,[r1,#0]
285    STR      r10,[r0,#0]
286    MOV      r0,#0
287L0x35c:
288    ADD      sp,sp,#0x40
289    POP      {r4-r12,pc}
290    .endfunc
291
292.LarmVCM4P10_CAVLCCoeffTokenTables:
293    .word   armVCM4P10_CAVLCCoeffTokenTables-(P0+8)
294.LarmVCM4P10_SuffixToLevel:
295    .word   armVCM4P10_SuffixToLevel-(P1+8)
296.LarmVCM4P10_CAVLCTotalZeros2x2Tables:
297    .word   (armVCM4P10_CAVLCTotalZeros2x2Tables - 4)-(P2+8)
298.LarmVCM4P10_CAVLCTotalZeroTables:
299    .word   (armVCM4P10_CAVLCTotalZeroTables - 4)-(P2+8)
300.LarmVCM4P10_CAVLCRunBeforeTables:
301    .word   (armVCM4P10_CAVLCRunBeforeTables - 4)-(P3+8)
302.LarmVCM4P10_ZigZag_2x2:
303    .word   armVCM4P10_ZigZag_2x2-(P4+8)
304.LarmVCM4P10_ZigZag_4x4:
305    .word   armVCM4P10_ZigZag_4x4-(P4+8)
306
307    .end
308