allocation.ll revision be46aa62ed595c517dbf236dfbb3d22e1c194907
1target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" 2target triple = "aarch64-none-linux-gnueabi" 3 4declare i8* @rsOffset([1 x i64] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z) 5declare i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) 6 7; The loads and stores in this file are annotated with RenderScript-specific 8; information for the type based alias analysis, such that the TBAA analysis 9; understands that loads and stores from two allocations with different types 10; can never access the same memory element. This is different from C, where 11; a char or uchar load/store is special as it can alias with about everything. 12; 13; The TBAA tree in this file has the the node "RenderScript TBAA" as its root. 14; This means all loads/stores that share this common root can be proven to not 15; alias. However, the alias analysis still has to assume MayAlias between 16; memory accesses in this file and memory accesses annotated with the C/C++ 17; TBAA metadata. 18; If we can ensure that all accesses to elements loaded from RenderScript 19; allocations are either annotated with the RenderScript TBAA information or 20; not annotated at all, but never annotated with the C/C++ metadata, we 21; can add the RenderScript TBAA tree under the C/C++ TBAA tree. This enables 22; then the TBAA to prove that an access to data from the RenderScript allocation 23; does not alias with a load/store accessing something not part of a RenderScript 24; allocation. 25 26 27!14 = metadata !{metadata !"RenderScript TBAA"} 28!15 = metadata !{metadata !"allocation", metadata !14} 29 30!21 = metadata !{metadata !"char", metadata !15} 31define void @rsSetElementAtImpl_char([1 x i64] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) #2 { 32 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10 33 store i8 %val, i8* %1, align 1, !tbaa !21 34 ret void 35} 36 37define signext i8 @rsGetElementAtImpl_char([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 38 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10 39 %2 = load i8* %1, align 1, !tbaa !21 40 ret i8 %2 41} 42 43!22 = metadata !{metadata !"char2", metadata !15} 44define void @rsSetElementAtImpl_char2([1 x i64] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 45 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 46 %2 = bitcast i8* %1 to <2 x i8>* 47 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !22 48 ret void 49} 50 51define <2 x i8> @rsGetElementAtImpl_char2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 52 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 53 %2 = bitcast i8* %1 to <2 x i8>* 54 %3 = load <2 x i8>* %2, align 2, !tbaa !22 55 ret <2 x i8> %3 56} 57 58!23 = metadata !{metadata !"char3", metadata !15} 59define void @rsSetElementAtImpl_char3([1 x i64] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 60 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 61 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 62 %3 = bitcast i8* %1 to <4 x i8>* 63 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !23 64 ret void 65} 66 67define <3 x i8> @rsGetElementAtImpl_char3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 68 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 69 %2 = bitcast i8* %1 to <4 x i8>* 70 %3 = load <4 x i8>* %2, align 4, !tbaa !23 71 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 72 ret <3 x i8> %4 73} 74 75!24 = metadata !{metadata !"char4", metadata !15} 76define void @rsSetElementAtImpl_char4([1 x i64] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 77 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 78 %2 = bitcast i8* %1 to <4 x i8>* 79 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !24 80 ret void 81} 82 83define <4 x i8> @rsGetElementAtImpl_char4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 84 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 85 %2 = bitcast i8* %1 to <4 x i8>* 86 %3 = load <4 x i8>* %2, align 4, !tbaa !24 87 ret <4 x i8> %3 88} 89 90!25 = metadata !{metadata !"uchar", metadata !15} 91define void @rsSetElementAtImpl_uchar([1 x i64] %a.coerce, i8 zeroext %val, i32 %x, i32 %y, i32 %z) #2 { 92 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10 93 store i8 %val, i8* %1, align 1, !tbaa !25 94 ret void 95} 96 97define zeroext i8 @rsGetElementAtImpl_uchar([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 98 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10 99 %2 = load i8* %1, align 1, !tbaa !25 100 ret i8 %2 101} 102 103!26 = metadata !{metadata !"uchar2", metadata !15} 104define void @rsSetElementAtImpl_uchar2([1 x i64] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 105 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 106 %2 = bitcast i8* %1 to <2 x i8>* 107 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !26 108 ret void 109} 110 111define <2 x i8> @rsGetElementAtImpl_uchar2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 112 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 113 %2 = bitcast i8* %1 to <2 x i8>* 114 %3 = load <2 x i8>* %2, align 2, !tbaa !26 115 ret <2 x i8> %3 116} 117 118!27 = metadata !{metadata !"uchar3", metadata !15} 119define void @rsSetElementAtImpl_uchar3([1 x i64] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 120 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 121 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 122 %3 = bitcast i8* %1 to <4 x i8>* 123 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !27 124 ret void 125} 126 127define <3 x i8> @rsGetElementAtImpl_uchar3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 128 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 129 %2 = bitcast i8* %1 to <4 x i8>* 130 %3 = load <4 x i8>* %2, align 4, !tbaa !27 131 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 132 ret <3 x i8> %4 133} 134 135!28 = metadata !{metadata !"uchar4", metadata !15} 136define void @rsSetElementAtImpl_uchar4([1 x i64] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #2 { 137 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 138 %2 = bitcast i8* %1 to <4 x i8>* 139 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !28 140 ret void 141} 142 143define <4 x i8> @rsGetElementAtImpl_uchar4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 144 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 145 %2 = bitcast i8* %1 to <4 x i8>* 146 %3 = load <4 x i8>* %2, align 4, !tbaa !28 147 ret <4 x i8> %3 148} 149 150!29 = metadata !{metadata !"short", metadata !15} 151define void @rsSetElementAtImpl_short([1 x i64] %a.coerce, i16 signext %val, i32 %x, i32 %y, i32 %z) #2 { 152 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 153 %2 = bitcast i8* %1 to i16* 154 store i16 %val, i16* %2, align 2, !tbaa !29 155 ret void 156} 157 158define signext i16 @rsGetElementAtImpl_short([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 159 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 160 %2 = bitcast i8* %1 to i16* 161 %3 = load i16* %2, align 2, !tbaa !29 162 ret i16 %3 163} 164 165!30 = metadata !{metadata !"short2", metadata !15} 166define void @rsSetElementAtImpl_short2([1 x i64] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 167 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 168 %2 = bitcast i8* %1 to <2 x i16>* 169 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !30 170 ret void 171} 172 173define <2 x i16> @rsGetElementAtImpl_short2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 174 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 175 %2 = bitcast i8* %1 to <2 x i16>* 176 %3 = load <2 x i16>* %2, align 4, !tbaa !30 177 ret <2 x i16> %3 178} 179 180!31 = metadata !{metadata !"short3", metadata !15} 181define void @rsSetElementAtImpl_short3([1 x i64] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 182 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 183 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 184 %3 = bitcast i8* %1 to <4 x i16>* 185 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !31 186 ret void 187} 188 189define <3 x i16> @rsGetElementAtImpl_short3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 190 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 191 %2 = bitcast i8* %1 to <4 x i16>* 192 %3 = load <4 x i16>* %2, align 8, !tbaa !31 193 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 194 ret <3 x i16> %4 195} 196 197!32 = metadata !{metadata !"short4", metadata !15} 198define void @rsSetElementAtImpl_short4([1 x i64] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 199 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 200 %2 = bitcast i8* %1 to <4 x i16>* 201 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !32 202 ret void 203} 204 205define <4 x i16> @rsGetElementAtImpl_short4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 206 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 207 %2 = bitcast i8* %1 to <4 x i16>* 208 %3 = load <4 x i16>* %2, align 8, !tbaa !32 209 ret <4 x i16> %3 210} 211 212!33 = metadata !{metadata !"ushort", metadata !15} 213define void @rsSetElementAtImpl_ushort([1 x i64] %a.coerce, i16 zeroext %val, i32 %x, i32 %y, i32 %z) #2 { 214 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 215 %2 = bitcast i8* %1 to i16* 216 store i16 %val, i16* %2, align 2, !tbaa !33 217 ret void 218} 219 220define zeroext i16 @rsGetElementAtImpl_ushort([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 221 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10 222 %2 = bitcast i8* %1 to i16* 223 %3 = load i16* %2, align 2, !tbaa !33 224 ret i16 %3 225} 226 227!34 = metadata !{metadata !"ushort2", metadata !15} 228define void @rsSetElementAtImpl_ushort2([1 x i64] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 229 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 230 %2 = bitcast i8* %1 to <2 x i16>* 231 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !34 232 ret void 233} 234 235define <2 x i16> @rsGetElementAtImpl_ushort2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 236 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 237 %2 = bitcast i8* %1 to <2 x i16>* 238 %3 = load <2 x i16>* %2, align 4, !tbaa !34 239 ret <2 x i16> %3 240} 241 242!35 = metadata !{metadata !"ushort3", metadata !15} 243define void @rsSetElementAtImpl_ushort3([1 x i64] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 244 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 245 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 246 %3 = bitcast i8* %1 to <4 x i16>* 247 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !35 248 ret void 249} 250 251define <3 x i16> @rsGetElementAtImpl_ushort3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 252 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 253 %2 = bitcast i8* %1 to <4 x i16>* 254 %3 = load <4 x i16>* %2, align 8, !tbaa !35 255 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 256 ret <3 x i16> %4 257} 258 259!36 = metadata !{metadata !"ushort4", metadata !15} 260define void @rsSetElementAtImpl_ushort4([1 x i64] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #2 { 261 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 262 %2 = bitcast i8* %1 to <4 x i16>* 263 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !36 264 ret void 265} 266 267define <4 x i16> @rsGetElementAtImpl_ushort4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 268 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 269 %2 = bitcast i8* %1 to <4 x i16>* 270 %3 = load <4 x i16>* %2, align 8, !tbaa !36 271 ret <4 x i16> %3 272} 273 274!37 = metadata !{metadata !"int", metadata !15} 275define void @rsSetElementAtImpl_int([1 x i64] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #2 { 276 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 277 %2 = bitcast i8* %1 to i32* 278 store i32 %val, i32* %2, align 4, !tbaa !37 279 ret void 280} 281 282define i32 @rsGetElementAtImpl_int([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 283 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 284 %2 = bitcast i8* %1 to i32* 285 %3 = load i32* %2, align 4, !tbaa !37 286 ret i32 %3 287} 288 289!38 = metadata !{metadata !"int2", metadata !15} 290define void @rsSetElementAtImpl_int2([1 x i64] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 291 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 292 %2 = bitcast i8* %1 to <2 x i32>* 293 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !38 294 ret void 295} 296 297define <2 x i32> @rsGetElementAtImpl_int2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 298 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 299 %2 = bitcast i8* %1 to <2 x i32>* 300 %3 = load <2 x i32>* %2, align 8, !tbaa !38 301 ret <2 x i32> %3 302} 303 304!39 = metadata !{metadata !"int3", metadata !15} 305define void @rsSetElementAtImpl_int3([1 x i64] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 306 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 307 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 308 %3 = bitcast i8* %1 to <4 x i32>* 309 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !39 310 ret void 311} 312 313define <3 x i32> @rsGetElementAtImpl_int3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 314 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 315 %2 = bitcast i8* %1 to <4 x i32>* 316 %3 = load <4 x i32>* %2, align 8, !tbaa !39 317 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 318 ret <3 x i32> %4 319} 320 321!40 = metadata !{metadata !"int4", metadata !15} 322define void @rsSetElementAtImpl_int4([1 x i64] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 323 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 324 %2 = bitcast i8* %1 to <4 x i32>* 325 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !40 326 ret void 327} 328 329define <4 x i32> @rsGetElementAtImpl_int4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 330 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 331 %2 = bitcast i8* %1 to <4 x i32>* 332 %3 = load <4 x i32>* %2, align 16, !tbaa !40 333 ret <4 x i32> %3 334} 335 336!41 = metadata !{metadata !"uint", metadata !15} 337define void @rsSetElementAtImpl_uint([1 x i64] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #2 { 338 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 339 %2 = bitcast i8* %1 to i32* 340 store i32 %val, i32* %2, align 4, !tbaa !41 341 ret void 342} 343 344define i32 @rsGetElementAtImpl_uint([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 345 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 346 %2 = bitcast i8* %1 to i32* 347 %3 = load i32* %2, align 4, !tbaa !41 348 ret i32 %3 349} 350 351!42 = metadata !{metadata !"uint2", metadata !15} 352define void @rsSetElementAtImpl_uint2([1 x i64] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 353 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 354 %2 = bitcast i8* %1 to <2 x i32>* 355 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !42 356 ret void 357} 358 359define <2 x i32> @rsGetElementAtImpl_uint2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 360 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 361 %2 = bitcast i8* %1 to <2 x i32>* 362 %3 = load <2 x i32>* %2, align 8, !tbaa !42 363 ret <2 x i32> %3 364} 365 366!43 = metadata !{metadata !"uint3", metadata !15} 367define void @rsSetElementAtImpl_uint3([1 x i64] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 368 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 369 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 370 %3 = bitcast i8* %1 to <4 x i32>* 371 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !43 372 ret void 373} 374 375define <3 x i32> @rsGetElementAtImpl_uint3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 376 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 377 %2 = bitcast i8* %1 to <4 x i32>* 378 %3 = load <4 x i32>* %2, align 8, !tbaa !43 379 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 380 ret <3 x i32> %4 381} 382 383!44 = metadata !{metadata !"uint4", metadata !15} 384define void @rsSetElementAtImpl_uint4([1 x i64] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #2 { 385 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 386 %2 = bitcast i8* %1 to <4 x i32>* 387 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !44 388 ret void 389} 390 391define <4 x i32> @rsGetElementAtImpl_uint4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 392 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 393 %2 = bitcast i8* %1 to <4 x i32>* 394 %3 = load <4 x i32>* %2, align 16, !tbaa !44 395 ret <4 x i32> %3 396} 397 398!45 = metadata !{metadata !"long", metadata !15} 399define void @rsSetElementAtImpl_long([1 x i64] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #2 { 400 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 401 %2 = bitcast i8* %1 to i64* 402 store i64 %val, i64* %2, align 8, !tbaa !45 403 ret void 404} 405 406define i64 @rsGetElementAtImpl_long([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 407 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 408 %2 = bitcast i8* %1 to i64* 409 %3 = load i64* %2, align 8, !tbaa !45 410 ret i64 %3 411} 412 413!46 = metadata !{metadata !"long2", metadata !15} 414define void @rsSetElementAtImpl_long2([1 x i64] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 415 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 416 %2 = bitcast i8* %1 to <2 x i64>* 417 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !46 418 ret void 419} 420 421define <2 x i64> @rsGetElementAtImpl_long2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 422 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 423 %2 = bitcast i8* %1 to <2 x i64>* 424 %3 = load <2 x i64>* %2, align 16, !tbaa !46 425 ret <2 x i64> %3 426} 427 428!47 = metadata !{metadata !"long3", metadata !15} 429define void @rsSetElementAtImpl_long3([1 x i64] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 430 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 431 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 432 %3 = bitcast i8* %1 to <4 x i64>* 433 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !47 434 ret void 435} 436 437define void @rsGetElementAtImpl_long3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 438 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 439 %2 = bitcast i8* %1 to <4 x i64>* 440 %3 = load <4 x i64>* %2, align 32 441 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 442 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !47 443 ret void 444} 445 446!48 = metadata !{metadata !"long4", metadata !15} 447define void @rsSetElementAtImpl_long4([1 x i64] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 448 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 449 %2 = bitcast i8* %1 to <4 x i64>* 450 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !48 451 ret void 452} 453 454define void @rsGetElementAtImpl_long4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 455 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 456 %2 = bitcast i8* %1 to <4 x i64>* 457 %3 = load <4 x i64>* %2, align 32, !tbaa !15 458 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !48 459 ret void 460} 461 462!49 = metadata !{metadata !"ulong", metadata !15} 463define void @rsSetElementAtImpl_ulong([1 x i64] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #2 { 464 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 465 %2 = bitcast i8* %1 to i64* 466 store i64 %val, i64* %2, align 8, !tbaa !49 467 ret void 468} 469 470define i64 @rsGetElementAtImpl_ulong([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 471 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 472 %2 = bitcast i8* %1 to i64* 473 %3 = load i64* %2, align 8, !tbaa !49 474 ret i64 %3 475} 476 477!50 = metadata !{metadata !"ulong2", metadata !15} 478define void @rsSetElementAtImpl_ulong2([1 x i64] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 479 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 480 %2 = bitcast i8* %1 to <2 x i64>* 481 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !50 482 ret void 483} 484 485define <2 x i64> @rsGetElementAtImpl_ulong2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 486 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 487 %2 = bitcast i8* %1 to <2 x i64>* 488 %3 = load <2 x i64>* %2, align 16, !tbaa !50 489 ret <2 x i64> %3 490} 491 492!51 = metadata !{metadata !"ulong3", metadata !15} 493define void @rsSetElementAtImpl_ulong3([1 x i64] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 494 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 495 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 496 %3 = bitcast i8* %1 to <4 x i64>* 497 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !51 498 ret void 499} 500 501define void @rsGetElementAtImpl_ulong3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 502 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 503 %2 = bitcast i8* %1 to <4 x i64>* 504 %3 = load <4 x i64>* %2, align 32 505 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 506 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !51 507 ret void 508} 509 510!52 = metadata !{metadata !"ulong4", metadata !15} 511define void @rsSetElementAtImpl_ulong4([1 x i64] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #2 { 512 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 513 %2 = bitcast i8* %1 to <4 x i64>* 514 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !52 515 ret void 516} 517 518define void @rsGetElementAtImpl_ulong4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 519 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 520 %2 = bitcast i8* %1 to <4 x i64>* 521 %3 = load <4 x i64>* %2, align 32, !tbaa !15 522 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !52 523 ret void 524} 525 526!53 = metadata !{metadata !"float", metadata !15} 527define void @rsSetElementAtImpl_float([1 x i64] %a.coerce, float %val, i32 %x, i32 %y, i32 %z) #2 { 528 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 529 %2 = bitcast i8* %1 to float* 530 store float %val, float* %2, align 4, !tbaa !53 531 ret void 532} 533 534define float @rsGetElementAtImpl_float([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 535 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #10 536 %2 = bitcast i8* %1 to float* 537 %3 = load float* %2, align 4, !tbaa !53 538 ret float %3 539} 540 541!54 = metadata !{metadata !"float2", metadata !15} 542define void @rsSetElementAtImpl_float2([1 x i64] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #2 { 543 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 544 %2 = bitcast i8* %1 to <2 x float>* 545 store <2 x float> %val, <2 x float>* %2, align 8, !tbaa !54 546 ret void 547} 548 549define <2 x float> @rsGetElementAtImpl_float2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 550 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 551 %2 = bitcast i8* %1 to <2 x float>* 552 %3 = load <2 x float>* %2, align 8, !tbaa !54 553 ret <2 x float> %3 554} 555 556!55 = metadata !{metadata !"float3", metadata !15} 557define void @rsSetElementAtImpl_float3([1 x i64] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #2 { 558 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 559 %2 = shufflevector <3 x float> %val, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 560 %3 = bitcast i8* %1 to <4 x float>* 561 store <4 x float> %2, <4 x float>* %3, align 16, !tbaa !55 562 ret void 563} 564 565define <3 x float> @rsGetElementAtImpl_float3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 566 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 567 %2 = bitcast i8* %1 to <4 x float>* 568 %3 = load <4 x float>* %2, align 8, !tbaa !55 569 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 570 ret <3 x float> %4 571} 572 573!56 = metadata !{metadata !"float4", metadata !15} 574define void @rsSetElementAtImpl_float4([1 x i64] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #2 { 575 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 576 %2 = bitcast i8* %1 to <4 x float>* 577 store <4 x float> %val, <4 x float>* %2, align 16, !tbaa !56 578 ret void 579} 580 581define <4 x float> @rsGetElementAtImpl_float4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 582 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 583 %2 = bitcast i8* %1 to <4 x float>* 584 %3 = load <4 x float>* %2, align 16, !tbaa !56 585 ret <4 x float> %3 586} 587 588!57 = metadata !{metadata !"double", metadata !15} 589define void @rsSetElementAtImpl_double([1 x i64] %a.coerce, double %val, i32 %x, i32 %y, i32 %z) #2 { 590 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 591 %2 = bitcast i8* %1 to double* 592 store double %val, double* %2, align 8, !tbaa !57 593 ret void 594} 595 596define double @rsGetElementAtImpl_double([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 597 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #10 598 %2 = bitcast i8* %1 to double* 599 %3 = load double* %2, align 8, !tbaa !57 600 ret double %3 601} 602 603!58 = metadata !{metadata !"double2", metadata !15} 604define void @rsSetElementAtImpl_double2([1 x i64] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #2 { 605 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 606 %2 = bitcast i8* %1 to <2 x double>* 607 store <2 x double> %val, <2 x double>* %2, align 16, !tbaa !58 608 ret void 609} 610 611define <2 x double> @rsGetElementAtImpl_double2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #3 { 612 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #10 613 %2 = bitcast i8* %1 to <2 x double>* 614 %3 = load <2 x double>* %2, align 16, !tbaa !58 615 ret <2 x double> %3 616} 617 618!59 = metadata !{metadata !"double3", metadata !15} 619define void @rsSetElementAtImpl_double3([1 x i64] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #2 { 620 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 621 %2 = shufflevector <3 x double> %val, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 622 %3 = bitcast i8* %1 to <4 x double>* 623 store <4 x double> %2, <4 x double>* %3, align 32, !tbaa !59 624 ret void 625} 626 627 628define void @rsGetElementAtImpl_double3(<3 x double>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 629 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 630 %2 = bitcast i8* %1 to <4 x double>* 631 %3 = load <4 x double>* %2, align 32 632 %4 = bitcast <3 x double>* %agg.result to <4 x double>* 633 store <4 x double> %3, <4 x double>* %4, align 32, !tbaa !59 634 ret void 635} 636 637!60 = metadata !{metadata !"double4", metadata !15} 638define void @rsSetElementAtImpl_double4([1 x i64] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #2 { 639 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 640 %2 = bitcast i8* %1 to <4 x double>* 641 store <4 x double> %val, <4 x double>* %2, align 32, !tbaa !60 642 ret void 643} 644define void @rsGetElementAtImpl_double4(<4 x double>* noalias nocapture sret %agg.result, [1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #2 { 645 %1 = tail call i8* @rsOffset([1 x i64] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #10 646 %2 = bitcast i8* %1 to <4 x double>* 647 %3 = load <4 x double>* %2, align 32, !tbaa !15 648 store <4 x double> %3, <4 x double>* %agg.result, align 32, !tbaa !60 649 ret void 650} 651 652 653define <4 x i64> @__rsAllocationVLoadXImpl_long4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 654 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 655 %2 = bitcast i8* %1 to <4 x i64>* 656 %3 = load <4 x i64>* %2, align 8 657 ret <4 x i64> %3 658} 659define <3 x i64> @__rsAllocationVLoadXImpl_long3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 660 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 661 %2 = bitcast i8* %1 to <3 x i64>* 662 %3 = load <3 x i64>* %2, align 8 663 ret <3 x i64> %3 664} 665define <2 x i64> @__rsAllocationVLoadXImpl_long2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 666 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 667 %2 = bitcast i8* %1 to <2 x i64>* 668 %3 = load <2 x i64>* %2, align 8 669 ret <2 x i64> %3 670} 671 672define <4 x i64> @__rsAllocationVLoadXImpl_ulong4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 673 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 674 %2 = bitcast i8* %1 to <4 x i64>* 675 %3 = load <4 x i64>* %2, align 8 676 ret <4 x i64> %3 677} 678define <3 x i64> @__rsAllocationVLoadXImpl_ulong3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 679 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 680 %2 = bitcast i8* %1 to <3 x i64>* 681 %3 = load <3 x i64>* %2, align 8 682 ret <3 x i64> %3 683} 684define <2 x i64> @__rsAllocationVLoadXImpl_ulong2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 685 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 686 %2 = bitcast i8* %1 to <2 x i64>* 687 %3 = load <2 x i64>* %2, align 8 688 ret <2 x i64> %3 689} 690 691define <4 x i32> @__rsAllocationVLoadXImpl_int4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 692 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 693 %2 = bitcast i8* %1 to <4 x i32>* 694 %3 = load <4 x i32>* %2, align 4 695 ret <4 x i32> %3 696} 697define <3 x i32> @__rsAllocationVLoadXImpl_int3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 698 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 699 %2 = bitcast i8* %1 to <3 x i32>* 700 %3 = load <3 x i32>* %2, align 4 701 ret <3 x i32> %3 702} 703define <2 x i32> @__rsAllocationVLoadXImpl_int2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 704 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 705 %2 = bitcast i8* %1 to <2 x i32>* 706 %3 = load <2 x i32>* %2, align 4 707 ret <2 x i32> %3 708} 709 710define <4 x i32> @__rsAllocationVLoadXImpl_uint4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 711 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 712 %2 = bitcast i8* %1 to <4 x i32>* 713 %3 = load <4 x i32>* %2, align 4 714 ret <4 x i32> %3 715} 716define <3 x i32> @__rsAllocationVLoadXImpl_uint3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 717 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 718 %2 = bitcast i8* %1 to <3 x i32>* 719 %3 = load <3 x i32>* %2, align 4 720 ret <3 x i32> %3 721} 722define <2 x i32> @__rsAllocationVLoadXImpl_uint2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 723 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 724 %2 = bitcast i8* %1 to <2 x i32>* 725 %3 = load <2 x i32>* %2, align 4 726 ret <2 x i32> %3 727} 728 729define <4 x i16> @__rsAllocationVLoadXImpl_short4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 730 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 731 %2 = bitcast i8* %1 to <4 x i16>* 732 %3 = load <4 x i16>* %2, align 2 733 ret <4 x i16> %3 734} 735define <3 x i16> @__rsAllocationVLoadXImpl_short3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 736 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 737 %2 = bitcast i8* %1 to <3 x i16>* 738 %3 = load <3 x i16>* %2, align 2 739 ret <3 x i16> %3 740} 741define <2 x i16> @__rsAllocationVLoadXImpl_short2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 742 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 743 %2 = bitcast i8* %1 to <2 x i16>* 744 %3 = load <2 x i16>* %2, align 2 745 ret <2 x i16> %3 746} 747 748define <4 x i16> @__rsAllocationVLoadXImpl_ushort4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 749 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 750 %2 = bitcast i8* %1 to <4 x i16>* 751 %3 = load <4 x i16>* %2, align 2 752 ret <4 x i16> %3 753} 754define <3 x i16> @__rsAllocationVLoadXImpl_ushort3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 755 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 756 %2 = bitcast i8* %1 to <3 x i16>* 757 %3 = load <3 x i16>* %2, align 2 758 ret <3 x i16> %3 759} 760define <2 x i16> @__rsAllocationVLoadXImpl_ushort2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 761 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 762 %2 = bitcast i8* %1 to <2 x i16>* 763 %3 = load <2 x i16>* %2, align 2 764 ret <2 x i16> %3 765} 766 767define <4 x i8> @__rsAllocationVLoadXImpl_char4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 768 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 769 %2 = bitcast i8* %1 to <4 x i8>* 770 %3 = load <4 x i8>* %2, align 1 771 ret <4 x i8> %3 772} 773define <3 x i8> @__rsAllocationVLoadXImpl_char3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 774 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 775 %2 = bitcast i8* %1 to <3 x i8>* 776 %3 = load <3 x i8>* %2, align 1 777 ret <3 x i8> %3 778} 779define <2 x i8> @__rsAllocationVLoadXImpl_char2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 780 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 781 %2 = bitcast i8* %1 to <2 x i8>* 782 %3 = load <2 x i8>* %2, align 1 783 ret <2 x i8> %3 784} 785 786define <4 x i8> @__rsAllocationVLoadXImpl_uchar4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 787 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 788 %2 = bitcast i8* %1 to <4 x i8>* 789 %3 = load <4 x i8>* %2, align 1 790 ret <4 x i8> %3 791} 792define <3 x i8> @__rsAllocationVLoadXImpl_uchar3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 793 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 794 %2 = bitcast i8* %1 to <3 x i8>* 795 %3 = load <3 x i8>* %2, align 1 796 ret <3 x i8> %3 797} 798define <2 x i8> @__rsAllocationVLoadXImpl_uchar2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 799 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 800 %2 = bitcast i8* %1 to <2 x i8>* 801 %3 = load <2 x i8>* %2, align 1 802 ret <2 x i8> %3 803} 804 805define <4 x float> @__rsAllocationVLoadXImpl_float4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 806 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 807 %2 = bitcast i8* %1 to <4 x float>* 808 %3 = load <4 x float>* %2, align 4 809 ret <4 x float> %3 810} 811define <3 x float> @__rsAllocationVLoadXImpl_float3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 812 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 813 %2 = bitcast i8* %1 to <3 x float>* 814 %3 = load <3 x float>* %2, align 4 815 ret <3 x float> %3 816} 817define <2 x float> @__rsAllocationVLoadXImpl_float2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 818 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 819 %2 = bitcast i8* %1 to <2 x float>* 820 %3 = load <2 x float>* %2, align 4 821 ret <2 x float> %3 822} 823 824define <4 x double> @__rsAllocationVLoadXImpl_double4([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 825 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 826 %2 = bitcast i8* %1 to <4 x double>* 827 %3 = load <4 x double>* %2, align 8 828 ret <4 x double> %3 829} 830define <3 x double> @__rsAllocationVLoadXImpl_double3([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 831 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 832 %2 = bitcast i8* %1 to <3 x double>* 833 %3 = load <3 x double>* %2, align 8 834 ret <3 x double> %3 835} 836define <2 x double> @__rsAllocationVLoadXImpl_double2([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 837 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 838 %2 = bitcast i8* %1 to <2 x double>* 839 %3 = load <2 x double>* %2, align 8 840 ret <2 x double> %3 841} 842 843 844define void @__rsAllocationVStoreXImpl_long4([1 x i64] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 845 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 846 %2 = bitcast i8* %1 to <4 x i64>* 847 store <4 x i64> %val, <4 x i64>* %2, align 8 848 ret void 849} 850define void @__rsAllocationVStoreXImpl_long3([1 x i64] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 851 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 852 %2 = bitcast i8* %1 to <3 x i64>* 853 store <3 x i64> %val, <3 x i64>* %2, align 8 854 ret void 855} 856define void @__rsAllocationVStoreXImpl_long2([1 x i64] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 857 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 858 %2 = bitcast i8* %1 to <2 x i64>* 859 store <2 x i64> %val, <2 x i64>* %2, align 8 860 ret void 861} 862 863define void @__rsAllocationVStoreXImpl_ulong4([1 x i64] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 864 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 865 %2 = bitcast i8* %1 to <4 x i64>* 866 store <4 x i64> %val, <4 x i64>* %2, align 8 867 ret void 868} 869define void @__rsAllocationVStoreXImpl_ulong3([1 x i64] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 870 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 871 %2 = bitcast i8* %1 to <3 x i64>* 872 store <3 x i64> %val, <3 x i64>* %2, align 8 873 ret void 874} 875define void @__rsAllocationVStoreXImpl_ulong2([1 x i64] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #0 { 876 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 877 %2 = bitcast i8* %1 to <2 x i64>* 878 store <2 x i64> %val, <2 x i64>* %2, align 8 879 ret void 880} 881 882define void @__rsAllocationVStoreXImpl_int4([1 x i64] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 883 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 884 %2 = bitcast i8* %1 to <4 x i32>* 885 store <4 x i32> %val, <4 x i32>* %2, align 8 886 ret void 887} 888define void @__rsAllocationVStoreXImpl_int3([1 x i64] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 889 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 890 %2 = bitcast i8* %1 to <3 x i32>* 891 store <3 x i32> %val, <3 x i32>* %2, align 8 892 ret void 893} 894define void @__rsAllocationVStoreXImpl_int2([1 x i64] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 895 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 896 %2 = bitcast i8* %1 to <2 x i32>* 897 store <2 x i32> %val, <2 x i32>* %2, align 8 898 ret void 899} 900 901define void @__rsAllocationVStoreXImpl_uint4([1 x i64] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 902 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 903 %2 = bitcast i8* %1 to <4 x i32>* 904 store <4 x i32> %val, <4 x i32>* %2, align 8 905 ret void 906} 907define void @__rsAllocationVStoreXImpl_uint3([1 x i64] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 908 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 909 %2 = bitcast i8* %1 to <3 x i32>* 910 store <3 x i32> %val, <3 x i32>* %2, align 8 911 ret void 912} 913define void @__rsAllocationVStoreXImpl_uint2([1 x i64] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #0 { 914 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 915 %2 = bitcast i8* %1 to <2 x i32>* 916 store <2 x i32> %val, <2 x i32>* %2, align 8 917 ret void 918} 919 920define void @__rsAllocationVStoreXImpl_short4([1 x i64] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 921 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 922 %2 = bitcast i8* %1 to <4 x i16>* 923 store <4 x i16> %val, <4 x i16>* %2, align 8 924 ret void 925} 926define void @__rsAllocationVStoreXImpl_short3([1 x i64] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 927 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 928 %2 = bitcast i8* %1 to <3 x i16>* 929 store <3 x i16> %val, <3 x i16>* %2, align 8 930 ret void 931} 932define void @__rsAllocationVStoreXImpl_short2([1 x i64] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 933 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 934 %2 = bitcast i8* %1 to <2 x i16>* 935 store <2 x i16> %val, <2 x i16>* %2, align 8 936 ret void 937} 938 939define void @__rsAllocationVStoreXImpl_ushort4([1 x i64] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 940 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 941 %2 = bitcast i8* %1 to <4 x i16>* 942 store <4 x i16> %val, <4 x i16>* %2, align 8 943 ret void 944} 945define void @__rsAllocationVStoreXImpl_ushort3([1 x i64] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 946 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 947 %2 = bitcast i8* %1 to <3 x i16>* 948 store <3 x i16> %val, <3 x i16>* %2, align 8 949 ret void 950} 951define void @__rsAllocationVStoreXImpl_ushort2([1 x i64] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #0 { 952 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 953 %2 = bitcast i8* %1 to <2 x i16>* 954 store <2 x i16> %val, <2 x i16>* %2, align 8 955 ret void 956} 957 958define void @__rsAllocationVStoreXImpl_char4([1 x i64] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 959 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 960 %2 = bitcast i8* %1 to <4 x i8>* 961 store <4 x i8> %val, <4 x i8>* %2, align 8 962 ret void 963} 964define void @__rsAllocationVStoreXImpl_char3([1 x i64] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 965 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 966 %2 = bitcast i8* %1 to <3 x i8>* 967 store <3 x i8> %val, <3 x i8>* %2, align 8 968 ret void 969} 970define void @__rsAllocationVStoreXImpl_char2([1 x i64] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 971 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 972 %2 = bitcast i8* %1 to <2 x i8>* 973 store <2 x i8> %val, <2 x i8>* %2, align 8 974 ret void 975} 976 977define void @__rsAllocationVStoreXImpl_uchar4([1 x i64] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 978 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 979 %2 = bitcast i8* %1 to <4 x i8>* 980 store <4 x i8> %val, <4 x i8>* %2, align 8 981 ret void 982} 983define void @__rsAllocationVStoreXImpl_uchar3([1 x i64] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 984 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 985 %2 = bitcast i8* %1 to <3 x i8>* 986 store <3 x i8> %val, <3 x i8>* %2, align 8 987 ret void 988} 989define void @__rsAllocationVStoreXImpl_uchar2([1 x i64] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #0 { 990 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 991 %2 = bitcast i8* %1 to <2 x i8>* 992 store <2 x i8> %val, <2 x i8>* %2, align 8 993 ret void 994} 995 996define void @__rsAllocationVStoreXImpl_float4([1 x i64] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #0 { 997 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 998 %2 = bitcast i8* %1 to <4 x float>* 999 store <4 x float> %val, <4 x float>* %2, align 8 1000 ret void 1001} 1002define void @__rsAllocationVStoreXImpl_float3([1 x i64] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #0 { 1003 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 1004 %2 = bitcast i8* %1 to <3 x float>* 1005 store <3 x float> %val, <3 x float>* %2, align 8 1006 ret void 1007} 1008define void @__rsAllocationVStoreXImpl_float2([1 x i64] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #0 { 1009 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 1010 %2 = bitcast i8* %1 to <2 x float>* 1011 store <2 x float> %val, <2 x float>* %2, align 8 1012 ret void 1013} 1014 1015define void @__rsAllocationVStoreXImpl_double4([1 x i64] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #0 { 1016 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 1017 %2 = bitcast i8* %1 to <4 x double>* 1018 store <4 x double> %val, <4 x double>* %2, align 8 1019 ret void 1020} 1021define void @__rsAllocationVStoreXImpl_double3([1 x i64] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #0 { 1022 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 1023 %2 = bitcast i8* %1 to <3 x double>* 1024 store <3 x double> %val, <3 x double>* %2, align 8 1025 ret void 1026} 1027define void @__rsAllocationVStoreXImpl_double2([1 x i64] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #0 { 1028 %1 = tail call i8* @rsOffsetNs([1 x i64] %a.coerce, i32 %x, i32 %y, i32 %z) #10 1029 %2 = bitcast i8* %1 to <2 x double>* 1030 store <2 x double> %val, <2 x double>* %2, align 8 1031 ret void 1032} 1033 1034 1035attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1036attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1037attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1038attributes #3 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1039attributes #4 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1040attributes #5 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1041attributes #6 = { nounwind readnone } 1042attributes #7 = { nounwind } 1043attributes #8 = { alwaysinline nounwind readnone } 1044attributes #9 = { nounwind readonly } 1045attributes #10 = { nobuiltin } 1046attributes #11 = { nobuiltin nounwind } 1047attributes #12 = { nobuiltin nounwind readnone } 1048 1049