1e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/*
2e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * Author: Brendan Le Foll <brendan.le.foll@intel.com>
4e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * Copyright (c) 2014 Intel Corporation.
5e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang *
6e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * Permission is hereby granted, free of charge, to any person obtaining
7e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * a copy of this software and associated documentation files (the
8e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * "Software"), to deal in the Software without restriction, including
9e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * without limitation the rights to use, copy, modify, merge, publish,
10e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * distribute, sublicense, and/or sell copies of the Software, and to
11e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * permit persons to whom the Software is furnished to do so, subject to
12e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * the following conditions:
13e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang *
14e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * The above copyright notice and this permission notice shall be
15e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * included in all copies or substantial portions of the Software.
16e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang *
17e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
21e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
25e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
26e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#pragma once
27e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
28e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#include "common.h"
29e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#include "mraa.h"
30e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#include "mraa_adv_func.h"
316b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare#include "iio.h"
32e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
337d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban// Bionic does not implement pthread cancellation API
347d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban#ifndef __BIONIC__
357d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban#define HAVE_PTHREAD_CANCEL
367d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban#endif
377d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban
38e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang// general status failures for internal functions
39e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#define MRAA_PLATFORM_NO_INIT -3
40e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#define MRAA_IO_SETUP_FAILURE -2
41e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang#define MRAA_NO_SUCH_IO -1
42e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
43e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
44e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing a gpio pin.
45e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
46e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _gpio {
47e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
48e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int pin; /**< the pin number, as known to the os. */
49e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int phy_pin; /**< pin passed to clean init. -1 none and raw*/
50e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int value_fp; /**< the file pointer to the value of the gpio */
51e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    void (* isr)(void *); /**< the interupt service request */
52e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    void *isr_args; /**< args return when interupt service request triggered */
53e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    pthread_t thread_id; /**< the isr handler thread id */
54e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int isr_value_fp; /**< the isr file pointer on the value */
557d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban#ifndef HAVE_PTHREAD_CANCEL
567d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban    int isr_control_pipe[2]; /**< a pipe used to interrupt the isr from polling the value fd*/
577d3978fad94b70b4cb0dba9231b30870022f8563Mihai Serban#endif
58e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t isr_thread_terminating; /**< is the isr thread being terminated? */
59e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t owner; /**< If this context originally exported the pin */
60e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_result_t (*mmap_write) (mraa_gpio_context dev, int value);
61e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int (*mmap_read) (mraa_gpio_context dev);
62e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
63e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
64e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
65e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
66e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
67e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing a I2C bus
68e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
69e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _i2c {
70e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
71e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int busnum; /**< the bus number of the /dev/i2c-* device */
72e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int fh; /**< the file handle to the /dev/i2c-* device */
73e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int addr; /**< the address of the i2c slave */
74e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned long funcs; /**< /dev/i2c-* device capabilities as per https://www.kernel.org/doc/Documentation/i2c/functionality */
75e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    void *handle; /**< generic handle for non-standard drivers that don't use file descriptors  */
76e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
77e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
78e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
79e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
80e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
81e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing the SPI device
82e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
83e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _spi {
84e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
85e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int devfd;          /**< File descriptor to SPI Device */
86e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    uint32_t mode;      /**< Spi mode see spidev.h */
87e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int clock;          /**< clock to run transactions at */
88e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t lsb; /**< least significant bit mode */
89e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int bpw;   /**< Bits per word */
90e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
91e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
92e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
93e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
94e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
95e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing a PWM pin
96e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
97e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _pwm {
98e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
99e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int pin; /**< the pin number, as known to the os. */
100e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int chipid; /**< the chip id, which the pwm resides */
101e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int duty_fp; /**< File pointer to duty file */
102e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int period;  /**< Cache the period to speed up setting duty */
103e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t owner; /**< Owner of pwm context*/
104e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
105e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
106e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
107e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
108e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
109e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing a Analog Input Channel
110e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
111e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _aio {
112e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
113e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int channel; /**< the channel as on board and ADC module */
114e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int adc_in_fp; /**< File Pointer to raw sysfs */
115e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int value_bit; /**< 10 bits by default. Can be increased if board */
116e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
117e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
118e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
119e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
120e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
121e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A structure representing a UART device
122e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
123e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangstruct _uart {
124e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
125e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int index; /**< the uart index, as known to the os. */
126e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    const char* path; /**< the uart device path. */
127e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int fd; /**< file descriptor for device. */
128e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* advance_func; /**< override function table */
129e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
130e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang};
131e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
132e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
1336b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare * A structure representing an IIO device
1346b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare */
1356b1611a178516c059b80b1fecb9bbea070a00d0dBruce Bearestruct _iio {
1366b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int num; /**< IIO device number */
1376b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    char* name; /**< IIO device name */
1386b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int fp; /**< IIO device in /dev */
1396b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int fp_event;  /**<  event file descriptor for IIO device */
1406b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    void (* isr)(char* data); /**< the interupt service request */
1416b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    void *isr_args; /**< args return when interupt service request triggered */
1426b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    void (* isr_event)(struct iio_event_data* data, void* args); /**< the event interupt service request */
1436b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int chan_num;
1446b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    pthread_t thread_id; /**< the isr handler thread id */
1456b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    mraa_iio_channel* channels;
1466b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int event_num;
1476b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    mraa_iio_event* events;
1486b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    int datasize;
1496b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare};
1506b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare
1516b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare/**
152e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A bitfield representing the capabilities of a pin.
153e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
154e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
155e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
156e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t valid:1;     /**< Is the pin valid at all */
157e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t gpio:1;      /**< Is the pin gpio capable */
158e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t pwm:1;       /**< Is the pin pwm capable */
159e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t fast_gpio:1; /**< Is the pin fast gpio capable */
160e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t spi:1;       /**< Is the pin spi capable */
161e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t i2c:1;       /**< Is the pin i2c capable */
162e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t aio:1;       /**< Is the pin analog input capable */
163e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t uart:1;       /**< Is the pin uart capable */
164e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
165e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_pincapabilities_t;
166e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
167e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
168e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing a multiplexer and the required value
169e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
170e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
171e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
172e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int pin;   /**< Raw GPIO pin id */
173e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int value; /**< Raw GPIO value */
174e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
175e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_mux_t;
176e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
177e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
178e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t complex_pin:1;
179e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t output_en:1;
180e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t output_en_high:1;
181e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t pullup_en:1;
182e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t pullup_en_hiz:1;
183e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_pin_cap_complex_t;
184e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
185e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
186e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
187e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int pinmap; /**< sysfs pin */
188e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int parent_id; /** parent chip id */
189e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int mux_total; /** Numfer of muxes needed for operation of pin */
190e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_mux_t mux[6]; /** Array holding information about mux */
191e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int output_enable; /** Output Enable GPIO, for level shifting */
192e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int pullup_enable; /** Pull-Up enable GPIO, inputs */
193e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_cap_complex_t complex_cap;
194e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
195e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_pin_t;
196e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
197e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
198e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
199e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    char mem_dev[32]; /**< Memory device to use /dev/uio0 etc */
200e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int mem_sz; /** Size of memory to map */
201e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int bit_pos; /** Position of value bit */
202e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t gpio; /** GPio context containing none mmap info */
203e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
204e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_mmap_pin_t;
205e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
206e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
207e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing a physical Pin.
208e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
209e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
210e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
211e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    char name[MRAA_PIN_NAME_SIZE]; /**< Pin's real world name */
212e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pincapabilities_t capabilites; /**< Pin Capabiliites */
213e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t gpio; /**< GPIO structure */
214e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t pwm;  /**< PWM structure */
215e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t aio;  /**< Anaglog Pin */
216e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_mmap_pin_t mmap; /**< GPIO through memory */
217e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t i2c;  /**< i2c bus/pin */
218e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t spi;  /**< spi bus/pin */
219e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pin_t uart;  /**< uart module/pin */
220e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
221e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_pininfo_t;
222e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
223e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
224e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing the physical properties of a i2c bus.
225e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
226e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
227e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
228e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int bus_id; /**< ID as exposed in the system */
229e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int scl; /**< i2c SCL */
230e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int sda; /**< i2c SDA */
231e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    // mraa_drv_api_t drv_type; /**< Driver type */
232e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
233e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_i2c_bus_t;
234e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
235e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
236e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing the physical properties of a spi bus.
237e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
238e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
239e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
240e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int bus_id; /**< The Bus ID as exposed to the system. */
241e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int slave_s; /**< Slave select */
242e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_boolean_t three_wire; /**< Is the bus only a three wire system */
243e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int sclk; /**< Serial Clock */
244e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int mosi; /**< Master Out, Slave In. */
245e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int miso; /**< Master In, Slave Out. */
246e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int cs; /**< Chip Select, used when the board is a spi slave */
247e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
248e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_spi_bus_t;
249e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
250e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
251e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing a uart device.
252e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
253e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct {
254e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
255e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int index; /**< ID as exposed in the system */
256e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int rx; /**< uart rx */
257e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int tx; /**< uart tx */
258e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    const char* device_path; /**< To store "/dev/ttyS1" for example */
259e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
260e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_uart_dev_t;
261e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
262e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang/**
263e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang * A Structure representing a platform/board.
264e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang */
265e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
266e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhangtypedef struct _board_t {
267e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@{*/
268e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int phy_pin_count; /**< The Total IO pins on board */
269e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int gpio_count; /**< GPIO Count */
270e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int aio_count;  /**< Analog side Count */
271e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int i2c_bus_count; /**< Usable i2c Count */
272e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_i2c_bus_t  i2c_bus[12]; /**< Array of i2c */
273e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int def_i2c_bus; /**< Position in array of default i2c bus */
274e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int spi_bus_count; /**< Usable spi Count */
275e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_spi_bus_t spi_bus[12];       /**< Array of spi */
276e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int def_spi_bus; /**< Position in array of defult spi bus */
277e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int adc_raw; /**< ADC raw bit value */
278e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int adc_supported; /**< ADC supported bit value */
279e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int def_uart_dev; /**< Position in array of defult uart */
280e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    unsigned int uart_dev_count; /**< Usable spi Count */
281e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_uart_dev_t uart_dev[6]; /**< Array of UARTs */
2826b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    mraa_boolean_t no_bus_mux; /**< i2c/spi/adc/pwm/uart bus muxing setup not required */
283e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int pwm_default_period; /**< The default PWM period is US */
284e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int pwm_max_period; /**< Maximum period in us */
285e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    int pwm_min_period; /**< Minimum period in us */
286e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_platform_t platform_type; /**< Platform type */
287e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    const char* platform_name; /**< Platform Name pointer */
2886b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    const char* platform_version; /**< Platform versioning info */
289e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_pininfo_t* pins;     /**< Pointer to pin array */
290e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    mraa_adv_func_t* adv_func;    /**< Pointer to advanced function disptach table */
291e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    struct _board_t* sub_platform;     /**< Pointer to sub platform */
292e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang    /*@}*/
293e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang} mraa_board_t;
294e595125fe2f8ed6af763b9da7cfd817f576958dcJianxun Zhang
2956b1611a178516c059b80b1fecb9bbea070a00d0dBruce Bearetypedef struct {
2966b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    struct _iio* iio_devices; /**< Pointer to IIO devices */
2976b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare    uint8_t iio_device_count; /**< IIO device count */
2986b1611a178516c059b80b1fecb9bbea070a00d0dBruce Beare} mraa_iio_info_t;
299