msm_mdp.h revision 5d6a7fb6f1a9ff1d898b290fc7c0b2695cf22229
1#ifndef _MSM_MDP_H_ 2#define _MSM_MDP_H_ 3 4#include <linux/types.h> 5#include <linux/fb.h> 6 7#define MSMFB_IOCTL_MAGIC 'm' 8#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15/* new ioctls's for set/get ccs matrix */ 16#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71#define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74#define FB_TYPE_3D_PANEL 0x10101010 75#define MDP_IMGTYPE2_START 0x10000 76#define MSMFB_DRIVER_VERSION 0xF9E8D701 77 78/* HW Revisions for different MDSS targets */ 79#define MDSS_GET_MAJOR(rev) ((rev) >> 28) 80#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 81#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 82#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 83 84#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 85 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 86 87#define MDSS_MDP_REV(major, minor, step) \ 88 ((((major) & 0x000F) << 28) | \ 89 (((minor) & 0x0FFF) << 16) | \ 90 ((step) & 0xFFFF)) 91 92#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 93#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 94#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 95#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 96#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 97#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 98#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 99#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 100#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 101#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 102#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 103#define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 104#define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 105#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 106#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 107#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 108#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 109#define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 110#define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 111 112enum { 113 NOTIFY_UPDATE_INIT, 114 NOTIFY_UPDATE_DEINIT, 115 NOTIFY_UPDATE_START, 116 NOTIFY_UPDATE_STOP, 117 NOTIFY_UPDATE_POWER_OFF, 118}; 119 120enum { 121 NOTIFY_TYPE_NO_UPDATE, 122 NOTIFY_TYPE_SUSPEND, 123 NOTIFY_TYPE_UPDATE, 124 NOTIFY_TYPE_BL_UPDATE, 125 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 126}; 127 128enum { 129 MDP_RGB_565, /* RGB 565 planer */ 130 MDP_XRGB_8888, /* RGB 888 padded */ 131 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 132 MDP_Y_CBCR_H2V2_ADRENO, 133 MDP_ARGB_8888, /* ARGB 888 */ 134 MDP_RGB_888, /* RGB 888 planer */ 135 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 136 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 137 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 138 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 139 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 140 MDP_Y_CRCB_H1V2, 141 MDP_Y_CBCR_H1V2, 142 MDP_RGBA_8888, /* ARGB 888 */ 143 MDP_BGRA_8888, /* ABGR 888 */ 144 MDP_RGBX_8888, /* RGBX 888 */ 145 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 146 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 147 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 148 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 149 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 150 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 151 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 152 MDP_YCRCB_H1V1, /* YCrCb interleave */ 153 MDP_YCBCR_H1V1, /* YCbCr interleave */ 154 MDP_BGR_565, /* BGR 565 planer */ 155 MDP_BGR_888, /* BGR 888 */ 156 MDP_Y_CBCR_H2V2_VENUS, 157 MDP_BGRX_8888, /* BGRX 8888 */ 158 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 159 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 160 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 161 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 162 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 163 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 164 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 165 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 166 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 167 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 168 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 169 MDP_ARGB_1555, /*ARGB 1555*/ 170 MDP_RGBA_5551, /*RGBA 5551*/ 171 MDP_ARGB_4444, /*ARGB 4444*/ 172 MDP_RGBA_4444, /*RGBA 4444*/ 173 MDP_RGB_565_UBWC, 174 MDP_RGBA_8888_UBWC, 175 MDP_Y_CBCR_H2V2_UBWC, 176 MDP_RGBX_8888_UBWC, 177 MDP_Y_CRCB_H2V2_VENUS, 178 MDP_IMGTYPE_LIMIT, 179 MDP_RGB_BORDERFILL, /* border fill pipe */ 180 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 181 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 182}; 183 184enum { 185 PMEM_IMG, 186 FB_IMG, 187}; 188 189enum { 190 HSIC_HUE = 0, 191 HSIC_SAT, 192 HSIC_INT, 193 HSIC_CON, 194 NUM_HSIC_PARAM, 195}; 196 197enum mdss_mdp_max_bw_mode { 198 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 199 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 200 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 201 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 202}; 203 204#define MDSS_MDP_ROT_ONLY 0x80 205#define MDSS_MDP_RIGHT_MIXER 0x100 206#define MDSS_MDP_DUAL_PIPE 0x200 207 208/* mdp_blit_req flag values */ 209#define MDP_ROT_NOP 0 210#define MDP_FLIP_LR 0x1 211#define MDP_FLIP_UD 0x2 212#define MDP_ROT_90 0x4 213#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 214#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 215#define MDP_DITHER 0x8 216#define MDP_BLUR 0x10 217#define MDP_BLEND_FG_PREMULT 0x20000 218#define MDP_IS_FG 0x40000 219#define MDP_SOLID_FILL 0x00000020 220#define MDP_VPU_PIPE 0x00000040 221#define MDP_DEINTERLACE 0x80000000 222#define MDP_SHARPENING 0x40000000 223#define MDP_NO_DMA_BARRIER_START 0x20000000 224#define MDP_NO_DMA_BARRIER_END 0x10000000 225#define MDP_NO_BLIT 0x08000000 226#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 227#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 228 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 229#define MDP_BLIT_SRC_GEM 0x04000000 230#define MDP_BLIT_DST_GEM 0x02000000 231#define MDP_BLIT_NON_CACHED 0x01000000 232#define MDP_OV_PIPE_SHARE 0x00800000 233#define MDP_DEINTERLACE_ODD 0x00400000 234#define MDP_OV_PLAY_NOWAIT 0x00200000 235#define MDP_SOURCE_ROTATED_90 0x00100000 236#define MDP_OVERLAY_PP_CFG_EN 0x00080000 237#define MDP_BACKEND_COMPOSITION 0x00040000 238#define MDP_BORDERFILL_SUPPORTED 0x00010000 239#define MDP_SECURE_OVERLAY_SESSION 0x00008000 240#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 241#define MDP_OV_PIPE_FORCE_DMA 0x00004000 242#define MDP_MEMORY_ID_TYPE_FB 0x00001000 243#define MDP_BWC_EN 0x00000400 244#define MDP_DECIMATION_EN 0x00000800 245#define MDP_SMP_FORCE_ALLOC 0x00200000 246#define MDP_TRANSP_NOP 0xffffffff 247#define MDP_ALPHA_NOP 0xff 248 249#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 250#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 251#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 252#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 253#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 254/* Sentinel: Don't use! */ 255#define MDP_FB_PAGE_PROTECTION_INVALID (5) 256/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 257#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 258 259struct mdp_rect { 260 uint32_t x; 261 uint32_t y; 262 uint32_t w; 263 uint32_t h; 264}; 265 266struct mdp_img { 267 uint32_t width; 268 uint32_t height; 269 uint32_t format; 270 uint32_t offset; 271 int memory_id; /* the file descriptor */ 272 uint32_t priv; 273}; 274 275struct mult_factor { 276 uint32_t numer; 277 uint32_t denom; 278}; 279 280/* 281 * {3x3} + {3} ccs matrix 282 */ 283 284#define MDP_CCS_RGB2YUV 0 285#define MDP_CCS_YUV2RGB 1 286 287#define MDP_CCS_SIZE 9 288#define MDP_BV_SIZE 3 289 290struct mdp_ccs { 291 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 292 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 293 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 294}; 295 296struct mdp_csc { 297 int id; 298 uint32_t csc_mv[9]; 299 uint32_t csc_pre_bv[3]; 300 uint32_t csc_post_bv[3]; 301 uint32_t csc_pre_lv[6]; 302 uint32_t csc_post_lv[6]; 303}; 304 305/* The version of the mdp_blit_req structure so that 306 * user applications can selectively decide which functionality 307 * to include 308 */ 309 310#define MDP_BLIT_REQ_VERSION 2 311 312struct color { 313 uint32_t r; 314 uint32_t g; 315 uint32_t b; 316 uint32_t alpha; 317}; 318 319struct mdp_blit_req { 320 struct mdp_img src; 321 struct mdp_img dst; 322 struct mdp_rect src_rect; 323 struct mdp_rect dst_rect; 324 struct color const_color; 325 uint32_t alpha; 326 uint32_t transp_mask; 327 uint32_t flags; 328 int sharpening_strength; /* -127 <--> 127, default 64 */ 329 uint8_t color_space; 330}; 331 332struct mdp_blit_req_list { 333 uint32_t count; 334 struct mdp_blit_req req[]; 335}; 336 337#define MSMFB_DATA_VERSION 2 338 339struct msmfb_data { 340 uint32_t offset; 341 int memory_id; 342 int id; 343 uint32_t flags; 344 uint32_t priv; 345 uint32_t iova; 346}; 347 348#define MSMFB_NEW_REQUEST -1 349 350struct msmfb_overlay_data { 351 uint32_t id; 352 struct msmfb_data data; 353 uint32_t version_key; 354 struct msmfb_data plane1_data; 355 struct msmfb_data plane2_data; 356 struct msmfb_data dst_data; 357}; 358 359struct msmfb_img { 360 uint32_t width; 361 uint32_t height; 362 uint32_t format; 363}; 364 365#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 366struct msmfb_writeback_data { 367 struct msmfb_data buf_info; 368 struct msmfb_img img; 369}; 370 371#define MDP_PP_OPS_ENABLE 0x1 372#define MDP_PP_OPS_READ 0x2 373#define MDP_PP_OPS_WRITE 0x4 374#define MDP_PP_OPS_DISABLE 0x8 375#define MDP_PP_IGC_FLAG_ROM0 0x10 376#define MDP_PP_IGC_FLAG_ROM1 0x20 377 378 379#define MDSS_PP_DSPP_CFG 0x000 380#define MDSS_PP_SSPP_CFG 0x100 381#define MDSS_PP_LM_CFG 0x200 382#define MDSS_PP_WB_CFG 0x300 383 384#define MDSS_PP_ARG_MASK 0x3C00 385#define MDSS_PP_ARG_NUM 4 386#define MDSS_PP_ARG_SHIFT 10 387#define MDSS_PP_LOCATION_MASK 0x0300 388#define MDSS_PP_LOGICAL_MASK 0x00FF 389 390#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 391#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 392#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 393#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 394 395 396struct mdp_qseed_cfg { 397 uint32_t table_num; 398 uint32_t ops; 399 uint32_t len; 400 uint32_t *data; 401}; 402 403struct mdp_sharp_cfg { 404 uint32_t flags; 405 uint32_t strength; 406 uint32_t edge_thr; 407 uint32_t smooth_thr; 408 uint32_t noise_thr; 409}; 410 411struct mdp_qseed_cfg_data { 412 uint32_t block; 413 struct mdp_qseed_cfg qseed_data; 414}; 415 416#define MDP_OVERLAY_PP_CSC_CFG 0x1 417#define MDP_OVERLAY_PP_QSEED_CFG 0x2 418#define MDP_OVERLAY_PP_PA_CFG 0x4 419#define MDP_OVERLAY_PP_IGC_CFG 0x8 420#define MDP_OVERLAY_PP_SHARP_CFG 0x10 421#define MDP_OVERLAY_PP_HIST_CFG 0x20 422#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 423#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 424#define MDP_OVERLAY_PP_PCC_CFG 0x100 425 426#define MDP_CSC_FLAG_ENABLE 0x1 427#define MDP_CSC_FLAG_YUV_IN 0x2 428#define MDP_CSC_FLAG_YUV_OUT 0x4 429 430#define MDP_CSC_MATRIX_COEFF_SIZE 9 431#define MDP_CSC_CLAMP_SIZE 6 432#define MDP_CSC_BIAS_SIZE 3 433 434struct mdp_csc_cfg { 435 /* flags for enable CSC, toggling RGB,YUV input/output */ 436 uint32_t flags; 437 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 438 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 439 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 440 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 441 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 442}; 443 444struct mdp_csc_cfg_data { 445 uint32_t block; 446 struct mdp_csc_cfg csc_data; 447}; 448 449struct mdp_pa_cfg { 450 uint32_t flags; 451 uint32_t hue_adj; 452 uint32_t sat_adj; 453 uint32_t val_adj; 454 uint32_t cont_adj; 455}; 456 457struct mdp_pa_mem_col_cfg { 458 uint32_t color_adjust_p0; 459 uint32_t color_adjust_p1; 460 uint32_t hue_region; 461 uint32_t sat_region; 462 uint32_t val_region; 463}; 464 465#define MDP_SIX_ZONE_LUT_SIZE 384 466 467/* PA Write/Read extension flags */ 468#define MDP_PP_PA_HUE_ENABLE 0x10 469#define MDP_PP_PA_SAT_ENABLE 0x20 470#define MDP_PP_PA_VAL_ENABLE 0x40 471#define MDP_PP_PA_CONT_ENABLE 0x80 472#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 473#define MDP_PP_PA_SKIN_ENABLE 0x200 474#define MDP_PP_PA_SKY_ENABLE 0x400 475#define MDP_PP_PA_FOL_ENABLE 0x800 476 477/* PA masks */ 478/* Masks used in PA v1_7 only */ 479#define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 480#define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 481#define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 482#define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 483#define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 484#define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 485/* Masks used in all PAv2 versions */ 486#define MDP_PP_PA_HUE_MASK 0x1000 487#define MDP_PP_PA_SAT_MASK 0x2000 488#define MDP_PP_PA_VAL_MASK 0x4000 489#define MDP_PP_PA_CONT_MASK 0x8000 490#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 491#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 492#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 493#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 494#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 495#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 496#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 497#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 498 499/* Flags for setting PA saturation and value hold */ 500#define MDP_PP_PA_LEFT_HOLD 0x1 501#define MDP_PP_PA_RIGHT_HOLD 0x2 502 503struct mdp_pa_v2_data { 504 /* Mask bits for PA features */ 505 uint32_t flags; 506 uint32_t global_hue_adj; 507 uint32_t global_sat_adj; 508 uint32_t global_val_adj; 509 uint32_t global_cont_adj; 510 struct mdp_pa_mem_col_cfg skin_cfg; 511 struct mdp_pa_mem_col_cfg sky_cfg; 512 struct mdp_pa_mem_col_cfg fol_cfg; 513 uint32_t six_zone_len; 514 uint32_t six_zone_thresh; 515 uint32_t *six_zone_curve_p0; 516 uint32_t *six_zone_curve_p1; 517}; 518 519struct mdp_pa_mem_col_data_v1_7 { 520 uint32_t color_adjust_p0; 521 uint32_t color_adjust_p1; 522 uint32_t color_adjust_p2; 523 uint32_t blend_gain; 524 uint8_t sat_hold; 525 uint8_t val_hold; 526 uint32_t hue_region; 527 uint32_t sat_region; 528 uint32_t val_region; 529}; 530 531struct mdp_pa_data_v1_7 { 532 uint32_t mode; 533 uint32_t global_hue_adj; 534 uint32_t global_sat_adj; 535 uint32_t global_val_adj; 536 uint32_t global_cont_adj; 537 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 538 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 539 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 540 uint32_t six_zone_thresh; 541 uint32_t six_zone_adj_p0; 542 uint32_t six_zone_adj_p1; 543 uint8_t six_zone_sat_hold; 544 uint8_t six_zone_val_hold; 545 uint32_t six_zone_len; 546 uint32_t *six_zone_curve_p0; 547 uint32_t *six_zone_curve_p1; 548}; 549 550 551struct mdp_pa_v2_cfg_data { 552 uint32_t version; 553 uint32_t block; 554 uint32_t flags; 555 struct mdp_pa_v2_data pa_v2_data; 556 void *cfg_payload; 557}; 558 559 560enum { 561 mdp_igc_rec601 = 1, 562 mdp_igc_rec709, 563 mdp_igc_srgb, 564 mdp_igc_custom, 565 mdp_igc_rec_max, 566}; 567 568struct mdp_igc_lut_data { 569 uint32_t block; 570 uint32_t version; 571 uint32_t len, ops; 572 uint32_t *c0_c1_data; 573 uint32_t *c2_data; 574 void *cfg_payload; 575}; 576 577struct mdp_igc_lut_data_v1_7 { 578 uint32_t table_fmt; 579 uint32_t len; 580 uint32_t *c0_c1_data; 581 uint32_t *c2_data; 582}; 583 584struct mdp_histogram_cfg { 585 uint32_t ops; 586 uint32_t block; 587 uint8_t frame_cnt; 588 uint8_t bit_mask; 589 uint16_t num_bins; 590}; 591 592struct mdp_hist_lut_data_v1_7 { 593 uint32_t len; 594 uint32_t *data; 595}; 596 597struct mdp_hist_lut_data { 598 uint32_t block; 599 uint32_t version; 600 uint32_t hist_lut_first; 601 uint32_t ops; 602 uint32_t len; 603 uint32_t *data; 604 void *cfg_payload; 605}; 606 607struct mdp_pcc_coeff { 608 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 609}; 610 611struct mdp_pcc_coeff_v1_7 { 612 uint32_t c, r, g, b, rg, gb, rb, rgb; 613}; 614 615struct mdp_pcc_data_v1_7 { 616 struct mdp_pcc_coeff_v1_7 r, g, b; 617}; 618 619struct mdp_pcc_cfg_data { 620 uint32_t version; 621 uint32_t block; 622 uint32_t ops; 623 struct mdp_pcc_coeff r, g, b; 624 void *cfg_payload; 625}; 626 627enum { 628 mdp_lut_igc, 629 mdp_lut_pgc, 630 mdp_lut_hist, 631 mdp_lut_rgb, 632 mdp_lut_max, 633}; 634struct mdp_overlay_pp_params { 635 uint32_t config_ops; 636 struct mdp_csc_cfg csc_cfg; 637 struct mdp_qseed_cfg qseed_cfg[2]; 638 struct mdp_pa_cfg pa_cfg; 639 struct mdp_pa_v2_data pa_v2_cfg; 640 struct mdp_igc_lut_data igc_cfg; 641 struct mdp_sharp_cfg sharp_cfg; 642 struct mdp_histogram_cfg hist_cfg; 643 struct mdp_hist_lut_data hist_lut_cfg; 644 /* PAv2 cfg data for PA 2.x versions */ 645 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 646 struct mdp_pcc_cfg_data pcc_cfg_data; 647}; 648 649/** 650 * enum mdss_mdp_blend_op - Different blend operations set by userspace 651 * 652 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 653 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 654 * would appear opaque in case fg plane alpha is 655 * 0xff. 656 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 657 * alpha pre-multiplication done. If fg plane alpha 658 * is less than 0xff, apply modulation as well. This 659 * operation is intended on layers having alpha 660 * channel. 661 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 662 * pre-multiplied. Apply pre-multiplication. If fg 663 * plane alpha is less than 0xff, apply modulation as 664 * well. 665 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 666 * mdp. 667 */ 668enum mdss_mdp_blend_op { 669 BLEND_OP_NOT_DEFINED = 0, 670 BLEND_OP_OPAQUE, 671 BLEND_OP_PREMULTIPLIED, 672 BLEND_OP_COVERAGE, 673 BLEND_OP_MAX, 674}; 675 676#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 677#define MAX_PLANES 4 678struct mdp_scale_data { 679 uint8_t enable_pxl_ext; 680 681 int init_phase_x[MAX_PLANES]; 682 int phase_step_x[MAX_PLANES]; 683 int init_phase_y[MAX_PLANES]; 684 int phase_step_y[MAX_PLANES]; 685 686 int num_ext_pxls_left[MAX_PLANES]; 687 int num_ext_pxls_right[MAX_PLANES]; 688 int num_ext_pxls_top[MAX_PLANES]; 689 int num_ext_pxls_btm[MAX_PLANES]; 690 691 int left_ftch[MAX_PLANES]; 692 int left_rpt[MAX_PLANES]; 693 int right_ftch[MAX_PLANES]; 694 int right_rpt[MAX_PLANES]; 695 696 int top_rpt[MAX_PLANES]; 697 int btm_rpt[MAX_PLANES]; 698 int top_ftch[MAX_PLANES]; 699 int btm_ftch[MAX_PLANES]; 700 701 uint32_t roi_w[MAX_PLANES]; 702}; 703 704/** 705 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 706 * 707 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 708 * @PIPE_TYPE_VIG: VIG pipe. 709 * @PIPE_TYPE_RGB: RGB pipe. 710 * @PIPE_TYPE_DMA: DMA pipe. 711 * @PIPE_TYPE_CURSOR: CURSOR pipe. 712 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 713 */ 714enum mdp_overlay_pipe_type { 715 PIPE_TYPE_AUTO = 0, 716 PIPE_TYPE_VIG, 717 PIPE_TYPE_RGB, 718 PIPE_TYPE_DMA, 719 PIPE_TYPE_CURSOR, 720 PIPE_TYPE_MAX, 721}; 722 723/** 724 * struct mdp_overlay - overlay surface structure 725 * @src: Source image information (width, height, format). 726 * @src_rect: Source crop rectangle, portion of image that will be fetched. 727 * This should always be within boundaries of source image. 728 * @dst_rect: Destination rectangle, the position and size of image on screen. 729 * This should always be within panel boundaries. 730 * @z_order: Blending stage to occupy in display, if multiple layers are 731 * present, highest z_order usually means the top most visible 732 * layer. The range acceptable is from 0-3 to support blending 733 * up to 4 layers. 734 * @is_fg: This flag is used to disable blending of any layers with z_order 735 * less than this overlay. It means that any layers with z_order 736 * less than this layer will not be blended and will be replaced 737 * by the background border color. 738 * @alpha: Used to set plane opacity. The range can be from 0-255, where 739 * 0 means completely transparent and 255 means fully opaque. 740 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 741 * image matching this color will be transparent when blending. 742 * The color should be in same format as the source image format. 743 * @flags: This is used to customize operation of overlay. See MDP flags 744 * for more information. 745 * @pipe_type: Used to specify the type of overlay pipe. 746 * @user_data: DEPRECATED* Used to store user application specific information. 747 * @bg_color: Solid color used to fill the overlay surface when no source 748 * buffer is provided. 749 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 750 * dropped for each pixel that is fetched from a line. The value 751 * given should be power of two of decimation amount. 752 * 0: no decimation 753 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 754 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 755 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 756 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 757 * @vert_deci: Vertical decimation value, this indicates the amount of lines 758 * dropped for each line that is fetched from overlay. The value 759 * given should be power of two of decimation amount. 760 * 0: no decimation 761 * 1: decimation by 2 (drop 1 line for each line fetched) 762 * 2: decimation by 4 (drop 3 lines for each line fetched) 763 * 3: decimation by 8 (drop 7 lines for each line fetched) 764 * 4: decimation by 16 (drop 15 lines for each line fetched) 765 * @overlay_pp_cfg: Overlay post processing configuration, for more information 766 * see struct mdp_overlay_pp_params. 767 * @priority: Priority is returned by the driver when overlay is set for the 768 * first time. It indicates the priority of the underlying pipe 769 * serving the overlay. This priority can be used by user-space 770 * in source split when pipes are re-used and shuffled around to 771 * reduce fallbacks. 772 */ 773struct mdp_overlay { 774 struct msmfb_img src; 775 struct mdp_rect src_rect; 776 struct mdp_rect dst_rect; 777 uint32_t z_order; /* stage number */ 778 uint32_t is_fg; /* control alpha & transp */ 779 uint32_t alpha; 780 uint32_t blend_op; 781 uint32_t transp_mask; 782 uint32_t flags; 783 uint32_t pipe_type; 784 uint32_t id; 785 uint8_t priority; 786 uint32_t user_data[6]; 787 uint32_t bg_color; 788 uint8_t horz_deci; 789 uint8_t vert_deci; 790 struct mdp_overlay_pp_params overlay_pp_cfg; 791 struct mdp_scale_data scale; 792 uint8_t color_space; 793 uint32_t frame_rate; 794}; 795 796struct msmfb_overlay_3d { 797 uint32_t is_3d; 798 uint32_t width; 799 uint32_t height; 800}; 801 802 803struct msmfb_overlay_blt { 804 uint32_t enable; 805 uint32_t offset; 806 uint32_t width; 807 uint32_t height; 808 uint32_t bpp; 809}; 810 811struct mdp_histogram { 812 uint32_t frame_cnt; 813 uint32_t bin_cnt; 814 uint32_t *r; 815 uint32_t *g; 816 uint32_t *b; 817}; 818 819#define MISR_CRC_BATCH_SIZE 32 820enum { 821 DISPLAY_MISR_EDP, 822 DISPLAY_MISR_DSI0, 823 DISPLAY_MISR_DSI1, 824 DISPLAY_MISR_HDMI, 825 DISPLAY_MISR_LCDC, 826 DISPLAY_MISR_MDP, 827 DISPLAY_MISR_ATV, 828 DISPLAY_MISR_DSI_CMD, 829 DISPLAY_MISR_MAX 830}; 831 832enum { 833 MISR_OP_NONE, 834 MISR_OP_SFM, 835 MISR_OP_MFM, 836 MISR_OP_BM, 837 MISR_OP_MAX 838}; 839 840struct mdp_misr { 841 uint32_t block_id; 842 uint32_t frame_count; 843 uint32_t crc_op_mode; 844 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 845}; 846 847/* 848 849 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 850 851 MDP_BLOCK_RESERVED is provided for backward compatibility and is 852 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 853 instead. 854 855 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 856 same for others. 857 858*/ 859 860enum { 861 MDP_BLOCK_RESERVED = 0, 862 MDP_BLOCK_OVERLAY_0, 863 MDP_BLOCK_OVERLAY_1, 864 MDP_BLOCK_VG_1, 865 MDP_BLOCK_VG_2, 866 MDP_BLOCK_RGB_1, 867 MDP_BLOCK_RGB_2, 868 MDP_BLOCK_DMA_P, 869 MDP_BLOCK_DMA_S, 870 MDP_BLOCK_DMA_E, 871 MDP_BLOCK_OVERLAY_2, 872 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 873 MDP_LOGICAL_BLOCK_DISP_1, 874 MDP_LOGICAL_BLOCK_DISP_2, 875 MDP_BLOCK_MAX, 876}; 877 878/* 879 * mdp_histogram_start_req is used to provide the parameters for 880 * histogram start request 881 */ 882 883struct mdp_histogram_start_req { 884 uint32_t block; 885 uint8_t frame_cnt; 886 uint8_t bit_mask; 887 uint16_t num_bins; 888}; 889 890/* 891 * mdp_histogram_data is used to return the histogram data, once 892 * the histogram is done/stopped/cance 893 */ 894 895struct mdp_histogram_data { 896 uint32_t block; 897 uint32_t bin_cnt; 898 uint32_t *c0; 899 uint32_t *c1; 900 uint32_t *c2; 901 uint32_t *extra_info; 902}; 903 904 905#define GC_LUT_ENTRIES_V1_7 512 906 907struct mdp_ar_gc_lut_data { 908 uint32_t x_start; 909 uint32_t slope; 910 uint32_t offset; 911}; 912 913struct mdp_pgc_lut_data { 914 uint32_t version; 915 uint32_t block; 916 uint32_t flags; 917 uint8_t num_r_stages; 918 uint8_t num_g_stages; 919 uint8_t num_b_stages; 920 struct mdp_ar_gc_lut_data *r_data; 921 struct mdp_ar_gc_lut_data *g_data; 922 struct mdp_ar_gc_lut_data *b_data; 923 void *cfg_payload; 924}; 925 926#define PGC_LUT_ENTRIES 1024 927struct mdp_pgc_lut_data_v1_7 { 928 uint32_t len; 929 uint32_t *c0_data; 930 uint32_t *c1_data; 931 uint32_t *c2_data; 932}; 933 934/* 935 * mdp_rgb_lut_data is used to provide parameters for configuring the 936 * generic RGB lut in case of gamma correction or other LUT updation usecases 937 */ 938struct mdp_rgb_lut_data { 939 uint32_t flags; 940 uint32_t lut_type; 941 struct fb_cmap cmap; 942}; 943 944enum { 945 mdp_rgb_lut_gc, 946 mdp_rgb_lut_hist, 947}; 948 949struct mdp_lut_cfg_data { 950 uint32_t lut_type; 951 union { 952 struct mdp_igc_lut_data igc_lut_data; 953 struct mdp_pgc_lut_data pgc_lut_data; 954 struct mdp_hist_lut_data hist_lut_data; 955 struct mdp_rgb_lut_data rgb_lut_data; 956 } data; 957}; 958 959struct mdp_bl_scale_data { 960 uint32_t min_lvl; 961 uint32_t scale; 962}; 963 964struct mdp_pa_cfg_data { 965 uint32_t block; 966 struct mdp_pa_cfg pa_data; 967}; 968 969struct mdp_dither_data_v1_7 { 970 uint32_t g_y_depth; 971 uint32_t r_cr_depth; 972 uint32_t b_cb_depth; 973}; 974 975struct mdp_dither_cfg_data { 976 uint32_t version; 977 uint32_t block; 978 uint32_t flags; 979 uint32_t mode; 980 uint32_t g_y_depth; 981 uint32_t r_cr_depth; 982 uint32_t b_cb_depth; 983 void *cfg_payload; 984}; 985 986#define MDP_GAMUT_TABLE_NUM 8 987#define MDP_GAMUT_TABLE_NUM_V1_7 4 988#define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 989#define MDP_GAMUT_TABLE_V1_7_SZ 1229 990#define MDP_GAMUT_SCALE_OFF_SZ 16 991#define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 992 993struct mdp_gamut_cfg_data { 994 uint32_t block; 995 uint32_t flags; 996 uint32_t version; 997 /* v1 version specific params */ 998 uint32_t gamut_first; 999 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1000 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1001 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1002 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1003 /* params for newer versions of gamut */ 1004 void *cfg_payload; 1005}; 1006 1007enum { 1008 mdp_gamut_fine_mode = 0x1, 1009 mdp_gamut_coarse_mode, 1010}; 1011 1012struct mdp_gamut_data_v1_7 { 1013 uint32_t mode; 1014 uint32_t map_en; 1015 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1016 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1017 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1018 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1019 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1020}; 1021 1022struct mdp_calib_config_data { 1023 uint32_t ops; 1024 uint32_t addr; 1025 uint32_t data; 1026}; 1027 1028struct mdp_calib_config_buffer { 1029 uint32_t ops; 1030 uint32_t size; 1031 uint32_t *buffer; 1032}; 1033 1034struct mdp_calib_dcm_state { 1035 uint32_t ops; 1036 uint32_t dcm_state; 1037}; 1038 1039enum { 1040 DCM_UNINIT, 1041 DCM_UNBLANK, 1042 DCM_ENTER, 1043 DCM_EXIT, 1044 DCM_BLANK, 1045 DTM_ENTER, 1046 DTM_EXIT, 1047}; 1048 1049#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1050#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1051#define MDSS_PP_SPLIT_MASK 0x30000000 1052 1053#define MDSS_MAX_BL_BRIGHTNESS 255 1054#define AD_BL_LIN_LEN 256 1055#define AD_BL_ATT_LUT_LEN 33 1056 1057#define MDSS_AD_MODE_AUTO_BL 0x0 1058#define MDSS_AD_MODE_AUTO_STR 0x1 1059#define MDSS_AD_MODE_TARG_STR 0x3 1060#define MDSS_AD_MODE_MAN_STR 0x7 1061#define MDSS_AD_MODE_CALIB 0xF 1062 1063#define MDP_PP_AD_INIT 0x10 1064#define MDP_PP_AD_CFG 0x20 1065 1066struct mdss_ad_init { 1067 uint32_t asym_lut[33]; 1068 uint32_t color_corr_lut[33]; 1069 uint8_t i_control[2]; 1070 uint16_t black_lvl; 1071 uint16_t white_lvl; 1072 uint8_t var; 1073 uint8_t limit_ampl; 1074 uint8_t i_dither; 1075 uint8_t slope_max; 1076 uint8_t slope_min; 1077 uint8_t dither_ctl; 1078 uint8_t format; 1079 uint8_t auto_size; 1080 uint16_t frame_w; 1081 uint16_t frame_h; 1082 uint8_t logo_v; 1083 uint8_t logo_h; 1084 uint32_t alpha; 1085 uint32_t alpha_base; 1086 uint32_t al_thresh; 1087 uint32_t bl_lin_len; 1088 uint32_t bl_att_len; 1089 uint32_t *bl_lin; 1090 uint32_t *bl_lin_inv; 1091 uint32_t *bl_att_lut; 1092}; 1093 1094#define MDSS_AD_BL_CTRL_MODE_EN 1 1095#define MDSS_AD_BL_CTRL_MODE_DIS 0 1096struct mdss_ad_cfg { 1097 uint32_t mode; 1098 uint32_t al_calib_lut[33]; 1099 uint16_t backlight_min; 1100 uint16_t backlight_max; 1101 uint16_t backlight_scale; 1102 uint16_t amb_light_min; 1103 uint16_t filter[2]; 1104 uint16_t calib[4]; 1105 uint8_t strength_limit; 1106 uint8_t t_filter_recursion; 1107 uint16_t stab_itr; 1108 uint32_t bl_ctrl_mode; 1109}; 1110 1111/* ops uses standard MDP_PP_* flags */ 1112struct mdss_ad_init_cfg { 1113 uint32_t ops; 1114 union { 1115 struct mdss_ad_init init; 1116 struct mdss_ad_cfg cfg; 1117 } params; 1118}; 1119 1120/* mode uses MDSS_AD_MODE_* flags */ 1121struct mdss_ad_input { 1122 uint32_t mode; 1123 union { 1124 uint32_t amb_light; 1125 uint32_t strength; 1126 uint32_t calib_bl; 1127 } in; 1128 uint32_t output; 1129}; 1130 1131#define MDSS_CALIB_MODE_BL 0x1 1132struct mdss_calib_cfg { 1133 uint32_t ops; 1134 uint32_t calib_mask; 1135}; 1136 1137enum { 1138 mdp_op_pcc_cfg, 1139 mdp_op_csc_cfg, 1140 mdp_op_lut_cfg, 1141 mdp_op_qseed_cfg, 1142 mdp_bl_scale_cfg, 1143 mdp_op_pa_cfg, 1144 mdp_op_pa_v2_cfg, 1145 mdp_op_dither_cfg, 1146 mdp_op_gamut_cfg, 1147 mdp_op_calib_cfg, 1148 mdp_op_ad_cfg, 1149 mdp_op_ad_input, 1150 mdp_op_calib_mode, 1151 mdp_op_calib_buffer, 1152 mdp_op_calib_dcm_state, 1153 mdp_op_max, 1154}; 1155 1156enum { 1157 WB_FORMAT_NV12, 1158 WB_FORMAT_RGB_565, 1159 WB_FORMAT_RGB_888, 1160 WB_FORMAT_xRGB_8888, 1161 WB_FORMAT_ARGB_8888, 1162 WB_FORMAT_BGRA_8888, 1163 WB_FORMAT_BGRX_8888, 1164 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1165}; 1166 1167struct msmfb_mdp_pp { 1168 uint32_t op; 1169 union { 1170 struct mdp_pcc_cfg_data pcc_cfg_data; 1171 struct mdp_csc_cfg_data csc_cfg_data; 1172 struct mdp_lut_cfg_data lut_cfg_data; 1173 struct mdp_qseed_cfg_data qseed_cfg_data; 1174 struct mdp_bl_scale_data bl_scale_data; 1175 struct mdp_pa_cfg_data pa_cfg_data; 1176 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1177 struct mdp_dither_cfg_data dither_cfg_data; 1178 struct mdp_gamut_cfg_data gamut_cfg_data; 1179 struct mdp_calib_config_data calib_cfg; 1180 struct mdss_ad_init_cfg ad_init_cfg; 1181 struct mdss_calib_cfg mdss_calib_cfg; 1182 struct mdss_ad_input ad_input; 1183 struct mdp_calib_config_buffer calib_buffer; 1184 struct mdp_calib_dcm_state calib_dcm; 1185 } data; 1186}; 1187 1188#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1189enum { 1190 metadata_op_none, 1191 metadata_op_base_blend, 1192 metadata_op_frame_rate, 1193 metadata_op_vic, 1194 metadata_op_wb_format, 1195 metadata_op_wb_secure, 1196 metadata_op_get_caps, 1197 metadata_op_crc, 1198 metadata_op_get_ion_fd, 1199 metadata_op_max 1200}; 1201 1202struct mdp_blend_cfg { 1203 uint32_t is_premultiplied; 1204}; 1205 1206struct mdp_mixer_cfg { 1207 uint32_t writeback_format; 1208 uint32_t alpha; 1209}; 1210 1211struct mdss_hw_caps { 1212 uint32_t mdp_rev; 1213 uint8_t rgb_pipes; 1214 uint8_t vig_pipes; 1215 uint8_t dma_pipes; 1216 uint8_t max_smp_cnt; 1217 uint8_t smp_per_pipe; 1218 uint32_t features; 1219}; 1220 1221struct msmfb_metadata { 1222 uint32_t op; 1223 uint32_t flags; 1224 union { 1225 struct mdp_misr misr_request; 1226 struct mdp_blend_cfg blend_cfg; 1227 struct mdp_mixer_cfg mixer_cfg; 1228 uint32_t panel_frame_rate; 1229 uint32_t video_info_code; 1230 struct mdss_hw_caps caps; 1231 uint8_t secure_en; 1232 int fbmem_ionfd; 1233 } data; 1234}; 1235 1236#define MDP_MAX_FENCE_FD 32 1237#define MDP_BUF_SYNC_FLAG_WAIT 1 1238#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1239 1240struct mdp_buf_sync { 1241 uint32_t flags; 1242 uint32_t acq_fen_fd_cnt; 1243 uint32_t session_id; 1244 int *acq_fen_fd; 1245 int *rel_fen_fd; 1246 int *retire_fen_fd; 1247}; 1248 1249struct mdp_async_blit_req_list { 1250 struct mdp_buf_sync sync; 1251 uint32_t count; 1252 struct mdp_blit_req req[]; 1253}; 1254 1255#define MDP_DISPLAY_COMMIT_OVERLAY 1 1256 1257struct mdp_display_commit { 1258 uint32_t flags; 1259 uint32_t wait_for_finish; 1260 struct fb_var_screeninfo var; 1261 /* 1262 * user needs to follow guidelines as per below rules 1263 * 1. source split is enabled: l_roi = roi and r_roi = 0 1264 * 2. source split is disabled: 1265 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1266 * 2.2 non split display: l_roi = roi and r_roi = 0 1267 */ 1268 struct mdp_rect l_roi; 1269 struct mdp_rect r_roi; 1270}; 1271 1272/** 1273 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1274 * @num_overlays: Number of overlay layers as part of the frame. 1275 * @overlay_list: Pointer to a list of overlay structures identifying 1276 * the layers as part of the frame 1277 * @flags: Flags can be used to extend behavior. 1278 * @processed_overlays: Output parameter indicating how many pipes were 1279 * successful. If there are no errors this number should 1280 * match num_overlays. Otherwise it will indicate the last 1281 * successful index for overlay that couldn't be set. 1282 */ 1283struct mdp_overlay_list { 1284 uint32_t num_overlays; 1285 struct mdp_overlay **overlay_list; 1286 uint32_t flags; 1287 uint32_t processed_overlays; 1288}; 1289 1290struct mdp_page_protection { 1291 uint32_t page_protection; 1292}; 1293 1294 1295struct mdp_mixer_info { 1296 int pndx; 1297 int pnum; 1298 int ptype; 1299 int mixer_num; 1300 int z_order; 1301}; 1302 1303#define MAX_PIPE_PER_MIXER 7 1304 1305struct msmfb_mixer_info_req { 1306 int mixer_num; 1307 int cnt; 1308 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1309}; 1310 1311enum { 1312 DISPLAY_SUBSYSTEM_ID, 1313 ROTATOR_SUBSYSTEM_ID, 1314}; 1315 1316enum { 1317 MDP_IOMMU_DOMAIN_CP, 1318 MDP_IOMMU_DOMAIN_NS, 1319}; 1320 1321enum { 1322 MDP_WRITEBACK_MIRROR_OFF, 1323 MDP_WRITEBACK_MIRROR_ON, 1324 MDP_WRITEBACK_MIRROR_PAUSE, 1325 MDP_WRITEBACK_MIRROR_RESUME, 1326}; 1327 1328enum mdp_color_space { 1329 MDP_CSC_ITU_R_601, 1330 MDP_CSC_ITU_R_601_FR, 1331 MDP_CSC_ITU_R_709, 1332}; 1333 1334enum { 1335 mdp_igc_v1_7 = 1, 1336 mdp_igc_vmax, 1337 mdp_hist_lut_v1_7, 1338 mdp_hist_lut_vmax, 1339 mdp_pgc_v1_7, 1340 mdp_pgc_vmax, 1341 mdp_dither_v1_7, 1342 mdp_dither_vmax, 1343 mdp_gamut_v1_7, 1344 mdp_gamut_vmax, 1345 mdp_pa_v1_7, 1346 mdp_pa_vmax, 1347 mdp_pcc_v1_7, 1348 mdp_pcc_vmax, 1349 mdp_pp_legacy, 1350}; 1351 1352/* PP Features */ 1353enum { 1354 IGC = 1, 1355 PCC, 1356 GC, 1357 PA, 1358 GAMUT, 1359 DITHER, 1360 QSEED, 1361 HIST_LUT, 1362 HIST, 1363 PP_FEATURE_MAX, 1364}; 1365 1366struct mdp_pp_feature_version { 1367 uint32_t pp_feature; 1368 uint32_t version_info; 1369}; 1370#endif /* _MSM_MDP_H_*/ 1371