msm_mdp.h revision a1582f49b9f19a98dc22559814b7595c9a8e4488
1#ifndef _UAPI_MSM_MDP_H_ 2#define _UAPI_MSM_MDP_H_ 3 4#include <linux/types.h> 5#include <linux/fb.h> 6 7#define MSMFB_IOCTL_MAGIC 'm' 8#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15/* new ioctls's for set/get ccs matrix */ 16#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 71#define FB_TYPE_3D_PANEL 0x10101010 72#define MDP_IMGTYPE2_START 0x10000 73#define MSMFB_DRIVER_VERSION 0xF9E8D701 74 75/* HW Revisions for different MDSS targets */ 76#define MDSS_GET_MAJOR(rev) ((rev) >> 28) 77#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 78#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 79#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 80 81#define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 82 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 83 84#define MDSS_MDP_REV(major, minor, step) \ 85 ((((major) & 0x000F) << 28) | \ 86 (((minor) & 0x0FFF) << 16) | \ 87 ((step) & 0xFFFF)) 88 89#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 90#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 91#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 92#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 93#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 94#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 95#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 96#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 97#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 98 99enum { 100 NOTIFY_UPDATE_START, 101 NOTIFY_UPDATE_STOP, 102 NOTIFY_UPDATE_POWER_OFF, 103}; 104 105enum { 106 NOTIFY_TYPE_NO_UPDATE, 107 NOTIFY_TYPE_SUSPEND, 108 NOTIFY_TYPE_UPDATE, 109}; 110 111enum { 112 MDP_RGB_565, /* RGB 565 planer */ 113 MDP_XRGB_8888, /* RGB 888 padded */ 114 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 115 MDP_Y_CBCR_H2V2_ADRENO, 116 MDP_ARGB_8888, /* ARGB 888 */ 117 MDP_RGB_888, /* RGB 888 planer */ 118 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 119 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 120 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 121 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 122 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 123 MDP_Y_CRCB_H1V2, 124 MDP_Y_CBCR_H1V2, 125 MDP_RGBA_8888, /* ARGB 888 */ 126 MDP_BGRA_8888, /* ABGR 888 */ 127 MDP_RGBX_8888, /* RGBX 888 */ 128 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 129 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 130 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 131 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 132 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 133 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 134 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 135 MDP_YCRCB_H1V1, /* YCrCb interleave */ 136 MDP_YCBCR_H1V1, /* YCbCr interleave */ 137 MDP_BGR_565, /* BGR 565 planer */ 138 MDP_BGR_888, /* BGR 888 */ 139 MDP_Y_CBCR_H2V2_VENUS, 140 MDP_BGRX_8888, /* BGRX 8888 */ 141 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 142 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 143 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 144 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 145 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 146 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 147 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 148 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 149 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 150 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 151 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 152 MDP_IMGTYPE_LIMIT, 153 MDP_RGB_BORDERFILL, /* border fill pipe */ 154 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 155 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 156}; 157 158enum { 159 PMEM_IMG, 160 FB_IMG, 161}; 162 163enum { 164 HSIC_HUE = 0, 165 HSIC_SAT, 166 HSIC_INT, 167 HSIC_CON, 168 NUM_HSIC_PARAM, 169}; 170 171#define MDSS_MDP_ROT_ONLY 0x80 172#define MDSS_MDP_RIGHT_MIXER 0x100 173#define MDSS_MDP_DUAL_PIPE 0x200 174 175/* mdp_blit_req flag values */ 176#define MDP_ROT_NOP 0 177#define MDP_FLIP_LR 0x1 178#define MDP_FLIP_UD 0x2 179#define MDP_ROT_90 0x4 180#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 181#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 182#define MDP_DITHER 0x8 183#define MDP_BLUR 0x10 184#define MDP_BLEND_FG_PREMULT 0x20000 185#define MDP_IS_FG 0x40000 186#define MDP_SOLID_FILL 0x00000020 187#define MDP_VPU_PIPE 0x00000040 188#define MDP_DEINTERLACE 0x80000000 189#define MDP_SHARPENING 0x40000000 190#define MDP_NO_DMA_BARRIER_START 0x20000000 191#define MDP_NO_DMA_BARRIER_END 0x10000000 192#define MDP_NO_BLIT 0x08000000 193#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 194#define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 195 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 196#define MDP_BLIT_SRC_GEM 0x04000000 197#define MDP_BLIT_DST_GEM 0x02000000 198#define MDP_BLIT_NON_CACHED 0x01000000 199#define MDP_OV_PIPE_SHARE 0x00800000 200#define MDP_DEINTERLACE_ODD 0x00400000 201#define MDP_OV_PLAY_NOWAIT 0x00200000 202#define MDP_SOURCE_ROTATED_90 0x00100000 203#define MDP_OVERLAY_PP_CFG_EN 0x00080000 204#define MDP_BACKEND_COMPOSITION 0x00040000 205#define MDP_BORDERFILL_SUPPORTED 0x00010000 206#define MDP_SECURE_OVERLAY_SESSION 0x00008000 207#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 208#define MDP_OV_PIPE_FORCE_DMA 0x00004000 209#define MDP_MEMORY_ID_TYPE_FB 0x00001000 210#define MDP_BWC_EN 0x00000400 211#define MDP_DECIMATION_EN 0x00000800 212#define MDP_TRANSP_NOP 0xffffffff 213#define MDP_ALPHA_NOP 0xff 214 215#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 216#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 217#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 218#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 219#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 220/* Sentinel: Don't use! */ 221#define MDP_FB_PAGE_PROTECTION_INVALID (5) 222/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 223#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 224 225struct mdp_rect { 226 uint32_t x; 227 uint32_t y; 228 uint32_t w; 229 uint32_t h; 230}; 231 232struct mdp_img { 233 uint32_t width; 234 uint32_t height; 235 uint32_t format; 236 uint32_t offset; 237 int memory_id; /* the file descriptor */ 238 uint32_t priv; 239}; 240 241/* 242 * {3x3} + {3} ccs matrix 243 */ 244 245#define MDP_CCS_RGB2YUV 0 246#define MDP_CCS_YUV2RGB 1 247 248#define MDP_CCS_SIZE 9 249#define MDP_BV_SIZE 3 250 251struct mdp_ccs { 252 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 253 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 254 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 255}; 256 257struct mdp_csc { 258 int id; 259 uint32_t csc_mv[9]; 260 uint32_t csc_pre_bv[3]; 261 uint32_t csc_post_bv[3]; 262 uint32_t csc_pre_lv[6]; 263 uint32_t csc_post_lv[6]; 264}; 265 266/* The version of the mdp_blit_req structure so that 267 * user applications can selectively decide which functionality 268 * to include 269 */ 270 271#define MDP_BLIT_REQ_VERSION 2 272 273struct color { 274 uint32_t r; 275 uint32_t g; 276 uint32_t b; 277 uint32_t alpha; 278}; 279 280struct mdp_blit_req { 281 struct mdp_img src; 282 struct mdp_img dst; 283 struct mdp_rect src_rect; 284 struct mdp_rect dst_rect; 285 struct color const_color; 286 uint32_t alpha; 287 uint32_t transp_mask; 288 uint32_t flags; 289 int sharpening_strength; /* -127 <--> 127, default 64 */ 290}; 291 292struct mdp_blit_req_list { 293 uint32_t count; 294 struct mdp_blit_req req[]; 295}; 296 297#define MSMFB_DATA_VERSION 2 298 299struct msmfb_data { 300 uint32_t offset; 301 int memory_id; 302 int id; 303 uint32_t flags; 304 uint32_t priv; 305 uint32_t iova; 306}; 307 308#define MSMFB_NEW_REQUEST -1 309 310struct msmfb_overlay_data { 311 uint32_t id; 312 struct msmfb_data data; 313 uint32_t version_key; 314 struct msmfb_data plane1_data; 315 struct msmfb_data plane2_data; 316 struct msmfb_data dst_data; 317}; 318 319struct msmfb_img { 320 uint32_t width; 321 uint32_t height; 322 uint32_t format; 323}; 324 325#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 326struct msmfb_writeback_data { 327 struct msmfb_data buf_info; 328 struct msmfb_img img; 329}; 330 331#define MDP_PP_OPS_ENABLE 0x1 332#define MDP_PP_OPS_READ 0x2 333#define MDP_PP_OPS_WRITE 0x4 334#define MDP_PP_OPS_DISABLE 0x8 335#define MDP_PP_IGC_FLAG_ROM0 0x10 336#define MDP_PP_IGC_FLAG_ROM1 0x20 337 338#define MDP_PP_PA_HUE_ENABLE 0x10 339#define MDP_PP_PA_SAT_ENABLE 0x20 340#define MDP_PP_PA_VAL_ENABLE 0x40 341#define MDP_PP_PA_CONT_ENABLE 0x80 342#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 343#define MDP_PP_PA_SKIN_ENABLE 0x200 344#define MDP_PP_PA_SKY_ENABLE 0x400 345#define MDP_PP_PA_FOL_ENABLE 0x800 346#define MDP_PP_PA_HUE_MASK 0x1000 347#define MDP_PP_PA_SAT_MASK 0x2000 348#define MDP_PP_PA_VAL_MASK 0x4000 349#define MDP_PP_PA_CONT_MASK 0x8000 350#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 351#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 352#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 353#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 354#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 355#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 356#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 357#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 358 359#define MDSS_PP_DSPP_CFG 0x000 360#define MDSS_PP_SSPP_CFG 0x100 361#define MDSS_PP_LM_CFG 0x200 362#define MDSS_PP_WB_CFG 0x300 363 364#define MDSS_PP_ARG_MASK 0x3C00 365#define MDSS_PP_ARG_NUM 4 366#define MDSS_PP_ARG_SHIFT 10 367#define MDSS_PP_LOCATION_MASK 0x0300 368#define MDSS_PP_LOGICAL_MASK 0x00FF 369 370#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 371#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 372#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 373#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 374 375 376struct mdp_qseed_cfg { 377 uint32_t table_num; 378 uint32_t ops; 379 uint32_t len; 380 uint32_t *data; 381}; 382 383struct mdp_sharp_cfg { 384 uint32_t flags; 385 uint32_t strength; 386 uint32_t edge_thr; 387 uint32_t smooth_thr; 388 uint32_t noise_thr; 389}; 390 391struct mdp_qseed_cfg_data { 392 uint32_t block; 393 struct mdp_qseed_cfg qseed_data; 394}; 395 396#define MDP_OVERLAY_PP_CSC_CFG 0x1 397#define MDP_OVERLAY_PP_QSEED_CFG 0x2 398#define MDP_OVERLAY_PP_PA_CFG 0x4 399#define MDP_OVERLAY_PP_IGC_CFG 0x8 400#define MDP_OVERLAY_PP_SHARP_CFG 0x10 401#define MDP_OVERLAY_PP_HIST_CFG 0x20 402#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 403#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 404 405#define MDP_CSC_FLAG_ENABLE 0x1 406#define MDP_CSC_FLAG_YUV_IN 0x2 407#define MDP_CSC_FLAG_YUV_OUT 0x4 408 409struct mdp_csc_cfg { 410 /* flags for enable CSC, toggling RGB,YUV input/output */ 411 uint32_t flags; 412 uint32_t csc_mv[9]; 413 uint32_t csc_pre_bv[3]; 414 uint32_t csc_post_bv[3]; 415 uint32_t csc_pre_lv[6]; 416 uint32_t csc_post_lv[6]; 417}; 418 419struct mdp_csc_cfg_data { 420 uint32_t block; 421 struct mdp_csc_cfg csc_data; 422}; 423 424struct mdp_pa_cfg { 425 uint32_t flags; 426 uint32_t hue_adj; 427 uint32_t sat_adj; 428 uint32_t val_adj; 429 uint32_t cont_adj; 430}; 431 432struct mdp_pa_mem_col_cfg { 433 uint32_t color_adjust_p0; 434 uint32_t color_adjust_p1; 435 uint32_t hue_region; 436 uint32_t sat_region; 437 uint32_t val_region; 438}; 439 440#define MDP_SIX_ZONE_LUT_SIZE 384 441 442struct mdp_pa_v2_data { 443 /* Mask bits for PA features */ 444 uint32_t flags; 445 uint32_t global_hue_adj; 446 uint32_t global_sat_adj; 447 uint32_t global_val_adj; 448 uint32_t global_cont_adj; 449 struct mdp_pa_mem_col_cfg skin_cfg; 450 struct mdp_pa_mem_col_cfg sky_cfg; 451 struct mdp_pa_mem_col_cfg fol_cfg; 452 uint32_t six_zone_len; 453 uint32_t six_zone_thresh; 454 uint32_t *six_zone_curve_p0; 455 uint32_t *six_zone_curve_p1; 456}; 457 458struct mdp_igc_lut_data { 459 uint32_t block; 460 uint32_t len, ops; 461 uint32_t *c0_c1_data; 462 uint32_t *c2_data; 463}; 464 465struct mdp_histogram_cfg { 466 uint32_t ops; 467 uint32_t block; 468 uint8_t frame_cnt; 469 uint8_t bit_mask; 470 uint16_t num_bins; 471}; 472 473struct mdp_hist_lut_data { 474 uint32_t block; 475 uint32_t ops; 476 uint32_t len; 477 uint32_t *data; 478}; 479 480struct mdp_overlay_pp_params { 481 uint32_t config_ops; 482 struct mdp_csc_cfg csc_cfg; 483 struct mdp_qseed_cfg qseed_cfg[2]; 484 struct mdp_pa_cfg pa_cfg; 485 struct mdp_pa_v2_data pa_v2_cfg; 486 struct mdp_igc_lut_data igc_cfg; 487 struct mdp_sharp_cfg sharp_cfg; 488 struct mdp_histogram_cfg hist_cfg; 489 struct mdp_hist_lut_data hist_lut_cfg; 490}; 491 492/** 493 * enum mdss_mdp_blend_op - Different blend operations set by userspace 494 * 495 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 496 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 497 * would appear opaque in case fg plane alpha is 498 * 0xff. 499 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 500 * alpha pre-multiplication done. If fg plane alpha 501 * is less than 0xff, apply modulation as well. This 502 * operation is intended on layers having alpha 503 * channel. 504 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 505 * pre-multiplied. Apply pre-multiplication. If fg 506 * plane alpha is less than 0xff, apply modulation as 507 * well. 508 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 509 * mdp. 510 */ 511enum mdss_mdp_blend_op { 512 BLEND_OP_NOT_DEFINED = 0, 513 BLEND_OP_OPAQUE, 514 BLEND_OP_PREMULTIPLIED, 515 BLEND_OP_COVERAGE, 516 BLEND_OP_MAX, 517}; 518 519#define MAX_PLANES 4 520struct mdp_scale_data { 521 uint8_t enable_pxl_ext; 522 523 int init_phase_x[MAX_PLANES]; 524 int phase_step_x[MAX_PLANES]; 525 int init_phase_y[MAX_PLANES]; 526 int phase_step_y[MAX_PLANES]; 527 528 int num_ext_pxls_left[MAX_PLANES]; 529 int num_ext_pxls_right[MAX_PLANES]; 530 int num_ext_pxls_top[MAX_PLANES]; 531 int num_ext_pxls_btm[MAX_PLANES]; 532 533 int left_ftch[MAX_PLANES]; 534 int left_rpt[MAX_PLANES]; 535 int right_ftch[MAX_PLANES]; 536 int right_rpt[MAX_PLANES]; 537 538 int top_rpt[MAX_PLANES]; 539 int btm_rpt[MAX_PLANES]; 540 int top_ftch[MAX_PLANES]; 541 int btm_ftch[MAX_PLANES]; 542 543 uint32_t roi_w[MAX_PLANES]; 544}; 545 546/** 547 * struct mdp_overlay - overlay surface structure 548 * @src: Source image information (width, height, format). 549 * @src_rect: Source crop rectangle, portion of image that will be fetched. 550 * This should always be within boundaries of source image. 551 * @dst_rect: Destination rectangle, the position and size of image on screen. 552 * This should always be within panel boundaries. 553 * @z_order: Blending stage to occupy in display, if multiple layers are 554 * present, highest z_order usually means the top most visible 555 * layer. The range acceptable is from 0-3 to support blending 556 * up to 4 layers. 557 * @is_fg: This flag is used to disable blending of any layers with z_order 558 * less than this overlay. It means that any layers with z_order 559 * less than this layer will not be blended and will be replaced 560 * by the background border color. 561 * @alpha: Used to set plane opacity. The range can be from 0-255, where 562 * 0 means completely transparent and 255 means fully opaque. 563 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 564 * image matching this color will be transparent when blending. 565 * The color should be in same format as the source image format. 566 * @flags: This is used to customize operation of overlay. See MDP flags 567 * for more information. 568 * @user_data: DEPRECATED* Used to store user application specific information. 569 * @bg_color: Solid color used to fill the overlay surface when no source 570 * buffer is provided. 571 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 572 * dropped for each pixel that is fetched from a line. The value 573 * given should be power of two of decimation amount. 574 * 0: no decimation 575 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 576 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 577 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 578 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 579 * @vert_deci: Vertical decimation value, this indicates the amount of lines 580 * dropped for each line that is fetched from overlay. The value 581 * given should be power of two of decimation amount. 582 * 0: no decimation 583 * 1: decimation by 2 (drop 1 line for each line fetched) 584 * 2: decimation by 4 (drop 3 lines for each line fetched) 585 * 3: decimation by 8 (drop 7 lines for each line fetched) 586 * 4: decimation by 16 (drop 15 lines for each line fetched) 587 * @overlay_pp_cfg: Overlay post processing configuration, for more information 588 * see struct mdp_overlay_pp_params. 589 */ 590struct mdp_overlay { 591 struct msmfb_img src; 592 struct mdp_rect src_rect; 593 struct mdp_rect dst_rect; 594 uint32_t z_order; /* stage number */ 595 uint32_t is_fg; /* control alpha & transp */ 596 uint32_t alpha; 597 uint32_t blend_op; 598 uint32_t transp_mask; 599 uint32_t flags; 600 uint32_t id; 601 uint32_t user_data[6]; 602 uint32_t bg_color; 603 uint8_t horz_deci; 604 uint8_t vert_deci; 605 struct mdp_overlay_pp_params overlay_pp_cfg; 606 struct mdp_scale_data scale; 607}; 608 609struct msmfb_overlay_3d { 610 uint32_t is_3d; 611 uint32_t width; 612 uint32_t height; 613}; 614 615 616struct msmfb_overlay_blt { 617 uint32_t enable; 618 uint32_t offset; 619 uint32_t width; 620 uint32_t height; 621 uint32_t bpp; 622}; 623 624struct mdp_histogram { 625 uint32_t frame_cnt; 626 uint32_t bin_cnt; 627 uint32_t *r; 628 uint32_t *g; 629 uint32_t *b; 630}; 631 632#define MISR_CRC_BATCH_SIZE 32 633enum { 634 DISPLAY_MISR_EDP, 635 DISPLAY_MISR_DSI0, 636 DISPLAY_MISR_DSI1, 637 DISPLAY_MISR_HDMI, 638 DISPLAY_MISR_LCDC, 639 DISPLAY_MISR_MDP, 640 DISPLAY_MISR_ATV, 641 DISPLAY_MISR_DSI_CMD, 642 DISPLAY_MISR_MAX 643}; 644 645enum { 646 MISR_OP_NONE, 647 MISR_OP_SFM, 648 MISR_OP_MFM, 649 MISR_OP_BM, 650 MISR_OP_MAX 651}; 652 653struct mdp_misr { 654 uint32_t block_id; 655 uint32_t frame_count; 656 uint32_t crc_op_mode; 657 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 658}; 659 660/* 661 662 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 663 664 MDP_BLOCK_RESERVED is provided for backward compatibility and is 665 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 666 instead. 667 668 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 669 same for others. 670 671*/ 672 673enum { 674 MDP_BLOCK_RESERVED = 0, 675 MDP_BLOCK_OVERLAY_0, 676 MDP_BLOCK_OVERLAY_1, 677 MDP_BLOCK_VG_1, 678 MDP_BLOCK_VG_2, 679 MDP_BLOCK_RGB_1, 680 MDP_BLOCK_RGB_2, 681 MDP_BLOCK_DMA_P, 682 MDP_BLOCK_DMA_S, 683 MDP_BLOCK_DMA_E, 684 MDP_BLOCK_OVERLAY_2, 685 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 686 MDP_LOGICAL_BLOCK_DISP_1, 687 MDP_LOGICAL_BLOCK_DISP_2, 688 MDP_BLOCK_MAX, 689}; 690 691/* 692 * mdp_histogram_start_req is used to provide the parameters for 693 * histogram start request 694 */ 695 696struct mdp_histogram_start_req { 697 uint32_t block; 698 uint8_t frame_cnt; 699 uint8_t bit_mask; 700 uint16_t num_bins; 701}; 702 703/* 704 * mdp_histogram_data is used to return the histogram data, once 705 * the histogram is done/stopped/cance 706 */ 707 708struct mdp_histogram_data { 709 uint32_t block; 710 uint32_t bin_cnt; 711 uint32_t *c0; 712 uint32_t *c1; 713 uint32_t *c2; 714 uint32_t *extra_info; 715}; 716 717struct mdp_pcc_coeff { 718 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 719}; 720 721struct mdp_pcc_cfg_data { 722 uint32_t block; 723 uint32_t ops; 724 struct mdp_pcc_coeff r, g, b; 725}; 726 727#define MDP_GAMUT_TABLE_NUM 8 728 729enum { 730 mdp_lut_igc, 731 mdp_lut_pgc, 732 mdp_lut_hist, 733 mdp_lut_max, 734}; 735 736struct mdp_ar_gc_lut_data { 737 uint32_t x_start; 738 uint32_t slope; 739 uint32_t offset; 740}; 741 742struct mdp_pgc_lut_data { 743 uint32_t block; 744 uint32_t flags; 745 uint8_t num_r_stages; 746 uint8_t num_g_stages; 747 uint8_t num_b_stages; 748 struct mdp_ar_gc_lut_data *r_data; 749 struct mdp_ar_gc_lut_data *g_data; 750 struct mdp_ar_gc_lut_data *b_data; 751}; 752 753 754struct mdp_lut_cfg_data { 755 uint32_t lut_type; 756 union { 757 struct mdp_igc_lut_data igc_lut_data; 758 struct mdp_pgc_lut_data pgc_lut_data; 759 struct mdp_hist_lut_data hist_lut_data; 760 } data; 761}; 762 763struct mdp_bl_scale_data { 764 uint32_t min_lvl; 765 uint32_t scale; 766}; 767 768struct mdp_pa_cfg_data { 769 uint32_t block; 770 struct mdp_pa_cfg pa_data; 771}; 772 773struct mdp_pa_v2_cfg_data { 774 uint32_t block; 775 struct mdp_pa_v2_data pa_v2_data; 776}; 777 778struct mdp_dither_cfg_data { 779 uint32_t block; 780 uint32_t flags; 781 uint32_t g_y_depth; 782 uint32_t r_cr_depth; 783 uint32_t b_cb_depth; 784}; 785 786struct mdp_gamut_cfg_data { 787 uint32_t block; 788 uint32_t flags; 789 uint32_t gamut_first; 790 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 791 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 792 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 793 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 794}; 795 796struct mdp_calib_config_data { 797 uint32_t ops; 798 uint32_t addr; 799 uint32_t data; 800}; 801 802struct mdp_calib_config_buffer { 803 uint32_t ops; 804 uint32_t size; 805 uint32_t *buffer; 806}; 807 808struct mdp_calib_dcm_state { 809 uint32_t ops; 810 uint32_t dcm_state; 811}; 812 813enum { 814 DCM_UNINIT, 815 DCM_UNBLANK, 816 DCM_ENTER, 817 DCM_EXIT, 818 DCM_BLANK, 819 DTM_ENTER, 820 DTM_EXIT, 821}; 822 823#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 824#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 825#define MDSS_PP_SPLIT_MASK 0x30000000 826 827#define MDSS_MAX_BL_BRIGHTNESS 255 828#define AD_BL_LIN_LEN 256 829#define AD_BL_ATT_LUT_LEN 33 830 831#define MDSS_AD_MODE_AUTO_BL 0x0 832#define MDSS_AD_MODE_AUTO_STR 0x1 833#define MDSS_AD_MODE_TARG_STR 0x3 834#define MDSS_AD_MODE_MAN_STR 0x7 835#define MDSS_AD_MODE_CALIB 0xF 836 837#define MDP_PP_AD_INIT 0x10 838#define MDP_PP_AD_CFG 0x20 839 840struct mdss_ad_init { 841 uint32_t asym_lut[33]; 842 uint32_t color_corr_lut[33]; 843 uint8_t i_control[2]; 844 uint16_t black_lvl; 845 uint16_t white_lvl; 846 uint8_t var; 847 uint8_t limit_ampl; 848 uint8_t i_dither; 849 uint8_t slope_max; 850 uint8_t slope_min; 851 uint8_t dither_ctl; 852 uint8_t format; 853 uint8_t auto_size; 854 uint16_t frame_w; 855 uint16_t frame_h; 856 uint8_t logo_v; 857 uint8_t logo_h; 858 uint32_t alpha; 859 uint32_t alpha_base; 860 uint32_t bl_lin_len; 861 uint32_t bl_att_len; 862 uint32_t *bl_lin; 863 uint32_t *bl_lin_inv; 864 uint32_t *bl_att_lut; 865}; 866 867#define MDSS_AD_BL_CTRL_MODE_EN 1 868#define MDSS_AD_BL_CTRL_MODE_DIS 0 869struct mdss_ad_cfg { 870 uint32_t mode; 871 uint32_t al_calib_lut[33]; 872 uint16_t backlight_min; 873 uint16_t backlight_max; 874 uint16_t backlight_scale; 875 uint16_t amb_light_min; 876 uint16_t filter[2]; 877 uint16_t calib[4]; 878 uint8_t strength_limit; 879 uint8_t t_filter_recursion; 880 uint16_t stab_itr; 881 uint32_t bl_ctrl_mode; 882}; 883 884/* ops uses standard MDP_PP_* flags */ 885struct mdss_ad_init_cfg { 886 uint32_t ops; 887 union { 888 struct mdss_ad_init init; 889 struct mdss_ad_cfg cfg; 890 } params; 891}; 892 893/* mode uses MDSS_AD_MODE_* flags */ 894struct mdss_ad_input { 895 uint32_t mode; 896 union { 897 uint32_t amb_light; 898 uint32_t strength; 899 uint32_t calib_bl; 900 } in; 901 uint32_t output; 902}; 903 904#define MDSS_CALIB_MODE_BL 0x1 905struct mdss_calib_cfg { 906 uint32_t ops; 907 uint32_t calib_mask; 908}; 909 910enum { 911 mdp_op_pcc_cfg, 912 mdp_op_csc_cfg, 913 mdp_op_lut_cfg, 914 mdp_op_qseed_cfg, 915 mdp_bl_scale_cfg, 916 mdp_op_pa_cfg, 917 mdp_op_pa_v2_cfg, 918 mdp_op_dither_cfg, 919 mdp_op_gamut_cfg, 920 mdp_op_calib_cfg, 921 mdp_op_ad_cfg, 922 mdp_op_ad_input, 923 mdp_op_calib_mode, 924 mdp_op_calib_buffer, 925 mdp_op_calib_dcm_state, 926 mdp_op_max, 927}; 928 929enum { 930 WB_FORMAT_NV12, 931 WB_FORMAT_RGB_565, 932 WB_FORMAT_RGB_888, 933 WB_FORMAT_xRGB_8888, 934 WB_FORMAT_ARGB_8888, 935 WB_FORMAT_BGRA_8888, 936 WB_FORMAT_BGRX_8888, 937 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 938}; 939 940struct msmfb_mdp_pp { 941 uint32_t op; 942 union { 943 struct mdp_pcc_cfg_data pcc_cfg_data; 944 struct mdp_csc_cfg_data csc_cfg_data; 945 struct mdp_lut_cfg_data lut_cfg_data; 946 struct mdp_qseed_cfg_data qseed_cfg_data; 947 struct mdp_bl_scale_data bl_scale_data; 948 struct mdp_pa_cfg_data pa_cfg_data; 949 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 950 struct mdp_dither_cfg_data dither_cfg_data; 951 struct mdp_gamut_cfg_data gamut_cfg_data; 952 struct mdp_calib_config_data calib_cfg; 953 struct mdss_ad_init_cfg ad_init_cfg; 954 struct mdss_calib_cfg mdss_calib_cfg; 955 struct mdss_ad_input ad_input; 956 struct mdp_calib_config_buffer calib_buffer; 957 struct mdp_calib_dcm_state calib_dcm; 958 } data; 959}; 960 961#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 962enum { 963 metadata_op_none, 964 metadata_op_base_blend, 965 metadata_op_frame_rate, 966 metadata_op_vic, 967 metadata_op_wb_format, 968 metadata_op_wb_secure, 969 metadata_op_get_caps, 970 metadata_op_crc, 971 metadata_op_max 972}; 973 974struct mdp_blend_cfg { 975 uint32_t is_premultiplied; 976}; 977 978struct mdp_mixer_cfg { 979 uint32_t writeback_format; 980 uint32_t alpha; 981}; 982 983struct mdss_hw_caps { 984 uint32_t mdp_rev; 985 uint8_t rgb_pipes; 986 uint8_t vig_pipes; 987 uint8_t dma_pipes; 988 uint8_t max_smp_cnt; 989 uint8_t smp_per_pipe; 990 uint32_t features; 991}; 992 993struct msmfb_metadata { 994 uint32_t op; 995 uint32_t flags; 996 union { 997 struct mdp_misr misr_request; 998 struct mdp_blend_cfg blend_cfg; 999 struct mdp_mixer_cfg mixer_cfg; 1000 uint32_t panel_frame_rate; 1001 uint32_t video_info_code; 1002 struct mdss_hw_caps caps; 1003 uint8_t secure_en; 1004 } data; 1005}; 1006 1007#define MDP_MAX_FENCE_FD 32 1008#define MDP_BUF_SYNC_FLAG_WAIT 1 1009#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1010 1011struct mdp_buf_sync { 1012 uint32_t flags; 1013 uint32_t acq_fen_fd_cnt; 1014 uint32_t session_id; 1015 int *acq_fen_fd; 1016 int *rel_fen_fd; 1017 int *retire_fen_fd; 1018}; 1019 1020struct mdp_async_blit_req_list { 1021 struct mdp_buf_sync sync; 1022 uint32_t count; 1023 struct mdp_blit_req req[]; 1024}; 1025 1026#define MDP_DISPLAY_COMMIT_OVERLAY 1 1027 1028struct mdp_display_commit { 1029 uint32_t flags; 1030 uint32_t wait_for_finish; 1031 struct fb_var_screeninfo var; 1032 struct mdp_rect roi; 1033}; 1034 1035/** 1036 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1037 * @num_overlays: Number of overlay layers as part of the frame. 1038 * @overlay_list: Pointer to a list of overlay structures identifying 1039 * the layers as part of the frame 1040 * @flags: Flags can be used to extend behavior. 1041 * @processed_overlays: Output parameter indicating how many pipes were 1042 * successful. If there are no errors this number should 1043 * match num_overlays. Otherwise it will indicate the last 1044 * successful index for overlay that couldn't be set. 1045 */ 1046struct mdp_overlay_list { 1047 uint32_t num_overlays; 1048 struct mdp_overlay **overlay_list; 1049 uint32_t flags; 1050 uint32_t processed_overlays; 1051}; 1052 1053struct mdp_page_protection { 1054 uint32_t page_protection; 1055}; 1056 1057 1058struct mdp_mixer_info { 1059 int pndx; 1060 int pnum; 1061 int ptype; 1062 int mixer_num; 1063 int z_order; 1064}; 1065 1066#define MAX_PIPE_PER_MIXER 4 1067 1068struct msmfb_mixer_info_req { 1069 int mixer_num; 1070 int cnt; 1071 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1072}; 1073 1074enum { 1075 DISPLAY_SUBSYSTEM_ID, 1076 ROTATOR_SUBSYSTEM_ID, 1077}; 1078 1079enum { 1080 MDP_IOMMU_DOMAIN_CP, 1081 MDP_IOMMU_DOMAIN_NS, 1082}; 1083 1084enum { 1085 MDP_WRITEBACK_MIRROR_OFF, 1086 MDP_WRITEBACK_MIRROR_ON, 1087 MDP_WRITEBACK_MIRROR_PAUSE, 1088 MDP_WRITEBACK_MIRROR_RESUME, 1089}; 1090#endif /*_UAPI_MSM_MDP_H_*/ 1091