1cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 2cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Video for Linux Two header file 3cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 4731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * Copyright (C) 1999-2012 the contributors 5cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 6cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * This program is free software; you can redistribute it and/or modify 7cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * it under the terms of the GNU General Public License as published by 8cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * the Free Software Foundation; either version 2 of the License, or 9cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * (at your option) any later version. 10cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 11cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * This program is distributed in the hope that it will be useful, 12cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * but WITHOUT ANY WARRANTY; without even the implied warranty of 13cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * GNU General Public License for more details. 15cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 16cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Alternatively you can redistribute this file under the terms of the 17cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * BSD license as stated below: 18cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 19cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Redistribution and use in source and binary forms, with or without 20cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * modification, are permitted provided that the following conditions 21cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * are met: 22cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1. Redistributions of source code must retain the above copyright 23cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * notice, this list of conditions and the following disclaimer. 24cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 2. Redistributions in binary form must reproduce the above copyright 25cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * notice, this list of conditions and the following disclaimer in 26cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * the documentation and/or other materials provided with the 27cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * distribution. 28cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 3. The names of its contributors may not be used to endorse or promote 29cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * products derived from this software without specific prior written 30cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * permission. 31cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 32cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 35cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 36cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 37cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 38cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 39cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 40cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 41cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 42cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 44cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Header file for v4l or V4L2 drivers and applications 45cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * with public API. 46cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * All kernel-specific stuff were moved to media/v4l2-dev.h, so 47cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * no #if __KERNEL tests are allowed here 48cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 49cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * See http://linuxtv.org for more info 50cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 51cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Author: Bill Dirks <bill@thedirks.org> 52cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Justin Schoeman 53cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Hans Verkuil <hverkuil@xs4all.nl> 54cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * et al. 55cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 56731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#ifndef _UAPI__LINUX_VIDEODEV2_H 57731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define _UAPI__LINUX_VIDEODEV2_H 58cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 59731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#ifndef __KERNEL__ 60cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#include <sys/time.h> 61cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#endif 62cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#include <linux/compiler.h> 63cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#include <linux/ioctl.h> 64cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#include <linux/types.h> 65731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#include <linux/v4l2-common.h> 66731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#include <linux/v4l2-controls.h> 67cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 68cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 69cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Common stuff for both V4L1 and V4L2 70cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Moved from videodev.h 71cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 72cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDEO_MAX_FRAME 32 73cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDEO_MAX_PLANES 8 74cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 75cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 76cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * M I S C E L L A N E O U S 77cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 78cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 79cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Four-character-code (FOURCC) */ 80cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define v4l2_fourcc(a, b, c, d)\ 81cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) 82cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 83cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 84cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * E N U M S 85cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 86cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_field { 87cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_ANY = 0, /* driver can choose from none, 88cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj top, bottom, interlaced 89cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj depending on whatever it thinks 90cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj is approximate ... */ 91cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_NONE = 1, /* this device has no fields ... */ 92cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_TOP = 2, /* top field only */ 93cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_BOTTOM = 3, /* bottom field only */ 94cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ 95cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one 96cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj buffer, top-bottom order */ 97cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ 98cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into 99cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj separate buffers */ 100cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_INTERLACED_TB = 8, /* both fields interlaced, top field 101cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj first and the top field is 102cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj transmitted first */ 103cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FIELD_INTERLACED_BT = 9, /* both fields interlaced, top field 104cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj first and the bottom field is 105cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj transmitted first */ 106cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 107cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FIELD_HAS_TOP(field) \ 108cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((field) == V4L2_FIELD_TOP ||\ 109cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED ||\ 110cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_TB ||\ 111cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_BT ||\ 112cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_TB ||\ 113cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_BT) 114cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FIELD_HAS_BOTTOM(field) \ 115cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((field) == V4L2_FIELD_BOTTOM ||\ 116cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED ||\ 117cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_TB ||\ 118cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_BT ||\ 119cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_TB ||\ 120cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_BT) 121cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FIELD_HAS_BOTH(field) \ 122cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((field) == V4L2_FIELD_INTERLACED ||\ 123cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_TB ||\ 124cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_INTERLACED_BT ||\ 125cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_TB ||\ 126cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (field) == V4L2_FIELD_SEQ_BT) 127cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 128cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_buf_type { 129cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, 130cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, 131cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, 132cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VBI_CAPTURE = 4, 133cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VBI_OUTPUT = 5, 134cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_SLICED_VBI_CAPTURE = 6, 135cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_SLICED_VBI_OUTPUT = 7, 136cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#if 1 137cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* Experimental */ 138cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY = 8, 139cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#endif 140cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9, 141cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, 142731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan /* Deprecated, do not use */ 143cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_BUF_TYPE_PRIVATE = 0x80, 144cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 145cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 146cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TYPE_IS_MULTIPLANAR(type) \ 147cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE \ 148cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 149cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 150cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TYPE_IS_OUTPUT(type) \ 151cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj ((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT \ 152cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE \ 153cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_VIDEO_OVERLAY \ 154cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY \ 155cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_VBI_OUTPUT \ 156cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj || (type) == V4L2_BUF_TYPE_SLICED_VBI_OUTPUT) 157cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 158cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_tuner_type { 159cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_TUNER_RADIO = 1, 160cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_TUNER_ANALOG_TV = 2, 161cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_TUNER_DIGITAL_TV = 3, 162cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 163cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 164cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_memory { 165cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_MEMORY_MMAP = 1, 166cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_MEMORY_USERPTR = 2, 167cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_MEMORY_OVERLAY = 3, 168731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan V4L2_MEMORY_DMABUF = 4, 169cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 170cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 171cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ 172cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_colorspace { 173cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* ITU-R 601 -- broadcast NTSC/PAL */ 174cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_SMPTE170M = 1, 175cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 176cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* 1125-Line (US) HDTV */ 177cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_SMPTE240M = 2, 178cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 179cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* HD and modern captures. */ 180cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_REC709 = 3, 181cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 182cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */ 183cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_BT878 = 4, 184cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 185cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* These should be useful. Assume 601 extents. */ 186cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_470_SYSTEM_M = 5, 187cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_470_SYSTEM_BG = 6, 188cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 189cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* I know there will be cameras that send this. So, this is 190cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * unspecified chromaticities and full 0-255 on each of the 191cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Y'CbCr components 192cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 193cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_JPEG = 7, 194cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 195cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* For RGB colourspaces, this is probably a good start. */ 196cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_COLORSPACE_SRGB = 8, 197cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 198cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 199cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_priority { 200cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_PRIORITY_UNSET = 0, /* not initialized */ 201cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_PRIORITY_BACKGROUND = 1, 202cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_PRIORITY_INTERACTIVE = 2, 203cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_PRIORITY_RECORD = 3, 204cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, 205cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 206cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 207cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_rect { 208cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 left; 209cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 top; 210cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 width; 211cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 height; 212cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 213cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 214cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_fract { 215cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 numerator; 216cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 denominator; 217cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 218cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 219cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 220cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP 221cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 222cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @driver: name of the driver module (e.g. "bttv") 223cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @card: name of the card (e.g. "Hauppauge WinTV") 224cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @bus_info: name of the bus (e.g. "PCI:" + pci_name(pci_dev) ) 225cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @version: KERNEL_VERSION 226cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @capabilities: capabilities of the physical device as a whole 227cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @device_caps: capabilities accessed via this particular device (node) 228cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @reserved: reserved fields for future extensions 229cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 230cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_capability { 231cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 driver[16]; 232cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 card[32]; 233cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 bus_info[32]; 234cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 version; 235cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capabilities; 236cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 device_caps; 237cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[3]; 238cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 239cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 240cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Values for 'capabilities' field */ 241cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ 242cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ 243cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ 244cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a raw VBI capture device */ 245cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a raw VBI output device */ 246cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ 247cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ 248cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ 249cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ 250cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ 251cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_RDS_OUTPUT 0x00000800 /* Is an RDS encoder */ 252cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 253cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Is a video capture device that supports multiplanar formats */ 254cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_CAPTURE_MPLANE 0x00001000 255cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Is a video output device that supports multiplanar formats */ 256cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_VIDEO_OUTPUT_MPLANE 0x00002000 257731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Is a video mem-to-mem device that supports multiplanar formats */ 258731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CAP_VIDEO_M2M_MPLANE 0x00004000 259731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Is a video mem-to-mem device */ 260731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CAP_VIDEO_M2M 0x00008000 261cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 262cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ 263cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ 264cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ 265cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_MODULATOR 0x00080000 /* has a modulator */ 266cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 267cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ 268cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ 269cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ 270cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 271cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_DEVICE_CAPS 0x80000000 /* sets device capabilities field */ 272cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 273cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 274cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V I D E O I M A G E F O R M A T 275cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 276cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_pix_format { 277cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 width; 278cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 height; 279cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pixelformat; 280731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 field; /* enum v4l2_field */ 281cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 bytesperline; /* for padding, zero if unused */ 282cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sizeimage; 283731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 colorspace; /* enum v4l2_colorspace */ 284cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 priv; /* private data, depends on pixelformat */ 285cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 286cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 287cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Pixel format FOURCC depth Description */ 288cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 289cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* RGB formats */ 290cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */ 291cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ 292cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */ 293cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ 294cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ 295cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ 296cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */ 297cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ 298cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ 299cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ 300cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ 301cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 302cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Grey formats */ 303cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ 304cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ 305cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ 306cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ 307cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ 308cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ 309cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 310cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Grey bit-packed formats */ 311cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */ 312cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 313cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Palette formats */ 314cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ 315cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 316731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Chrominance formats */ 317731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_UV8 v4l2_fourcc('U', 'V', '8', ' ') /* 8 UV 4:4 */ 318731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 319cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Luminance+Chrominance formats */ 320cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */ 321cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */ 322cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */ 323cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */ 324cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YVYU v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */ 325cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */ 326cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ 327cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */ 328cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */ 329cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ 330cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ 331cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ 332cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ 333cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ 334cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */ 335cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */ 336cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ 337cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ 338cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ 339cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 340cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* two planes -- one Y, one Cr + Cb interleaved */ 341cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ 342cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ 343cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ 344cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ 345cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ 346cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ 347cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 348cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* two non contiguous planes - one Y, one Cr + Cb interleaved */ 349cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ 350731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ 351cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ 352731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */ 353cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 354cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* three non contiguous planes - Y, Cb, Cr */ 355cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12 YUV420 planar */ 356731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12 YVU420 planar */ 357cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 358cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ 359cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */ 360cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ 361cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGRBG8 v4l2_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ 362cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SRGGB8 v4l2_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ 363cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10 BGBG.. GRGR.. */ 364cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10 GBGB.. RGRG.. */ 365cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10 GRGR.. BGBG.. */ 366cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10 RGRG.. GBGB.. */ 367cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12 BGBG.. GRGR.. */ 368cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12 GBGB.. RGRG.. */ 369cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ 370cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ 371731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan /* 10bit raw bayer a-law compressed to 8 bits */ 372731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8') 373731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8') 374731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8') 375731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8') 376cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* 10bit raw bayer DPCM compressed to 8 bits */ 377731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8') 378731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8') 379cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0') 380731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8') 381cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* 382cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 10bit raw bayer, expanded to 16 bits 383cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb... 384cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 385cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ 386cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 387cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* compressed formats */ 388cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ 389cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */ 390cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */ 391cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */ 392cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ 393cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ 394731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ 395cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ 396cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ 397cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ 398cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 ES */ 399cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_XVID v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid */ 400cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ 401cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ 402cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */ 403cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */ 404731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ 405cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* for HEVC stream */ 406731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') 407cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 408cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Vendor-specific formats */ 409cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ 410cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */ 411cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */ 412cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */ 413cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */ 414cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */ 415cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */ 416cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */ 417cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */ 418cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */ 419cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */ 420cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */ 421cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */ 422cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */ 423cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */ 424cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_SQ905C v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */ 425cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_PJPG v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */ 426cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_OV511 v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */ 427cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_OV518 v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */ 428cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_STV0680 v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */ 429cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_TM6000 v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */ 430cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */ 431cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_KONICA420 v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */ 432cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_PIX_FMT_JPGL v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */ 433731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_SE401 v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */ 434731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */ 435731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') /* Composite stats */ 436731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 437731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') /* AEC stats */ 438731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') /* AF stats */ 439731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') /* AWB stats */ 440731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') /* IHIST stats */ 441731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') /* Column count stats */ 442731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') /* Row count stats */ 443731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') /* Bayer Grid stats */ 444731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') /* Bayer focus stats */ 445731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') /* Bayer hist stats */ 446cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 447cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 448cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * F O R M A T E N U M E R A T I O N 449cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 450cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_fmtdesc { 451cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; /* Format number */ 452731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 453cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 454cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 description[32]; /* Description string */ 455cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pixelformat; /* Format fourcc */ 456cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 457cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 458cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 459cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FMT_FLAG_COMPRESSED 0x0001 460cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FMT_FLAG_EMULATED 0x0002 461cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 462cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#if 1 463cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* Experimental Frame Size and frame rate enumeration */ 464cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 465cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * F R A M E S I Z E E N U M E R A T I O N 466cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 467cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_frmsizetypes { 468cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMSIZE_TYPE_DISCRETE = 1, 469cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, 470cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMSIZE_TYPE_STEPWISE = 3, 471cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 472cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 473cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frmsize_discrete { 474cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 width; /* Frame width [pixel] */ 475cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 height; /* Frame height [pixel] */ 476cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 477cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 478cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frmsize_stepwise { 479cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 min_width; /* Minimum frame width [pixel] */ 480cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 max_width; /* Maximum frame width [pixel] */ 481cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 step_width; /* Frame width step size [pixel] */ 482cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 min_height; /* Minimum frame height [pixel] */ 483cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 max_height; /* Maximum frame height [pixel] */ 484cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 step_height; /* Frame height step size [pixel] */ 485cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 486cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 487cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frmsizeenum { 488cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; /* Frame size number */ 489cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pixel_format; /* Pixel format */ 490cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; /* Frame size type the device supports. */ 491cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 492cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { /* Frame size */ 493cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_frmsize_discrete discrete; 494cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_frmsize_stepwise stepwise; 495cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 496cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 497cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; /* Reserved space for future use */ 498cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 499cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 500cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 501cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * F R A M E R A T E E N U M E R A T I O N 502cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 503cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_frmivaltypes { 504cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMIVAL_TYPE_DISCRETE = 1, 505cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, 506cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_FRMIVAL_TYPE_STEPWISE = 3, 507cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 508cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 509cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frmival_stepwise { 510cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract min; /* Minimum frame interval [s] */ 511cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract max; /* Maximum frame interval [s] */ 512cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract step; /* Frame interval step size [s] */ 513cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 514cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 515cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frmivalenum { 516cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; /* Frame format index */ 517cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pixel_format; /* Pixel format */ 518cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 width; /* Frame width */ 519cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 height; /* Frame height */ 520cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; /* Frame interval type the device supports. */ 521cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 522cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { /* Frame interval */ 523cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract discrete; 524cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_frmival_stepwise stepwise; 525cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 526cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 527cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; /* Reserved space for future use */ 528cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 529cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#endif 530cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 531cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 532cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * T I M E C O D E 533cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 534cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_timecode { 535cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 536cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 537cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 frames; 538cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 seconds; 539cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 minutes; 540cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 hours; 541cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 userbits[4]; 542cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 543cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 544cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Type */ 545cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_TYPE_24FPS 1 546cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_TYPE_25FPS 2 547cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_TYPE_30FPS 3 548cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_TYPE_50FPS 4 549cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_TYPE_60FPS 5 550cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 551cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags */ 552cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ 553cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_FLAG_COLORFRAME 0x0002 554cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_USERBITS_field 0x000C 555cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_USERBITS_USERDEFINED 0x0000 556cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TC_USERBITS_8BITCHARS 0x0008 557cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* The above is based on SMPTE timecodes */ 558cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 559cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_jpegcompression { 560cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj int quality; 561cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 562cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj int APPn; /* Number of APP segment to be written, 563cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * must be 0..15 */ 564cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj int APP_len; /* Length of data in JPEG APPn segment */ 565cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj char APP_data[60]; /* Data in the JPEG APPn segment. */ 566cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 567cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj int COM_len; /* Length of data in JPEG COM segment */ 568cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj char COM_data[60]; /* Data in JPEG COM segment */ 569cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 570cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 jpeg_markers; /* Which markers should go into the JPEG 571cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * output. Unless you exactly know what 572cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * you do, leave them untouched. 573cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Inluding less markers will make the 574cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * resulting code smaller, but there will 575cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * be fewer applications which can read it. 576cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * The presence of the APP and COM marker 577cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * is influenced by APP_len and COM_len 578cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * ONLY, not by this property! */ 579cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 580cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ 581cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ 582cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ 583cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ 584cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will 585cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * allways use APP0 */ 586cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 587cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 588cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 589cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * M E M O R Y - M A P P I N G B U F F E R S 590cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 591cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_requestbuffers { 592cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 count; 593731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 594731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 memory; /* enum v4l2_memory */ 595cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 596cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 597cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 598cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 599cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_plane - plane info for multi-planar buffers 600cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @bytesused: number of bytes occupied by data in the plane (payload) 601cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @length: size of this plane (NOT the payload) in bytes 602cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @mem_offset: when memory in the associated struct v4l2_buffer is 603cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V4L2_MEMORY_MMAP, equals the offset from the start of 604cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * the device memory for this plane (or is a "cookie" that 605cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * should be passed to mmap() called on the video node) 606cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @userptr: when memory is V4L2_MEMORY_USERPTR, a userspace pointer 607cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * pointing to this plane 608731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @fd: when memory is V4L2_MEMORY_DMABUF, a userspace file 609731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * descriptor associated with this plane 610cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @data_offset: offset in the plane to the start of data; usually 0, 611cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * unless there is a header in front of the data 612cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 613cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Multi-planar buffers consist of one or more planes, e.g. an YCbCr buffer 614cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * with two planes can have one plane for Y, and another for interleaved CbCr 615cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * components. Each plane can reside in a separate memory buffer, or even in 616cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * a completely separate memory node (e.g. in embedded devices). 617cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 618cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_plane { 619cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 bytesused; 620cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 length; 621cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 622cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 mem_offset; 623cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj unsigned long userptr; 624731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __s32 fd; 625cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } m; 626cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 data_offset; 627cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[11]; 628cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 629cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 630cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 631cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_buffer - video buffer info 632cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @index: id number of the buffer 633731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for 634731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * multiplanar buffers); 635cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @bytesused: number of bytes occupied by data in the buffer (payload); 636cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * unused (set to 0) for multiplanar buffers 637cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @flags: buffer informational flags 638731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @field: enum v4l2_field; field order of the image in the buffer 639cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @timestamp: frame timestamp 640cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @timecode: frame timecode 641cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @sequence: sequence count of this frame 642731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @memory: enum v4l2_memory; the method, in which the actual video data is 643731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * passed 644cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP; 645cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * offset from the start of the device memory for this plane, 646cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * (or a "cookie" that should be passed to mmap() as offset) 647cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @userptr: for non-multiplanar buffers with memory == V4L2_MEMORY_USERPTR; 648cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * a userspace pointer pointing to this buffer 649731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @fd: for non-multiplanar buffers with memory == V4L2_MEMORY_DMABUF; 650731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * a userspace file descriptor associated with this buffer 651cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @planes: for multiplanar buffers; userspace pointer to the array of plane 652cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * info structs for this buffer 653cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @length: size in bytes of the buffer (NOT its payload) for single-plane 654cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * buffers (when type != *_MPLANE); number of elements in the 655cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * planes array for multi-plane buffers 656cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @input: input number from which the video data has has been captured 657cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 658cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Contains data exchanged by application and driver using one of the Streaming 659cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * I/O methods. 660cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 661cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_buffer { 662cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 663731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; 664cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 bytesused; 665cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 666731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 field; 667cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct timeval timestamp; 668cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_timecode timecode; 669cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sequence; 670cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 671cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* memory location */ 672731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 memory; 673cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 674cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 offset; 675cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj unsigned long userptr; 676cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_plane *planes; 677731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __s32 fd; 678cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } m; 679cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 length; 680731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved2; 681cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved; 682cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 683cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 684cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for 'flags' field */ 685731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ 686731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ 687731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ 688731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ 689731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ 690731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ 691cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Buffer is ready, but the data contained within is corrupted. */ 692731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_ERROR 0x0040 693731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ 694731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_PREPARED 0x0400 /* Buffer is prepared for queuing */ 695cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Cache handling flags */ 696731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_NO_CACHE_INVALIDATE 0x0800 697731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_NO_CACHE_CLEAN 0x1000 698cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Timestamp type */ 699731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_TIMESTAMP_MASK 0xe000 700731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x0000 701731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x2000 702731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x4000 703cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Vendor extensions */ 704731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x10000 705731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x20000 706731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x40000 707731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000 /*Image is a IDR-frame*/ 708731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x100000 709731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_DATA_CORRUPT 0x200000 710731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_DROP_FRAME 0x400000 711731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x800000 712731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_EOS 0x1000000 713731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_TS_DISCONTINUITY 0x2000000 714731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_TS_ERROR 0x4000000 715731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_QCOM_BUF_FLAG_READONLY 0x8000000 716731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x10000000 717731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x20000000 718cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MSM_BUF_FLAG_MBAFF 0x40000000 719cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 720731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** 721731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor 722731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * 723731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @index: id number of the buffer 724731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for 725731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * multiplanar buffers); 726731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @plane: index of the plane to be exported, 0 for single plane queues 727731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @flags: flags for newly created file, currently only O_CLOEXEC is 728731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * supported, refer to manual of open syscall for more details 729731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @fd: file descriptor associated with DMABUF (set by driver) 730731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * 731731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * Contains data used for exporting a video buffer as DMABUF file descriptor. 732731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * The buffer is identified by a 'cookie' returned by VIDIOC_QUERYBUF 733731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * (identical to the cookie used to mmap() the buffer to userspace). All 734731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * reserved fields must be set to zero. The field reserved0 is expected to 735731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * become a structure 'type' allowing an alternative layout of the structure 736731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * content. Therefore this field should not be used for any other extensions. 737731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan */ 738731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_exportbuffer { 739731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 740731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 index; 741731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 plane; 742731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 flags; 743731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __s32 fd; 744731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[11]; 745731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan}; 746731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 747cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 748cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * O V E R L A Y P R E V I E W 749cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 750cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_framebuffer { 751cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; 752cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 753cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* FIXME: in theory we should pass something like PCI device + memory 754cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * region + offset instead of some physical address */ 755cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj void *base; 756cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_pix_format fmt; 757cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 758cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'capability' field. Read only */ 759cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 760cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 761cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 762cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 763cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 764cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 765cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 766cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_CAP_SRC_CHROMAKEY 0x0080 767cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'flags' field. */ 768cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_PRIMARY 0x0001 769cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_OVERLAY 0x0002 770cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 771cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 772cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 773cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 774cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_FBUF_FLAG_SRC_CHROMAKEY 0x0040 775cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 776cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_clip { 777cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect c; 778cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_clip __user *next; 779cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 780cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 781cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_window { 782cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect w; 783731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 field; /* enum v4l2_field */ 784cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 chromakey; 785cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_clip __user *clips; 786cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 clipcount; 787cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj void __user *bitmap; 788cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 global_alpha; 789cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 790cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 791cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 792cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * C A P T U R E P A R A M E T E R S 793cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 794cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_captureparm { 795cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; /* Supported modes */ 796cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capturemode; /* Current mode */ 797731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan struct v4l2_fract timeperframe; /* Time per frame in seconds */ 798cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 extendedmode; /* Driver-specific extensions */ 799cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 readbuffers; /* # of buffers for read */ 800cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 801cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 802cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 803cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for 'capability' and 'capturemode' fields */ 804cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ 805cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ 806cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 /* frame skipping is supported */ 807cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 808cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_qcom_frameskip { 809731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u64 maxframeinterval; 810731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u8 fpsvariance; 811cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 812cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 813cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_outputparm { 814cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; /* Supported modes */ 815cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 outputmode; /* Current mode */ 816cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract timeperframe; /* Time per frame in seconds */ 817cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 extendedmode; /* Driver-specific extensions */ 818cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 writebuffers; /* # of buffers for write */ 819cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 820cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 821cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 822cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 823cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * I N P U T I M A G E C R O P P I N G 824cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 825cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_cropcap { 826731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 827cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect bounds; 828cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect defrect; 829cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract pixelaspect; 830cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 831cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 832cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_crop { 833731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 834cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect c; 835cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 836cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 837cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 838cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_selection - selection info 839cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @type: buffer type (do not use *_MPLANE types) 840731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @target: Selection target, used to choose one of possible rectangles; 841731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * defined in v4l2-common.h; V4L2_SEL_TGT_* . 842731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @flags: constraints flags, defined in v4l2-common.h; V4L2_SEL_FLAG_*. 843cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @r: coordinates of selection window 844cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @reserved: for future use, rounds structure size to 64 bytes, set to zero 845cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 846cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Hardware may use multiple helper windows to process a video stream. 847cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * The structure is used to exchange this selection areas between 848cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * an application and a driver. 849cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 850cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_selection { 851cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 852cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 target; 853cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 854cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_rect r; 855cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[9]; 856cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 857cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 858cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 859cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 860cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * A N A L O G V I D E O S T A N D A R D 861cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 862cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 863cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajtypedef __u64 v4l2_std_id; 864cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 865cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* one bit for each */ 866cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) 867cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) 868cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) 869cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) 870cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) 871cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) 872cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) 873cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) 874cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 875cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) 876cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) 877cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) 878cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) 879cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 880cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) /* BTSC */ 881cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) /* EIA-J */ 882cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_NTSC_443 ((v4l2_std_id)0x00004000) 883cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_NTSC_M_KR ((v4l2_std_id)0x00008000) /* FM A2 */ 884cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 885cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) 886cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) 887cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) 888cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) 889cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) 890cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) 891cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) 892cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_LC ((v4l2_std_id)0x00800000) 893cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 894cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* ATSC/HDTV */ 895cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) 896cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) 897cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 898cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* FIXME: 899cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj Although std_id is 64 bits, there is an issue on PPC32 architecture that 900cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj makes switch(__u64) to break. So, there's a hack on v4l2-common.c rounding 901cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj this value to 32 bits. 902cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj As, currently, the max value is for V4L2_STD_ATSC_16_VSB (30 bits wide), 903cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj it should work fine. However, if needed to add more than two standards, 904cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj v4l2-common.c should be fixed. 905cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 906cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 907cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 908cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Some macros to merge video standards in order to make live easier for the 909cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * drivers and V4L2 applications 910cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 911cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 912cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 913cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * "Common" NTSC/M - It should be noticed that V4L2_STD_NTSC_443 is 914cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Missing here. 915cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 916cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ 917cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_NTSC_M_JP |\ 918cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_NTSC_M_KR) 919cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Secam macros */ 920cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ 921cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_K |\ 922cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_K1) 923cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* All Secam Standards */ 924cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ 925cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_G |\ 926cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_H |\ 927cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_DK |\ 928cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_L |\ 929cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_LC) 930cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* PAL macros */ 931cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ 932cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_B1 |\ 933cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_G) 934cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ 935cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_D1 |\ 936cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_K) 937cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 938cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * "Common" PAL - This macro is there to be compatible with the old 939cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V4L1 concept of "PAL": /BGDKHI. 940cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Several PAL standards are mising here: /M, /N and /Nc 941cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 942cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ 943cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_DK |\ 944cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_H |\ 945cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_I) 946cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Chroma "agnostic" standards */ 947cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_B (V4L2_STD_PAL_B |\ 948cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_B1 |\ 949cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_B) 950cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_G (V4L2_STD_PAL_G |\ 951cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_G) 952cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_H (V4L2_STD_PAL_H |\ 953cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_H) 954cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_L (V4L2_STD_SECAM_L |\ 955cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_LC) 956cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_GH (V4L2_STD_G |\ 957cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_H) 958cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_DK (V4L2_STD_PAL_DK |\ 959cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM_DK) 960cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_BG (V4L2_STD_B |\ 961cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_G) 962cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_MN (V4L2_STD_PAL_M |\ 963cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_N |\ 964cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_Nc |\ 965cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_NTSC) 966cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 967cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Standards where MTS/BTSC stereo could be found */ 968cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_MTS (V4L2_STD_NTSC_M |\ 969cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_M |\ 970cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_N |\ 971cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_Nc) 972cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 973cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Standards for Countries with 60Hz Line frequency */ 974cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ 975cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_60 |\ 976cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_NTSC |\ 977cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_NTSC_443) 978cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Standards for Countries with 50Hz Line frequency */ 979cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_625_50 (V4L2_STD_PAL |\ 980cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_N |\ 981cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_PAL_Nc |\ 982cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_SECAM) 983cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 984cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ 985cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_ATSC_16_VSB) 986cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Macros with none and all analog standards */ 987cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_UNKNOWN 0 988cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_STD_ALL (V4L2_STD_525_60 |\ 989cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_STD_625_50) 990cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 991cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_standard { 992cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 993cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj v4l2_std_id id; 994cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[24]; 995cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_fract frameperiod; /* Frames, not fields */ 996cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 framelines; 997cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 998cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 999cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1000cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1001731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * D V B T T I M I N G S 1002cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1003cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1004731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** struct v4l2_bt_timings - BT.656/BT.1120 timing data 1005731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @width: total width of the active video in pixels 1006731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @height: total height of the active video in lines 1007731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @interlaced: Interlaced or progressive 1008731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @polarities: Positive or negative polarities 1009731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 1010731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @hfrontporch:Horizontal front porch in pixels 1011731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @hsync: Horizontal Sync length in pixels 1012731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @hbackporch: Horizontal back porch in pixels 1013731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @vfrontporch:Vertical front porch in lines 1014731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @vsync: Vertical Sync length in lines 1015731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @vbackporch: Vertical back porch in lines 1016731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @il_vfrontporch:Vertical front porch for the even field 1017731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * (aka field 2) of interlaced field formats 1018731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @il_vsync: Vertical Sync length for the even field 1019731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * (aka field 2) of interlaced field formats 1020731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @il_vbackporch:Vertical back porch for the even field 1021731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * (aka field 2) of interlaced field formats 1022731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @standards: Standards the timing belongs to 1023731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @flags: Flags 1024731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @reserved: Reserved fields, must be zeroed. 1025731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * 1026731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * A note regarding vertical interlaced timings: height refers to the total 1027731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * height of the active video frame (= two fields). The blanking timings refer 1028731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * to the blanking of each field. So the height of the total frame is 1029731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * calculated as follows: 1030731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * 1031731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * tot_height = height + vfrontporch + vsync + vbackporch + 1032731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * il_vfrontporch + il_vsync + il_vbackporch 1033731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * 1034731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * The active height of each field is height / 2. 1035cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1036731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_bt_timings { 1037cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 width; 1038cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 height; 1039731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 interlaced; 1040731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 polarities; 1041731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u64 pixelclock; 1042731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 hfrontporch; 1043731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 hsync; 1044731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 hbackporch; 1045731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 vfrontporch; 1046731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 vsync; 1047731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 vbackporch; 1048731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 il_vfrontporch; 1049731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 il_vsync; 1050731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 il_vbackporch; 1051731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 standards; 1052731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 flags; 1053731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[14]; 1054cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1055cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1056cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Interlaced or progressive format */ 1057cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DV_PROGRESSIVE 0 1058cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DV_INTERLACED 1 1059cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1060cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Polarities. If bit is not set, it is assumed to be negative polarity */ 1061cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DV_VSYNC_POS_POL 0x00000001 1062cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DV_HSYNC_POS_POL 0x00000002 1063cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1064731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Timings standards */ 1065731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_STD_CEA861 (1 << 0) /* CEA-861 Digital TV Profile */ 1066731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_STD_DMT (1 << 1) /* VESA Discrete Monitor Timings */ 1067731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_STD_CVT (1 << 2) /* VESA Coordinated Video Timings */ 1068731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_STD_GTF (1 << 3) /* VESA Generalized Timings Formula */ 1069731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1070731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Flags */ 1071731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1072731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* CVT/GTF specific: timing uses reduced blanking (CVT) or the 'Secondary 1073731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan GTF' curve (GTF). In both cases the horizontal and/or vertical blanking 1074731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan intervals are reduced, allowing a higher resolution over the same 1075731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan bandwidth. This is a read-only flag. */ 1076731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0) 1077731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* CEA-861 specific: set for CEA-861 formats with a framerate of a multiple 1078731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan of six. These formats can be optionally played at 1 / 1.001 speed. 1079731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan This is a read-only flag. */ 1080731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1) 1081731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* CEA-861 specific: only valid for video transmitters, the flag is cleared 1082731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan by receivers. 1083731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan If the framerate of the format is a multiple of six, then the pixelclock 1084731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan used to set up the transmitter is divided by 1.001 to make it compatible 1085731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan with 60 Hz based standards such as NTSC and PAL-M that use a framerate of 1086731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 29.97 Hz. Otherwise this flag is cleared. If the transmitter can't generate 1087731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan such frequencies, then the flag will also be cleared. */ 1088731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_FL_REDUCED_FPS (1 << 2) 1089731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Specific to interlaced formats: if set, then field 1 is really one half-line 1090731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan longer and field 2 is really one half-line shorter, so each field has 1091731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan exactly the same number of half-lines. Whether half-lines can be detected 1092731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan or used depends on the hardware. */ 1093731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_FL_HALF_LINE (1 << 3) 1094731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1095731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1096731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** struct v4l2_dv_timings - DV timings 1097731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @type: the type of the timings 1098731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @bt: BT656/1120 timings 1099731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan */ 1100cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_dv_timings { 1101cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 1102cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1103cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_bt_timings bt; 1104cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[32]; 1105cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1106cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1107cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1108cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Values for the type field */ 1109cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ 1110cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1111731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1112731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** struct v4l2_enum_dv_timings - DV timings enumeration 1113731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @index: enumeration index 1114731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @reserved: must be zeroed 1115731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @timings: the timings for the given index 1116731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan */ 1117731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_enum_dv_timings { 1118731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 index; 1119731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[3]; 1120731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan struct v4l2_dv_timings timings; 1121731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan}; 1122731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1123731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** struct v4l2_bt_timings_cap - BT.656/BT.1120 timing capabilities 1124731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @min_width: width in pixels 1125731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @max_width: width in pixels 1126731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @min_height: height in lines 1127731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @max_height: height in lines 1128731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @min_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 1129731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @max_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 1130731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @standards: Supported standards 1131731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @capabilities: Supported capabilities 1132731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @reserved: Must be zeroed 1133731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan */ 1134731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_bt_timings_cap { 1135731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 min_width; 1136731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 max_width; 1137731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 min_height; 1138731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 max_height; 1139731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u64 min_pixelclock; 1140731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u64 max_pixelclock; 1141731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 standards; 1142731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 capabilities; 1143731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[16]; 1144731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan} __attribute__ ((packed)); 1145731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1146731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Supports interlaced formats */ 1147731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_CAP_INTERLACED (1 << 0) 1148731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Supports progressive formats */ 1149731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1) 1150731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Supports CVT/GTF reduced blanking */ 1151731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2) 1152731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Supports custom formats */ 1153731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_DV_BT_CAP_CUSTOM (1 << 3) 1154731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1155731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/** struct v4l2_dv_timings_cap - DV timings capabilities 1156731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @type: the type of the timings (same as in struct v4l2_dv_timings) 1157731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @bt: the BT656/1120 timings capabilities 1158731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan */ 1159731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_dv_timings_cap { 1160731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; 1161731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[3]; 1162731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan union { 1163731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan struct v4l2_bt_timings_cap bt; 1164731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 raw_data[32]; 1165731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan }; 1166731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan}; 1167731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1168731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1169cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1170cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V I D E O I N P U T S 1171cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1172cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_input { 1173cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; /* Which input */ 1174cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; /* Label */ 1175cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; /* Type of input */ 1176cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 audioset; /* Associated audios (bitfield) */ 1177731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 tuner; /* enum v4l2_tuner_type */ 1178cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj v4l2_std_id std; 1179cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 status; 1180cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capabilities; 1181cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[3]; 1182cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1183cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1184cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Values for the 'type' field */ 1185cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_INPUT_TYPE_TUNER 1 1186cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_INPUT_TYPE_CAMERA 2 1187cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1188cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* field 'status' - general */ 1189cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ 1190cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_SIGNAL 0x00000002 1191cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_COLOR 0x00000004 1192cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1193cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* field 'status' - sensor orientation */ 1194cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* If sensor is mounted upside down set both bits */ 1195cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_HFLIP 0x00000010 /* Frames are flipped horizontally */ 1196cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_VFLIP 0x00000020 /* Frames are flipped vertically */ 1197cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1198cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* field 'status' - analog */ 1199cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ 1200cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ 1201cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1202cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* field 'status' - digital */ 1203cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ 1204cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ 1205cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ 1206cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1207cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* field 'status' - VCR and set-top box */ 1208cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ 1209cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ 1210cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ 1211cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1212cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* capabilities flags */ 1213731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_IN_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ 1214731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_IN_CAP_CUSTOM_TIMINGS V4L2_IN_CAP_DV_TIMINGS /* For compatibility */ 1215cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ 1216cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1217cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1218cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V I D E O O U T P U T S 1219cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1220cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_output { 1221cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; /* Which output */ 1222cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; /* Label */ 1223cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; /* Type of output */ 1224cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 audioset; /* Associated audios (bitfield) */ 1225cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 modulator; /* Associated modulator */ 1226cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj v4l2_std_id std; 1227cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capabilities; 1228cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[3]; 1229cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1230cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Values for the 'type' field */ 1231cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_OUTPUT_TYPE_MODULATOR 1 1232cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_OUTPUT_TYPE_ANALOG 2 1233cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 1234cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1235cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* capabilities flags */ 1236731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_OUT_CAP_DV_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ 1237731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_OUT_CAP_CUSTOM_TIMINGS V4L2_OUT_CAP_DV_TIMINGS /* For compatibility */ 1238cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ 1239cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1240cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1241cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * C O N T R O L S 1242cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1243cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_control { 1244cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1245cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 value; 1246cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1247cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1248cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_ext_control { 1249cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1250cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 size; 1251cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved2[1]; 1252cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1253cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 value; 1254cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s64 value64; 1255cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj char *string; 1256cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1257cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1258cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1259cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_ext_controls { 1260cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 ctrl_class; 1261cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 count; 1262cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 error_idx; 1263cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 1264cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_ext_control *controls; 1265cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1266cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1267cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_ID_MASK (0x0fffffff) 1268cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) 1269cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) 1270cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1271cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajenum v4l2_ctrl_type { 1272cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_INTEGER = 1, 1273cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_BOOLEAN = 2, 1274cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_MENU = 3, 1275cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_BUTTON = 4, 1276cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_INTEGER64 = 5, 1277cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_CTRL_CLASS = 6, 1278cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_STRING = 7, 1279cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj V4L2_CTRL_TYPE_BITMASK = 8, 1280731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan V4L2_CTRL_TYPE_INTEGER_MENU = 9, 1281cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1282cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1283cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ 1284cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_queryctrl { 1285cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1286731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_ctrl_type */ 1287cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; /* Whatever */ 1288cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 minimum; /* Note signedness */ 1289cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 maximum; 1290cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 step; 1291cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 default_value; 1292cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1293cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 1294cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1295cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1296cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ 1297cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_querymenu { 1298cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1299cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1300731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan union { 1301731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u8 name[32]; /* Whatever */ 1302731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __s64 value; 1303731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan }; 1304cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved; 1305731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan} __attribute__ ((packed)); 1306cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1307cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Control flags */ 1308cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_DISABLED 0x0001 1309cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_GRABBED 0x0002 1310cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_READ_ONLY 0x0004 1311cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_UPDATE 0x0008 1312cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_INACTIVE 0x0010 1313cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_SLIDER 0x0020 1314cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_WRITE_ONLY 0x0040 1315cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_VOLATILE 0x0080 1316cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1317cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Query flag, to be ORed with the control ID */ 1318cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 1319cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1320cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* User-class control IDs defined by V4L2 */ 1321cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CID_MAX_CTRLS 1024 1322cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* IDs reserved for driver specific controls */ 1323cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_CID_PRIVATE_BASE 0x08000000 1324cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1325cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1326cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1327cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * T U N I N G 1328cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1329cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_tuner { 1330cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1331cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; 1332731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_tuner_type */ 1333cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; 1334cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 rangelow; 1335cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 rangehigh; 1336cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 rxsubchans; 1337cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 audmode; 1338cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 signal; 1339cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 afc; 1340cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 1341cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1342cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1343cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_modulator { 1344cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1345cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; 1346cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; 1347cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 rangelow; 1348cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 rangehigh; 1349cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 txsubchans; 1350cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 1351cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1352cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1353cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'capability' field */ 1354cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_LOW 0x0001 1355cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_NORM 0x0002 1356731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_TUNER_CAP_HWSEEK_BOUNDED 0x0004 1357731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_TUNER_CAP_HWSEEK_WRAP 0x0008 1358cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_STEREO 0x0010 1359cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_LANG2 0x0020 1360cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_SAP 0x0020 1361cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_LANG1 0x0040 1362cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_RDS 0x0080 1363cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_RDS_BLOCK_IO 0x0100 1364cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_CAP_RDS_CONTROLS 0x0200 1365731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_TUNER_CAP_FREQ_BANDS 0x0400 1366731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_TUNER_CAP_HWSEEK_PROG_LIM 0x0800 1367cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1368cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'rxsubchans' field */ 1369cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_MONO 0x0001 1370cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_STEREO 0x0002 1371cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_LANG2 0x0004 1372cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_SAP 0x0004 1373cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_LANG1 0x0008 1374cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_SUB_RDS 0x0010 1375cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1376cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Values for the 'audmode' field */ 1377cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_MONO 0x0000 1378cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_STEREO 0x0001 1379cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_LANG2 0x0002 1380cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_SAP 0x0002 1381cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_LANG1 0x0003 1382cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 1383cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1384cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_frequency { 1385731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 tuner; 1386731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_tuner_type */ 1387731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 frequency; 1388731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[8]; 1389731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan}; 1390731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1391731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BAND_MODULATION_VSB (1 << 1) 1392731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BAND_MODULATION_FM (1 << 2) 1393731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_BAND_MODULATION_AM (1 << 3) 1394731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1395731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_frequency_band { 1396731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 tuner; 1397731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_tuner_type */ 1398731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 index; 1399731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 capability; 1400731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 rangelow; 1401731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 rangehigh; 1402731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 modulation; 1403731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[9]; 1404cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1405cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1406cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_hw_freq_seek { 1407731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 tuner; 1408731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_tuner_type */ 1409731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 seek_upward; 1410731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 wrap_around; 1411731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 spacing; 1412731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 rangelow; 1413731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 rangehigh; 1414731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[5]; 1415cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1416cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1417cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1418cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * R D S 1419cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1420cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1421cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_rds_data { 1422cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 lsb; 1423cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 msb; 1424cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 block; 1425cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1426cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1427cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_MSK 0x7 1428cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_A 0 1429cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_B 1 1430cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_C 2 1431cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_D 3 1432cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_C_ALT 4 1433cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_INVALID 7 1434cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1435cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_CORRECTED 0x40 1436cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_RDS_BLOCK_ERROR 0x80 1437cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1438cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1439cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * A U D I O 1440cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1441cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_audio { 1442cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1443cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; 1444cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; 1445cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 mode; 1446cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 1447cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1448cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1449cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'capability' field */ 1450cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_AUDCAP_STEREO 0x00001 1451cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_AUDCAP_AVL 0x00002 1452cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1453cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for the 'mode' field */ 1454cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_AUDMODE_AVL 0x00001 1455cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1456cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_audioout { 1457cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1458cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 name[32]; 1459cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 capability; 1460cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 mode; 1461cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 1462cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1463cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1464cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1465cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * M P E G S E R V I C E S 1466cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1467cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * NOTE: EXPERIMENTAL API 1468cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1469cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#if 1 1470cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_IDX_FRAME_I (0) 1471cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_IDX_FRAME_P (1) 1472cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_IDX_FRAME_B (2) 1473cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_IDX_FRAME_MASK (0xf) 1474cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1475cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_enc_idx_entry { 1476cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u64 offset; 1477cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u64 pts; 1478cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 length; 1479cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1480cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; 1481cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1482cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1483cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_IDX_ENTRIES (64) 1484cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_enc_idx { 1485cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 entries; 1486cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 entries_cap; 1487cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[4]; 1488cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_enc_idx_entry entry[V4L2_ENC_IDX_ENTRIES]; 1489cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1490cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1491cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1492cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_CMD_START (0) 1493cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_CMD_STOP (1) 1494cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_CMD_PAUSE (2) 1495cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_CMD_RESUME (3) 1496cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_QCOM_CMD_FLUSH (4) 1497cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1498cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for V4L2_ENC_CMD_STOP */ 1499cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) 1500cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1501cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_encoder_cmd { 1502cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 cmd; 1503cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1504cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1505cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct { 1506cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 data[8]; 1507cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } raw; 1508cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1509cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1510cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1511cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Decoder commands */ 1512cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_START (0) 1513cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_STOP (1) 1514cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_PAUSE (2) 1515cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_RESUME (3) 1516cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_QCOM_CMD_FLUSH (4) 1517cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1518cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for V4L2_DEC_CMD_START */ 1519cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) 1520cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1521cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for V4L2_DEC_CMD_PAUSE */ 1522cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_PAUSE_TO_BLACK (1 << 0) 1523cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1524cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for V4L2_DEC_CMD_STOP */ 1525cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) 1526cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) 1527cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1528cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Flags for V4L2_DEC_QCOM_CMD_FLUSH */ 1529cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) 1530cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) 1531cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1532cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) 1533cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) 1534cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1535cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Play format requirements (returned by the driver): */ 1536cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1537cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* The decoder has no special format requirements */ 1538cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_START_FMT_NONE (0) 1539cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* The decoder requires full GOPs */ 1540cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_DEC_START_FMT_GOP (1) 1541cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1542cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* The structure must be zeroed before use by the application 1543cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj This ensures it can be extended safely in the future. */ 1544cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_decoder_cmd { 1545cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 cmd; 1546cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1547cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1548cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct { 1549cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u64 pts; 1550cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } stop; 1551cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1552cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct { 1553cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* 0 or 1000 specifies normal speed, 1554cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1 specifies forward single stepping, 1555cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj -1 specifies backward single stepping, 1556cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj >1: playback at speed/1000 of the normal speed, 1557cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj <-1: reverse playback at (-speed/1000) of the normal speed. */ 1558cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 speed; 1559cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 format; 1560cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } start; 1561cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1562cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct { 1563cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 data[16]; 1564cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } raw; 1565cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1566cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1567cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#endif 1568cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1569cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1570cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1571cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * D A T A S E R V I C E S ( V B I ) 1572cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1573cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Data services API by Michael Schimek 1574cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1575cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1576cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Raw VBI */ 1577cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_vbi_format { 1578cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sampling_rate; /* in 1 Hz */ 1579cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 offset; 1580cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 samples_per_line; 1581cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sample_format; /* V4L2_PIX_FMT_* */ 1582cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 start[2]; 1583cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 count[2]; 1584cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; /* V4L2_VBI_* */ 1585cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; /* must be zero */ 1586cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1587cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1588cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* VBI flags */ 1589cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_VBI_UNSYNC (1 << 0) 1590cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_VBI_INTERLACED (1 << 1) 1591cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1592cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Sliced VBI 1593cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1594cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * This implements is a proposal V4L2 API to allow SLICED VBI 1595cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * required for some hardware encoders. It should change without 1596cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * notice in the definitive implementation. 1597cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1598cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1599cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_sliced_vbi_format { 1600cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 service_set; 1601cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field 1602cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field 1603cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (equals frame lines 313-336 for 625 line video 1604cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj standards, 263-286 for 525 line standards) */ 1605cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 service_lines[2][24]; 1606cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 io_size; 1607cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[2]; /* must be zero */ 1608cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1609cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1610cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Teletext World System Teletext 1611cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (WST), defined on ITU-R BT.653-2 */ 1612cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_TELETEXT_B (0x0001) 1613cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Video Program System, defined on ETS 300 231*/ 1614cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_VPS (0x0400) 1615cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Closed Caption, defined on EIA-608 */ 1616cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_CAPTION_525 (0x1000) 1617cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Wide Screen System, defined on ITU-R BT1119.1 */ 1618cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_WSS_625 (0x4000) 1619cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1620cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) 1621cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) 1622cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1623cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_sliced_vbi_cap { 1624cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 service_set; 1625cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field 1626cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field 1627cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (equals frame lines 313-336 for 625 line video 1628cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj standards, 263-286 for 525 line standards) */ 1629cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 service_lines[2][24]; 1630731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 1631cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[3]; /* must be 0 */ 1632cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1633cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1634cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_sliced_vbi_data { 1635cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1636cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 field; /* 0: first field, 1: second field */ 1637cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 line; /* 1-23 */ 1638cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved; /* must be 0 */ 1639cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 data[48]; 1640cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1641cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1642cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1643cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Sliced VBI data inserted into MPEG Streams 1644cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1645cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1646cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1647cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * V4L2_MPEG_STREAM_VBI_FMT_IVTV: 1648cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1649cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Structure of payload contained in an MPEG 2 Private Stream 1 PES Packet in an 1650cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * MPEG-2 Program Pack that contains V4L2_MPEG_STREAM_VBI_FMT_IVTV Sliced VBI 1651cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * data 1652cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1653cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * Note, the MPEG-2 Program Pack and Private Stream 1 PES packet header 1654cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * definitions are not included here. See the MPEG-2 specifications for details 1655cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * on these headers. 1656cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1657cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1658cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Line type IDs */ 1659cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_TELETEXT_B (1) 1660cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_CAPTION_525 (4) 1661cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_WSS_625 (5) 1662cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_VPS (7) 1663cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1664cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_mpeg_vbi_itv0_line { 1665cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 id; /* One of V4L2_MPEG_VBI_IVTV_* above */ 1666cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 data[42]; /* Sliced VBI data for the line */ 1667cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1668cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1669cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_mpeg_vbi_itv0 { 1670cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __le32 linemask[2]; /* Bitmasks of VBI service lines present */ 1671cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_mpeg_vbi_itv0_line line[35]; 1672cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1673cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1674cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_mpeg_vbi_ITV0 { 1675cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_mpeg_vbi_itv0_line line[36]; 1676cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1677cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1678cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_MAGIC0 "itv0" 1679cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_MPEG_VBI_IVTV_MAGIC1 "ITV0" 1680cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1681cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_mpeg_vbi_fmt_ivtv { 1682cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 magic[4]; 1683cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1684cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_mpeg_vbi_itv0 itv0; 1685cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_mpeg_vbi_ITV0 ITV0; 1686cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1687cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1688cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1689cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1690cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * A G G R E G A T E S T R U C T U R E S 1691cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1692cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1693cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 1694cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_plane_pix_format - additional, per-plane format definition 1695cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @sizeimage: maximum size in bytes required for data, for which 1696cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * this plane will be used 1697cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @bytesperline: distance in bytes between the leftmost pixels in two 1698cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * adjacent lines 1699cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1700cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_plane_pix_format { 1701cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sizeimage; 1702cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 bytesperline; 1703cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u16 reserved[7]; 1704cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1705cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1706cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 1707cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_pix_format_mplane - multiplanar format definition 1708cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @width: image width in pixels 1709cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @height: image height in pixels 1710cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @pixelformat: little endian four character code (fourcc) 1711731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @field: enum v4l2_field; field order (for interlaced video) 1712731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @colorspace: enum v4l2_colorspace; supplemental to pixelformat 1713cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @plane_fmt: per-plane information 1714cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @num_planes: number of planes for this format 1715cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1716cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_pix_format_mplane { 1717cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 width; 1718cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 height; 1719cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pixelformat; 1720731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 field; 1721731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 colorspace; 1722cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1723cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES]; 1724cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 num_planes; 1725cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 reserved[11]; 1726cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1727cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1728cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 1729cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_format - stream data format 1730731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @type: enum v4l2_buf_type; type of the data stream 1731cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @pix: definition of an image format 1732cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @pix_mp: definition of a multiplanar image format 1733cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @win: definition of an overlaid image 1734cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @vbi: raw VBI capture or output parameters 1735cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @sliced: sliced VBI capture or output parameters 1736cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @raw_data: placeholder for future extensions and custom formats 1737cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1738cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_format { 1739731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; 1740cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1741cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ 1742cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */ 1743cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ 1744cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ 1745cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ 1746cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 raw_data[200]; /* user-defined */ 1747cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } fmt; 1748cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1749cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1750cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Stream type-dependent parameters 1751cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1752cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_streamparm { 1753731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 type; /* enum v4l2_buf_type */ 1754cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1755cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_captureparm capture; 1756cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_outputparm output; 1757cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 raw_data[200]; /* user-defined */ 1758cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } parm; 1759cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1760cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1761cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1762cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * E V E N T S 1763cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1764cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1765cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_ALL 0 1766cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_VSYNC 1 1767cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_EOS 2 1768cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_CTRL 3 1769cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_FRAME_SYNC 4 1770cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_PRIVATE_START 0x08000000 1771cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1772cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) 1773cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) 1774cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \ 1775cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (V4L2_EVENT_MSM_VIDC_START + 2) 1776cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \ 1777cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (V4L2_EVENT_MSM_VIDC_START + 3) 1778cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_CLOSE_DONE (V4L2_EVENT_MSM_VIDC_START + 4) 1779cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) 1780cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \ 1781cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (V4L2_EVENT_MSM_VIDC_START + 6) 1782cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \ 1783cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj (V4L2_EVENT_MSM_VIDC_START + 7) 1784731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) 1785731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) 17865564ba432eb2de9df9d17174ef9c38b5786bc2b4Vineeta Srivastava#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) 1787cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1788cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Payload for V4L2_EVENT_VSYNC */ 1789cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_event_vsync { 1790cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj /* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */ 1791cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 field; 1792cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1793cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1794cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Payload for V4L2_EVENT_CTRL */ 1795cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_CTRL_CH_VALUE (1 << 0) 1796cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_CTRL_CH_FLAGS (1 << 1) 1797731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_EVENT_CTRL_CH_RANGE (1 << 2) 1798cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1799cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_event_ctrl { 1800cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 changes; 1801cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 1802cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1803cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 value; 1804cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s64 value64; 1805cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1806cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1807cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 minimum; 1808cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 maximum; 1809cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 step; 1810cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __s32 default_value; 1811cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1812cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1813cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_event_frame_sync { 1814cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 frame_sequence; 1815cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1816cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1817cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_event { 1818cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 1819cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { 1820cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_event_vsync vsync; 1821cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_event_ctrl ctrl; 1822cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_event_frame_sync frame_sync; 1823cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u8 data[64]; 1824cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj } u; 1825cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 pending; 1826cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 sequence; 1827cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct timespec timestamp; 1828cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1829cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[8]; 1830cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1831cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1832cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_SUB_FL_SEND_INITIAL (1 << 0) 1833cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK (1 << 1) 1834cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1835cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_event_subscription { 1836cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; 1837cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 id; 1838cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 flags; 1839cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[5]; 1840cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1841cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1842cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1843cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * A D V A N C E D D E B U G G I N G 1844cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1845cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * NOTE: EXPERIMENTAL API, NEVER RELY ON THIS IN APPLICATIONS! 1846cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * FOR DEBUGGING, TESTING AND INTERNAL USE ONLY! 1847cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1848cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1849cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ 1850cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1851731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_BRIDGE 0 /* Match against chip ID on the bridge (0 for the bridge) */ 1852731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE 1853731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ 1854731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ 1855731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_AC97 3 /* Match against anciliary AC97 chip */ 1856731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */ 1857cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1858cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_dbg_match { 1859cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 type; /* Match type */ 1860cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj union { /* Match this chip, meaning determined by type */ 1861cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 addr; 1862cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj char name[32]; 1863cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj }; 1864cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1865cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1866cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_dbg_register { 1867cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_dbg_match match; 1868cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 size; /* register size in bytes */ 1869cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u64 reg; 1870cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u64 val; 1871cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1872cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1873cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* VIDIOC_DBG_G_CHIP_IDENT */ 1874cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_dbg_chip_ident { 1875cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_dbg_match match; 1876cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */ 1877cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 revision; /* chip revision, chip specific */ 1878cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj} __attribute__ ((packed)); 1879cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1880731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_FL_READABLE (1 << 0) 1881731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define V4L2_CHIP_FL_WRITABLE (1 << 1) 1882731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1883731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* VIDIOC_DBG_G_CHIP_INFO */ 1884731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavanstruct v4l2_dbg_chip_info { 1885731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan struct v4l2_dbg_match match; 1886731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan char name[32]; 1887731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 flags; 1888731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 reserved[32]; 1889731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan} __attribute__ ((packed)); 1890731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1891cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/** 1892cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * struct v4l2_create_buffers - VIDIOC_CREATE_BUFS argument 1893cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @index: on return, index of the first created buffer 1894cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @count: entry: number of requested buffers, 1895cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * return: number of created buffers 1896731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan * @memory: enum v4l2_memory; buffer memory type 1897cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @format: frame format, for which buffers are requested 1898cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * @reserved: future extensions 1899cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1900cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramarajstruct v4l2_create_buffers { 1901cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 index; 1902cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 count; 1903731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan __u32 memory; 1904cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj struct v4l2_format format; 1905cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj __u32 reserved[8]; 1906cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj}; 1907cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1908cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* 1909cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * I O C T L C O D E S F O R V I D E O D E V I C E S 1910cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj * 1911cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj */ 1912cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability) 1913cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_RESERVED _IO('V', 1) 1914cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc) 1915cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format) 1916cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format) 1917cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers) 1918cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer) 1919cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer) 1920cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer) 1921cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_OVERLAY _IOW('V', 14, int) 1922cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer) 1923731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_EXPBUF _IOWR('V', 16, struct v4l2_exportbuffer) 1924cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer) 1925cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_STREAMON _IOW('V', 18, int) 1926cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_STREAMOFF _IOW('V', 19, int) 1927cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm) 1928cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm) 1929cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id) 1930cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id) 1931cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard) 1932cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input) 1933cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control) 1934cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control) 1935cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner) 1936cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner) 1937cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio) 1938cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio) 1939cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl) 1940cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu) 1941cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_INPUT _IOR('V', 38, int) 1942cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_INPUT _IOWR('V', 39, int) 1943cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_OUTPUT _IOR('V', 46, int) 1944cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_OUTPUT _IOWR('V', 47, int) 1945cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output) 1946cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout) 1947cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout) 1948cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator) 1949cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator) 1950cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency) 1951cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency) 1952cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap) 1953cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop) 1954cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop) 1955cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression) 1956cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression) 1957cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id) 1958cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format) 1959cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio) 1960cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout) 1961731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) /* enum v4l2_priority */ 1962731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) /* enum v4l2_priority */ 1963cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap) 1964cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_LOG_STATUS _IO('V', 70) 1965cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls) 1966cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls) 1967cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls) 1968cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum) 1969cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum) 1970cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx) 1971cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd) 1972cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd) 1973cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1974cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Experimental, meant for debugging, testing and internal use. 1975cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj Only implemented if CONFIG_VIDEO_ADV_DEBUG is defined. 1976cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj You must be root to use these ioctls. Never use these in applications! */ 1977cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) 1978cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) 1979cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1980cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Experimental, meant for debugging, testing and internal use. 1981731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan Never use this ioctl in applications! 1982731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan Note: this ioctl is deprecated in favor of VIDIOC_DBG_G_CHIP_INFO and 1983731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan will go away in the future. */ 1984cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) 1985cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1986cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) 1987731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 1988cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) 1989cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) 1990cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DQEVENT _IOR('V', 89, struct v4l2_event) 1991cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_SUBSCRIBE_EVENT _IOW('V', 90, struct v4l2_event_subscription) 1992cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_UNSUBSCRIBE_EVENT _IOW('V', 91, struct v4l2_event_subscription) 1993cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1994cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Experimental, the below two ioctls may change over the next couple of kernel 1995cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj versions */ 1996cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_CREATE_BUFS _IOWR('V', 92, struct v4l2_create_buffers) 1997cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_PREPARE_BUF _IOWR('V', 93, struct v4l2_buffer) 1998cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 1999cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Experimental selection API */ 2000cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_G_SELECTION _IOWR('V', 94, struct v4l2_selection) 2001cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_S_SELECTION _IOWR('V', 95, struct v4l2_selection) 2002cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 2003cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Experimental, these two ioctls may change over the next couple of kernel 2004cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj versions. */ 2005cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd) 2006cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd) 2007cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 2008731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Experimental, these three ioctls may change over the next couple of kernel 2009731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan versions. */ 2010731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) 2011731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) 2012731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) 2013731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 2014731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Experimental, this ioctl may change over the next couple of kernel 2015731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan versions. */ 2016731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_ENUM_FREQ_BANDS _IOWR('V', 101, struct v4l2_frequency_band) 2017731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 2018731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan/* Experimental, meant for debugging, testing and internal use. 2019731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan Never use these in applications! */ 2020731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) 2021731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan 2022cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj/* Reminder: when adding new ioctls please add support for them to 2023cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj drivers/media/video/v4l2-compat-ioctl32.c as well! */ 2024cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 2025cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ 2026cd369140fd7fbed4ea06e15beb5ec45cbbfdd0ffNaveen Ramaraj 2027731075f3fd4c9fd79fa2b70f29f8f24acc5ae9b7Praveen Chavan#endif /* _UAPI__LINUX_VIDEODEV2_H */ 2028