Cross Reference: /art/compiler/utils/arm/assembler_arm32

Lines Matching refs:shift
40 // To speed up tests, don't use all shift immediates.
173     // ShifterOperands of form "reg shift-type imm."
174     for (arm::Shift shift : shifts) {
179         if (shift != arm::Shift::RRX) {
182               shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, imm));
185             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 1));
186             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 2));
187             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 3));
188             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 7));
189             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 15));
190             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 16));
191             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 30));
192             shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 31));
196           shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 0));
208     for (arm::Shift shift : kShifts) {
211         res.push_back(arm::ShifterOperand(*reg, shift, shift_min));
213           res.push_back(arm::ShifterOperand(*reg, shift, shift_max));
215           res.push_back(arm::ShifterOperand(*reg, shift, middle));
216           res.push_back(arm::ShifterOperand(*reg, shift, middle - 1));
217           res.push_back(arm::ShifterOperand(*reg, shift, middle + 1));
356     for (const arm::ShifterOperand& shift : GetShiftOperands()) {
360       std::string shift_string = GetShiftString(shift);
373       ExecuteAndPrint([&] () { f(shift); }, after_shift, oss);
458     for (const arm::ShifterOperand& shift : GetShiftOperands()) {
462       std::string shift_string = GetShiftString(shift);
475       auto lambda = [&] (Args... args) { f(shift, args...); };  // NOLINT [readability/braces] [4]
724   T5Helper(&arm::Arm32Assembler::and_, true, "and{cond}{s} {reg1}, {reg2}, {shift}", "and");
728   T4Helper(&arm::Arm32Assembler::ands, true, "and{cond}s {reg1}, {reg2}, {shift}", "ands");
732   T5Helper(&arm::Arm32Assembler::eor, true, "eor{cond}{s} {reg1}, {reg2}, {shift}", "eor");
736   T4Helper(&arm::Arm32Assembler::eors, true, "eor{cond}s {reg1}, {reg2}, {shift}", "eors");
740   T5Helper(&arm::Arm32Assembler::orr, true, "orr{cond}{s} {reg1}, {reg2}, {shift}", "orr");
744   T4Helper(&arm::Arm32Assembler::orrs, true, "orr{cond}s {reg1}, {reg2}, {shift}", "orrs");
748   T5Helper(&arm::Arm32Assembler::bic, true, "bic{cond}{s} {reg1}, {reg2}, {shift}", "bic");
752   T4Helper(&arm::Arm32Assembler::bics, true, "bic{cond}s {reg1}, {reg2}, {shift}", "bics");
756   T4Helper(&arm::Arm32Assembler::mov, true, "mov{cond}{s} {reg1}, {shift}", "mov");
760   T3Helper(&arm::Arm32Assembler::movs, true, "mov{cond}s {reg1}, {shift}", "movs");
764   T4Helper(&arm::Arm32Assembler::mvn, true, "mvn{cond}{s} {reg1}, {shift}", "mvn");
768   T3Helper(&arm::Arm32Assembler::mvns, true, "mvn{cond}s {reg1}, {shift}", "mvns");
772   T5Helper(&arm::Arm32Assembler::add, false, "add{cond}{s} {reg1}, {reg2}, {shift}", "add");
776   T4Helper(&arm::Arm32Assembler::adds, false, "add{cond}s {reg1}, {reg2}, {shift}", "adds");
780   T5Helper(&arm::Arm32Assembler::adc, false, "adc{cond}{s} {reg1}, {reg2}, {shift}", "adc");
784   T4Helper(&arm::Arm32Assembler::adcs, false, "adc{cond}s {reg1}, {reg2}, {shift}", "adcs");
788   T5Helper(&arm::Arm32Assembler::sub, false, "sub{cond}{s} {reg1}, {reg2}, {shift}", "sub");
792   T4Helper(&arm::Arm32Assembler::subs, false, "sub{cond}s {reg1}, {reg2}, {shift}", "subs");
796   T5Helper(&arm::Arm32Assembler::sbc, false, "sbc{cond}{s} {reg1}, {reg2}, {shift}", "sbc");
800   T4Helper(&arm::Arm32Assembler::sbcs, false, "sbc{cond}s {reg1}, {reg2}, {shift}", "sbcs");
804   T5Helper(&arm::Arm32Assembler::rsb, true, "rsb{cond}{s} {reg1}, {reg2}, {shift}", "rsb");
808   T4Helper(&arm::Arm32Assembler::rsbs, true, "rsb{cond}s {reg1}, {reg2}, {shift}", "rsbs");
812   T5Helper(&arm::Arm32Assembler::rsc, true, "rsc{cond}{s} {reg1}, {reg2}, {shift}", "rsc");
816   T4Helper(&arm::Arm32Assembler::rscs, false, "rsc{cond}s {reg1}, {reg2}, {shift}", "rscs");
831   T3Helper(&arm::Arm32Assembler::tst, true, "tst{cond} {reg1}, {shift}", "tst");
835   T3Helper(&arm::Arm32Assembler::teq, true, "teq{cond} {reg1}, {shift}", "teq");
839   T3Helper(&arm::Arm32Assembler::cmp, true, "cmp{cond} {reg1}, {shift}", "cmp");
843   T3Helper(&arm::Arm32Assembler::cmn, true, "cmn{cond} {reg1}, {shift}", "cmn");