Cross Reference: /art/compiler/utils/arm64/assembler

Lines Matching refs:offset
59 void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) {
60   StoreToOffset(TR, SP, offset.Int32Value());
98                                     XRegister base, int32_t offset) {
101       ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset));
104       ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset));
107       ___ Str(reg_w(source), MEM_OP(reg_x(base), offset));
114 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) {
116   ___ Str(reg_x(source), MEM_OP(reg_x(base), offset));
119 void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) {
120   ___ Str(reg_s(source), MEM_OP(reg_x(base), offset));
123 void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_t offset) {
124   ___ Str(reg_d(source), MEM_OP(reg_x(base), offset));
221                                      XRegister base, int32_t offset) {
224       ___ Ldrsb(reg_w(dest), MEM_OP(reg_x(base), offset));
227       ___ Ldrsh(reg_w(dest), MEM_OP(reg_x(base), offset));
230       ___ Ldrb(reg_w(dest), MEM_OP(reg_x(base), offset));
233       ___ Ldrh(reg_w(dest), MEM_OP(reg_x(base), offset));
236       ___ Ldr(reg_w(dest), MEM_OP(reg_x(base), offset));
246                                     int32_t offset) {
248   ___ Ldr(reg_x(dest), MEM_OP(reg_x(base), offset));
252                                      int32_t offset) {
253   ___ Ldr(reg_s(dest), MEM_OP(reg_x(base), offset));
257                                      int32_t offset) {
258   ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset));
262                           int32_t offset, size_t size) {
267     ___ Ldr(reg_w(dest.AsWRegister()), MEM_OP(reg_x(base), offset));
271       ___ Ldr(reg_w(dest.AsOverlappingWRegister()), MEM_OP(reg_x(base), offset));
274       ___ Ldr(reg_x(dest.AsXRegister()), MEM_OP(reg_x(base), offset));
277     ___ Ldr(reg_s(dest.AsSRegister()), MEM_OP(reg_x(base), offset));
280     ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset));
539   // Call *(*(SP + base) + offset)
545 void Arm64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*scratch*/) {
648 void Arm64Assembler::SpillRegisters(vixl::CPURegList registers, int offset) {
654     ___ Stp(dst0, dst1, MemOperand(sp, offset));
655     cfi_.RelOffset(DWARFReg(dst0), offset);
656     cfi_.RelOffset(DWARFReg(dst1), offset + size);
657     offset += 2 * size;
661     ___ Str(dst0, MemOperand(sp, offset));
662     cfi_.RelOffset(DWARFReg(dst0), offset);
667 void Arm64Assembler::UnspillRegisters(vixl::CPURegList registers, int offset) {
673     ___ Ldp(dst0, dst1, MemOperand(sp, offset));
676     offset += 2 * size;
680     ___ Ldr(dst0, MemOperand(sp, offset));
720   int32_t offset = frame_size + kArm64PointerSize;
724       // only increment stack offset.
726       offset += spill.getSize();
728       StoreToOffset(reg.AsXRegister(), SP, offset);
729       offset += 8;
731       StoreWToOffset(kStoreWord, reg.AsWRegister(), SP, offset);
732       offset += 4;
734       StoreDToOffset(reg.AsDRegister(), SP, offset);
735       offset += 8;
737       StoreSToOffset(reg.AsSRegister(), SP, offset);
738       offset += 4;