Lines Matching refs:offset
355 void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
356 void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
357 void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
358 void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
471 // Call to address held at [base+offset].
472 void Call(ManagedRegister base, Offset offset, ManagedRegister mscratch) OVERRIDE;
473 void Call(FrameOffset base, Offset offset, ManagedRegister mscratch) OVERRIDE;
474 void CallFromThread64(ThreadOffset<kMips64DoublewordSize> offset,
548 // PC-relative offset (or its most significant 16-bit half, which goes first).
552 // instructions) from the instruction containing the offset.
554 // How large (in bits) a PC-relative offset can be for a given type of branch (kCondBranch is
557 // Some MIPS instructions with PC-relative offsets shift the offset by 2. Encode the shift
599 // Returns the bit size of the signed offset that the branch instruction can handle.
621 // 0x7FFF, adding 1 will overflow the positive offset into the negative range.
626 // case with the addiu instruction and a 16 bit offset.
648 // Returns the location of the instruction(s) containing the offset.
651 // Calculates and returns the offset ready for encoding in the branch instruction(s).