Lines Matching refs:VT
207 getPreferredVectorAction(EVT VT) const {
209 if (VT.getVectorNumElements() == 1)
225 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
234 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const {
329 virtual bool enableAggressiveFMAFusion(EVT VT) const {
335 EVT VT) const;
380 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
381 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
393 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
394 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
400 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
401 return RepRegClassCostForVT[VT.SimpleTy];
407 bool isTypeLegal(EVT VT) const {
408 assert(!VT.isSimple() ||
409 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
410 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
424 LegalizeTypeAction getTypeAction(MVT VT) const {
425 return ValueTypeActions[VT.SimpleTy];
428 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
429 ValueTypeActions[VT.SimpleTy] = Action;
441 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
442 return getTypeConversion(Context, VT).first;
444 LegalizeTypeAction getTypeAction(MVT VT) const {
445 return ValueTypeActions.getTypeAction(VT);
454 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
455 return getTypeConversion(Context, VT).second;
462 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
463 assert(!VT.isVector());
465 switch (getTypeAction(Context, VT)) {
467 return VT;
469 VT = getTypeToTransformTo(Context, VT);
482 /// This method returns the number of registers needed, and the VT for each
483 /// register. It also returns the VT and quantity of the intermediate values
485 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
492 EVT memVT; // memory VT
518 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
527 EVT /*VT*/) const {
533 /// VT must be a legal type. By default, we optimistically assume most
535 virtual bool canOpTrap(unsigned Op, EVT VT) const;
541 EVT /*VT*/) const {
548 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
549 if (VT.isExtended()) return Expand;
553 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
559 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
560 return (VT == MVT::Other || isTypeLegal(VT)) &&
561 (getOperationAction(Op, VT) == Legal ||
562 getOperationAction(Op, VT) == Custom);
568 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
569 return (VT == MVT::Other || isTypeLegal(VT)) &&
570 (getOperationAction(Op, VT) == Legal ||
571 getOperationAction(Op, VT) == Promote);
577 bool isOperationExpand(unsigned Op, EVT VT) const {
578 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
582 bool isOperationLegal(unsigned Op, EVT VT) const {
583 return (VT == MVT::Other || isTypeLegal(VT)) &&
584 getOperationAction(Op, VT) == Legal;
637 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
638 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
640 unsigned Ty = (unsigned)VT.SimpleTy;
645 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
646 return VT.isSimple() &&
647 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
648 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
655 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
656 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
658 unsigned Ty = (unsigned)VT.SimpleTy;
663 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
664 return VT.isSimple() &&
665 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
666 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
673 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
675 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
678 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
679 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
686 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
688 getCondCodeAction(CC, VT) == Legal ||
689 getCondCodeAction(CC, VT) == Custom;
695 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
696 assert(getOperationAction(Op, VT) == Promote &&
702 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
705 assert((VT.isInteger() || VT.isFloatingPoint()) &&
708 MVT NVT = VT;
711 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
755 MVT getRegisterType(MVT VT) const {
756 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
757 return RegisterTypeForVT[VT.SimpleTy];
761 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
762 if (VT.isSimple()) {
763 assert((unsigned)VT.getSimpleVT().SimpleTy <
765 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
767 if (VT.isVector()) {
771 (void)getVectorTypeBreakdown(Context, VT, VT1,
775 if (VT.isInteger()) {
776 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
789 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
790 if (VT.isSimple()) {
791 assert((unsigned)VT.getSimpleVT().SimpleTy <
793 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
795 if (VT.isVector()) {
799 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
801 if (VT.isInteger()) {
802 unsigned BitWidth = VT.getSizeInBits();
803 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
827 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
828 return DL.isBigEndian() || VT == MVT::ppcf128;
892 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
923 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1175 EVT VT) const {
1182 LegalizeTypeAction Action = getTypeAction(Context, VT);
1287 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1288 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1289 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1290 RegClassForVT[VT.SimpleTy] = RC;
1307 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1315 void setOperationAction(unsigned Op, MVT VT,
1318 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1343 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1345 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1348 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1349 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1357 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1359 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1362 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1363 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1368 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1370 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1376 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1377 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1378 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1659 virtual bool isFPExtFree(EVT VT) const {
1660 assert(VT.isFloatingPoint());
1670 virtual bool isFNegFree(EVT VT) const {
1671 assert(VT.isFloatingPoint());
1677 virtual bool isFAbsFree(EVT VT) const {
1678 assert(VT.isFloatingPoint());
1920 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2095 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2140 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2209 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2246 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2248 return isTypeLegal(VT);
2255 EVT /*VT*/) const {
2532 virtual unsigned getRegisterByName(const char* RegName, EVT VT,
2543 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2546 return VT.bitsLT(MinVT) ? MinVT : VT;
2741 StringRef Constraint, MVT VT) const;