Lines Matching refs:VT
218 for (MVT VT : MVT::vector_valuetypes()) {
219 setOperationAction(ISD::ROTL, VT, Expand);
220 setOperationAction(ISD::ROTR, VT, Expand);
240 for (MVT VT : MVT::vector_valuetypes()) {
241 setOperationAction(ISD::SDIVREM, VT, Expand);
242 setOperationAction(ISD::UDIVREM, VT, Expand);
430 for (MVT VT : MVT::fp_valuetypes()) {
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
436 for (MVT VT : MVT::integer_valuetypes())
437 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
597 for (MVT VT : MVT::vector_valuetypes()) {
598 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
600 setOperationAction(ISD::MULHS, VT, Expand);
601 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
602 setOperationAction(ISD::MULHU, VT, Expand);
603 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
605 setOperationAction(ISD::BSWAP, VT, Expand);
608 setTruncStoreAction(VT, InnerVT, Expand);
609 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
610 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
611 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
631 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
632 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
633 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
634 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
636 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
637 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
638 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
639 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
640 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
642 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
643 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
647 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
648 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
649 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
650 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
651 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
652 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
653 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
654 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
655 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
656 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
659 setOperationAction(ISD::FCOPYSIGN, VT.getSimpleVT(), Custom);
662 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
663 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
664 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
665 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
666 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
667 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
668 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
669 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
670 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
671 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
672 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
673 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
675 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
677 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
679 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
682 if (VT != MVT::v8i8 && VT != MVT::v16i8)
683 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
685 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
686 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
687 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
688 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
689 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
691 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
692 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
695 if (!VT.isFloatingPoint() &&
696 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
698 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
701 if (VT.isFloatingPoint() && VT.getVectorElementType() != MVT::f16)
704 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
709 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
710 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
715 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
716 addRegisterClass(VT, &AArch64::FPR64RegClass);
717 addTypeForNEON(VT, MVT::v2i32);
720 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
721 addRegisterClass(VT, &AArch64::FPR128RegClass);
722 addTypeForNEON(VT, MVT::v4i32);
726 EVT VT) const {
727 if (!VT.isVector())
729 return VT.changeVectorElementTypeToInteger();
757 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
758 unsigned MemBits = VT.getScalarType().getSizeInBits();
777 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
779 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
783 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
800 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
812 *Fast = !Subtarget->isCyclone() || VT.getStoreSize() != 16 ||
823 VT == MVT::v2i64;
1178 EVT VT = LHS.getValueType();
1180 if (VT.isFloatingPoint())
1181 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1213 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1438 EVT VT = RHS.getValueType();
1447 if ((VT == MVT::i32 && C != 0x80000000 &&
1449 (VT == MVT::i64 && C != 0x80000000ULL &&
1452 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1453 RHS = DAG.getConstant(C, dl, VT);
1458 if ((VT == MVT::i32 && C != 0 &&
1460 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1462 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1463 RHS = DAG.getConstant(C, dl, VT);
1468 if ((VT == MVT::i32 && C != INT32_MAX &&
1470 (VT == MVT::i64 && C != INT64_MAX &&
1473 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1474 RHS = DAG.getConstant(C, dl, VT);
1479 if ((VT == MVT::i32 && C != UINT32_MAX &&
1481 (VT == MVT::i64 && C != UINT64_MAX &&
1484 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1485 RHS = DAG.getConstant(C, dl, VT);
1725 EVT VT = Op.getValueType();
1728 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1731 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1850 EVT VT = Op.getValueType();
1862 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1867 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1870 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1873 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1874 VT.getVectorNumElements());
1876 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1915 EVT VT = Op.getValueType();
1920 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1925 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1928 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1931 EVT CastVT = VT.changeVectorElementTypeToInteger();
1933 return DAG.getNode(Op.getOpcode(), dl, VT, In);
2054 EVT VT = N->getValueType(0);
2061 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2086 EVT VT = N->getValueType(0);
2088 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
2089 unsigned NumElts = VT.getVectorNumElements();
2144 EVT VT = Op.getValueType();
2145 assert(VT.is128BitVector() && VT.isInteger() &&
2177 if (VT == MVT::v2i64)
2195 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2203 return DAG.getNode(N0->getOpcode(), DL, VT,
2204 DAG.getNode(NewOpc, DL, VT,
2206 DAG.getNode(NewOpc, DL, VT,
2377 // At this point, Ins[].VT may already be promoted to i32. To correctly
2380 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2387 MVT ValVT = Ins[i].VT;
2472 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2904 MVT ArgVT = Outs[i].VT;
2913 // At this point, Outs[].VT may already be promoted to i32. To correctly
2916 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2921 MVT ValVT = Outs[i].VT;
3027 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
3030 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
3710 EVT VT = Op.getValueType();
3717 if (SrcVT.bitsLT(VT))
3718 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3719 else if (SrcVT.bitsGT(VT))
3720 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
3726 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3728 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3731 if (!VT.isVector()) {
3740 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3749 if (!VT.isVector()) {
3766 if (VT == MVT::f64 || VT == MVT::v2f64) {
3775 if (VT == MVT::f32)
3776 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3777 else if (VT == MVT::f64)
3778 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3780 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3801 EVT VT = Op.getValueType();
3803 if (VT == MVT::i32)
3812 if (VT == MVT::i64)
3828 EVT VT = Op.getValueType();
3829 SDValue TVal = DAG.getConstant(1, dl, VT);
3830 SDValue FVal = DAG.getConstant(0, dl, VT);
3853 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3872 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3882 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3885 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4002 EVT VT = TVal.getValueType();
4003 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
4009 EVT VT = TVal.getValueType();
4017 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4023 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4283 EVT VT = Op.getValueType();
4302 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4309 if (VT.isInteger() && !VT.isVector())
4312 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4330 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4337 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4346 EVT VT = Op.getValueType();
4350 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4352 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4359 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4376 EVT VT = Op.getValueType();
4382 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4383 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4389 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4397 EVT VT = Op.getValueType();
4398 unsigned VTBits = VT.getSizeInBits();
4409 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4417 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4423 SDValue LoBitsForLo = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4425 DAG.getNode(ISD::OR, dl, VT, LoBitsForLo, HiBitsForLo);
4430 SDValue LoForBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4431 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4436 SDValue HiForNormalShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4439 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4441 : DAG.getConstant(0, dl, VT);
4442 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4455 EVT VT = Op.getValueType();
4456 unsigned VTBits = VT.getSizeInBits();
4465 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4473 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4478 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4480 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
4482 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4487 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4492 SDValue LoForBigShift = DAG.getConstant(0, dl, VT);
4493 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4494 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4507 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4510 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4513 if (VT == MVT::f64)
4515 else if (VT == MVT::f32)
4606 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4610 if (VT.getSizeInBits() == 64)
4614 if (VT == MVT::f32)
4616 if (VT.getSizeInBits() == 64)
4618 if (VT.getSizeInBits() == 128)
4624 if (VT.getSizeInBits() == 128)
4635 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4801 EVT VT = V64Reg.getValueType();
4802 unsigned NarrowSize = VT.getVectorNumElements();
4803 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4821 EVT VT = V128Reg.getValueType();
4822 unsigned WideSize = VT.getVectorNumElements();
4823 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4836 EVT VT = Op.getValueType();
4837 unsigned NumElts = VT.getVectorNumElements();
4892 EVT SmallestEltTy = VT.getVectorElementType();
4900 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4901 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4910 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4916 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4919 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4920 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4929 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4986 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4999 VT.getVectorElementType().getSizeInBits());
5022 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
5027 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
5028 unsigned NumElts = VT.getVectorNumElements();
5058 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
5065 unsigned NumElts = VT.getVectorNumElements();
5100 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5104 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5108 unsigned NumElts = VT.getVectorNumElements();
5127 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5128 unsigned NumElts = VT.getVectorNumElements();
5141 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5142 unsigned NumElts = VT.getVectorNumElements();
5154 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5155 unsigned NumElts = VT.getVectorNumElements();
5168 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5169 unsigned NumElts = VT.getVectorNumElements();
5185 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5186 unsigned Half = VT.getVectorNumElements() / 2;
5204 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5205 unsigned NumElts = VT.getVectorNumElements();
5254 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5255 if (VT.getSizeInBits() != 128)
5258 unsigned NumElts = VT.getVectorNumElements();
5276 EVT VT = Op.getValueType();
5281 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5282 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5287 if (!isConcatMask(Mask, VT, SplitV0))
5290 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5291 VT.getVectorNumElements() / 2);
5300 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5340 EVT VT = OpLHS.getValueType();
5347 if (VT.getVectorElementType() == MVT::i32 ||
5348 VT.getVectorElementType() == MVT::f32)
5349 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5351 if (VT.getVectorElementType() == MVT::i16 ||
5352 VT.getVectorElementType() == MVT::f16)
5353 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5355 assert(VT.getVectorElementType() == MVT::i8);
5356 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5361 EVT EltTy = VT.getVectorElementType();
5374 if (VT.getSizeInBits() == 64)
5377 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5383 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5387 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5390 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5393 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5396 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5399 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5402 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5486 EVT VT = Op.getValueType();
5513 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5525 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5526 Lane -= Idx * VT.getVectorNumElements() / 2;
5528 } else if (VT.getSizeInBits() == 64)
5531 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5534 if (isREVMask(ShuffleMask, VT, 64))
5536 if (isREVMask(ShuffleMask, VT, 32))
5538 if (isREVMask(ShuffleMask, VT, 16))
5543 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5550 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5557 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5561 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5565 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5570 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5574 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5578 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5598 SrcLane -= VT.getVectorNumElements();
5602 EVT ScalarVT = VT.getVectorElementType();
5608 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5615 unsigned NumElts = VT.getVectorNumElements();
5640 EVT VT = BVN->getValueType(0);
5645 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5650 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5651 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5666 EVT VT = Op.getValueType();
5671 APInt CnstBits(VT.getSizeInBits(), 0);
5672 APInt UndefBits(VT.getSizeInBits(), 0);
5688 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5692 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5697 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5701 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5706 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5710 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5715 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5719 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5724 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5728 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5733 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5737 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5764 EVT VT = Bvec->getValueType(0);
5765 unsigned NumElts = VT.getVectorNumElements();
5792 EVT VT = N->getValueType(0);
5794 if (!VT.isVector())
5826 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5839 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5865 EVT VT = Op.getValueType();
5875 APInt CnstBits(VT.getSizeInBits(), 0);
5876 APInt UndefBits(VT.getSizeInBits(), 0);
5889 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5893 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5898 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5902 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5907 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5911 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5916 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5920 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5925 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5929 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5934 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5938 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5960 EVT VT = Op.getValueType();
5961 EVT EltTy= VT.getVectorElementType();
5975 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5981 EVT VT = Op.getValueType();
5985 APInt CnstBits(VT.getSizeInBits(), 0);
5986 APInt UndefBits(VT.getSizeInBits(), 0);
6001 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
6007 if (VT.getSizeInBits() == 128) {
6010 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6016 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6021 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6025 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6030 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6034 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6039 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6043 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6048 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6052 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6057 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6061 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6066 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6070 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6075 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6079 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6084 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6088 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6093 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
6096 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6102 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
6105 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6109 VT.getSizeInBits() == 128) {
6113 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6120 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6124 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6129 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6133 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6138 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6142 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6147 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6151 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6156 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6160 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6165 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6169 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6174 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6178 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6183 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
6187 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
6210 unsigned NumElts = VT.getVectorNumElements();
6242 return DAG.getUNDEF(VT);
6245 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
6252 Value.getValueType() != VT)
6253 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
6263 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
6264 return DAG.getNode(Opcode, dl, VT, Value, Lane);
6267 if (VT.getVectorElementType().isFloatingPoint()) {
6269 EVT EltTy = VT.getVectorElementType();
6279 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6288 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
6294 // Note that type legalization likely mucked about with the VT of the
6296 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
6321 SDValue Vec = DAG.getUNDEF(VT);
6323 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6335 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6345 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6359 EVT VT = Op.getOperand(0).getValueType();
6361 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6366 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6367 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6368 VT == MVT::v8f16)
6371 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6372 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6393 EVT VT = Op.getOperand(0).getValueType();
6395 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6400 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6401 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6402 VT == MVT::v8f16)
6405 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6406 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6426 EVT VT = Op.getOperand(0).getValueType();
6429 if (!VT.isVector())
6445 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6452 EVT VT) const {
6453 if (VT.getVectorNumElements() == 4 &&
6454 (VT.is128BitVector() || VT.is64BitVector())) {
6477 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6478 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6479 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6480 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6481 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6482 isZIPMask(M, VT, DummyUnsigned) ||
6483 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6484 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6485 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6486 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6487 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6513 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6514 assert(VT.isVector() && "vector shift count is not a vector type");
6515 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6524 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
6525 assert(VT.isVector() && "vector shift count is not a vector type");
6526 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
6534 EVT VT = Op.getValueType();
6540 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6547 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6548 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6550 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6557 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {
6560 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6570 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6572 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6582 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6585 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6589 APInt CnstBits(VT.getSizeInBits(), 0);
6590 APInt UndefBits(VT.getSizeInBits(), 0);
6601 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6603 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6604 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6608 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6609 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6612 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6613 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6616 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6617 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6620 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6621 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6629 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6630 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6640 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6642 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6643 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6647 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6648 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6651 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6652 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6655 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6656 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6659 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6660 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6662 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6664 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6667 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6668 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6670 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6672 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6878 EVT VT = getValueType(DL, User->getOperand(0)->getType());
6880 if (isFMAFasterThanFMulAndFAdd(VT) &&
6881 isOperationLegalOrCustom(ISD::FMA, VT) &&
7270 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7271 VT = VT.getScalarType();
7273 if (!VT.isSimple())
7276 switch (VT.getSimpleVT().SimpleTy) {
7300 EVT VT = N->getValueType(0);
7303 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
7339 EVT VT = N->getValueType(0);
7347 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
7351 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
7352 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7356 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7357 N0.getOperand(0), DAG.getConstant(0, DL, VT));
7358 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7380 EVT VT = N->getValueType(0);
7381 if ((VT != MVT::i32 && VT != MVT::i64) ||
7388 SDValue Zero = DAG.getConstant(0, DL, VT);
7389 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
7394 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7395 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7405 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7414 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7430 EVT VT = N->getValueType(0);
7437 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7439 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7446 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7448 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7456 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7458 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7465 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
7468 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7469 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7489 EVT VT = N->getValueType(0);
7490 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7492 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7510 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7515 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7529 EVT VT = N->getValueType(0);
7530 if (VT != MVT::f32 && VT != MVT::f64)
7534 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7545 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7556 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7718 EVT VT = N->getValueType(0);
7722 if (VT != MVT::i32 && VT != MVT::i64)
7742 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7750 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7756 EVT VT = N->getValueType(0);
7760 if (!VT.isVector())
7773 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7783 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7794 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7807 EVT VT = N->getValueType(0);
7809 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7839 EVT VT = N->getValueType(0);
7840 if (!VT.isVector())
7842 if (VT.getSimpleVT().getSizeInBits() != 64)
7869 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7877 unsigned NumElements = VT.getVectorNumElements();
7880 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7883 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7893 EVT VT = N->getValueType(0);
7916 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7921 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7937 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7938 assert(VT.getVectorElementType().getSizeInBits() == 64);
7939 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7964 return DAG.getNode(ISD::BITCAST, dl, VT,
8198 EVT VT = Op->getValueType(0);
8199 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8200 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
8220 MVT VT = N->getSimpleValueType(0);
8221 if (!VT.is128BitVector()) {
8244 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
8250 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8253 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
8490 // If the vector type isn't a simple VT, it's beyond the scope of what
8498 // If the source VT is a 64-bit vector, we can play games and get the
8539 EVT VT = StVal.getValueType();
8543 if (VT.isFloatingPoint())
8551 unsigned NumVecElts = VT.getVectorNumElements();
8616 EVT VT = StVal.getValueType();
8620 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8628 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8639 unsigned NumElts = VT.getVectorNumElements() / 2;
8640 // Split VT into two.
8642 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8667 EVT VT = N->getValueType(0);
8678 if (MemVT != VT.getVectorElementType())
8714 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8736 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
9764 EVT VT;
9767 VT = LD->getMemoryVT();
9770 VT = ST->getMemoryVT();
9785 EVT VT;
9788 VT = LD->getMemoryVT();
9791 VT = ST->getMemoryVT();
9883 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9884 MVT SVT = VT.getSimpleVT();
9891 return TargetLoweringBase::getPreferredVectorAction(VT);