Cross Reference: /external/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines Matching defs:Src1
835     unsigned Src1 = MI->getOperand(2).getReg();
840         .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
844         .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
911   MachineOperand &Src1 = MI->getOperand(Src1Idx);
927   if (!Src1.isReg()) {
929     if (NewMI || !Src1.isImm() ||
954     if (Src1.isImm())
955       Src0.ChangeToImmediate(Src1.getImm());
959     Src1.ChangeToRegister(Reg, false);
960     Src1.setSubReg(SubReg);
996   MachineOperand &Src1 = MI->getOperand(Src1Idx);
997   if (Src1.isImm()) {
1002   } else if (Src1.isReg()) {
1063     MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
1069       if (!Src1->isReg() ||
1070           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1097       unsigned Src1Reg = Src1->getReg();
1098       unsigned Src1SubReg = Src1->getSubReg();
1103       Src0->setIsKill(Src1->isKill());
1105       Src1->setReg(Src2Reg);
1106       Src1->setSubReg(Src2SubReg);
1107       Src1->setIsKill(Src2->isKill());
1134       if (!Src1->isReg() ||
1135           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1268   const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1275                  .addImm(0) // Src1 mods
1276                  .addOperand(*Src1)
1559     const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1561     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1562       if (!compareMachineOp(Src0, Src1) &&
1851   MachineOperand &Src1 = MI->getOperand(Src1Idx);
1870   if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
1890   if ((!Src1.isImm() && !Src1.isReg()) ||
1908   if (Src1.isImm())
1909     Src0.ChangeToImmediate(Src1.getImm());
1910   else if (Src1.isReg()) {
1911     Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
1912     Src0.setSubReg(Src1.getSubReg());
1916   Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
1917   Src1.setSubReg(Src0SubReg);
2710   MachineOperand &Src1 = Inst->getOperand(2);
2721   const TargetRegisterClass *Src1RC = Src1.isReg() ?
2722     MRI.getRegClass(Src1.getReg()) :
2729   MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2743   MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,