Cross Reference: /external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines Matching defs:V0
261   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
262   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
263   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
264   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
267   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1592 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1593   SDLoc dl(V0.getNode());
1598   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1603 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1604   SDLoc dl(V0.getNode());
1609   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1614 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1615   SDLoc dl(V0.getNode());
1620   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1625 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1626   SDLoc dl(V0.getNode());
1631   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1636 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1638   SDLoc dl(V0.getNode());
1645   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1651 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1653   SDLoc dl(V0.getNode());
1660   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1666 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1668   SDLoc dl(V0.getNode());
1675   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1994       SDValue V0 = N->getOperand(Vec0Idx + 0);
1997         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2005         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2047   SDValue V0 = N->getOperand(Vec0Idx + 0);
2053   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2159   SDValue V0 = N->getOperand(Vec0Idx + 0);
2163       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2165       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2172       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2174       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2295   SDValue V0 = N->getOperand(FirstTblReg + 0);
2298     RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2306     RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
3335     SDValue V0 = N->getOperand(0);
3337     SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3832     SDValue V0 = N->getOperand(i+1);
3834     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();