Cross Reference: /external/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

Lines Matching defs:Op2
701   MachineOperand &Op2 = MI->getOperand(2);
719   if (Op2.isImm()) {
721       .addImm(Op2.getImm());
722   } else if (Op2.isReg()) {
724       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
755   MachineOperand &Op2 = MI->getOperand(2);
756   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
757   int64_t Sh64 = Op2.getImm();
879   MachineOperand &Op2 = MI->getOperand(2);
881   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
896   unsigned RS2 = getRegState(Op2);
902   // Op0 = S2_asl_i_p_or Op1, Op2, Op3
903   // means:  Op0 = or (Op1, asl(Op2, Op3))
920       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
923       .addReg(Op2.getReg(), RS2, HiSR);
927       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
931       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
940       .addReg(Op2.getReg(), RS2, HiSR)
951       .addReg(Op2.getReg(), RS2, LoSR);
962       .addReg(Op2.getReg(), RS2, LoSR)