/external/webrtc/webrtc/voice_engine/test/auto_test/ |
H A D | voe_test_interface.h | 31 CPU = 4 enumerator in enum:voetest::TestType
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/external/llvm/lib/Target/BPF/ |
H A D | BPFSubtarget.cpp | 28 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU, argument 30 : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
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H A D | BPFTargetMachine.cpp | 40 StringRef CPU, StringRef FS, 44 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, 47 Subtarget(TT, CPU, FS, *this) { 39 BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430Subtarget.cpp | 29 MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument 34 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, argument 36 : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), 37 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 28 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, argument 30 : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
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/external/vixl/src/vixl/a64/ |
H A D | cpu-a64.h | 35 class CPU { class in namespace:vixl 37 // Initialise CPU support.
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/external/clang/include/clang/Basic/ |
H A D | TargetOptions.h | 30 /// If given, the name of the target CPU to generate code for. 31 std::string CPU; member in class:clang::TargetOptions
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/external/libvpx/libvpx/third_party/libyuv/source/ |
H A D | x86inc.asm | 97 CPU amdnop label
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/external/llvm/include/llvm/CodeGen/ |
H A D | CommandFlags.h | 305 // If user asked for the 'native' CPU, autodetect here. If autodection fails, 306 // this will set the CPU to an empty string which tells the target to 317 // If user asked for the 'native' CPU, we need to autodetect features. 318 // This is necessary for x86 where the CPU might not support all the 319 // features the autodetected CPU name lists in the target. For example, 334 /// \brief Set function attributes of functions in Module M based on CPU, 336 static inline void setFunctionAttributes(StringRef CPU, StringRef Features, argument 342 if (!CPU.empty()) 344 "target-cpu", CPU);
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/external/llvm/lib/CodeGen/ |
H A D | LLVMTargetMachine.cpp | 76 const Triple &TT, StringRef CPU, 80 : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { 74 LLVMTargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | ParallelCG.cpp | 29 const Target *TheTarget, StringRef CPU, StringRef Features, 34 M->getTargetTriple(), CPU, Features, Options, RM, CM, OL)); 44 ArrayRef<llvm::raw_pwrite_stream *> OSs, StringRef CPU, 55 codegen(M.get(), *OSs[0], TheTarget, CPU, Features, Options, RM, CM, 73 [TheTarget, CPU, Features, Options, RM, CM, OL, FileType, 84 codegen(MPartInCtx.get(), *ThreadOS, TheTarget, CPU, Features, 28 codegen(Module *M, llvm::raw_pwrite_stream &OS, const Target *TheTarget, StringRef CPU, StringRef Features, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, TargetMachine::CodeGenFileType FileType) argument 43 splitCodeGen(std::unique_ptr<Module> M, ArrayRef<llvm::raw_pwrite_stream *> OSs, StringRef CPU, StringRef Features, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, TargetMachine::CodeGenFileType FileType) argument
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/external/llvm/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 26 CPPTargetMachine(const Target &T, const Triple &TT, StringRef CPU, argument 29 : TargetMachine(T, "", TT, CPU, FS, Options) {}
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 63 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument 64 CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU); 91 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, argument 93 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), 94 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), 99 // Initialize scheduling itinerary for the specified CPU.
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H A D | HexagonTargetMachine.cpp | 125 StringRef CPU, StringRef FS, 131 "n16:32", TT, CPU, FS, Options, RM, CM, OL), 144 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) local 151 auto &I = SubtargetMap[CPU + FS]; 157 I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this); 124 HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonELFObjectWriter.cpp | 26 StringRef CPU; member in class:__anon12629::HexagonELFObjectWriter 39 CPU(C) {} 248 StringRef CPU) { 249 MCELFObjectTargetWriter *MOTW = new HexagonELFObjectWriter(OSABI, CPU); 246 createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXSubtarget.cpp | 29 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, argument 31 // Provide the default CPU if we don't have one. 32 if (CPU.empty() && FS.size()) 34 TargetName = CPU.empty() ? "sm_20" : CPU; 46 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, argument 49 : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), 50 InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcSubtarget.cpp | 29 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, argument 38 std::string CPUName = CPU; 52 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU, argument 55 : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), 56 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSubtarget.cpp | 26 SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument 27 std::string CPUName = CPU; 35 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, argument 38 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), 44 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySubtarget.cpp | 40 const std::string &CPU, 43 : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false), 44 CPUString(CPU), TargetTriple(TT), FrameLowering(), 39 WebAssemblySubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) argument
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUSubtarget.cpp | 23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument 24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) { 25 InstrItins = getInstrItineraryForCPU(CPU); 30 StringRef GPU = CPU;
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/external/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFAsmBackend.cpp | 98 const Triple &TT, StringRef CPU) { 104 const Triple &TT, StringRef CPU) { 96 createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) argument 102 createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) argument
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H A D | BPFMCTargetDesc.cpp | 50 StringRef CPU, StringRef FS) { 51 return createBPFMCSubtargetInfoImpl(TT, CPU, FS); 49 createBPFMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) argument
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcAsmBackend.cpp | 302 const Triple &TT, StringRef CPU) { 300 createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64Subtarget.cpp | 50 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, argument 53 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), 58 CPUString(CPU), TargetTriple(TT), FrameLowering(),
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetMachine.cpp | 67 computeTargetABI(const Triple &TT, StringRef CPU, argument 86 CPU.startswith("cortex-m")) { 121 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument 124 auto ABI = computeTargetABI(TT, CPU, Options); 177 StringRef CPU, StringRef FS, 181 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 182 CPU, FS, Options, RM, CM, OL), 183 TargetABI(computeTargetABI(TT, CPU, Options)), 185 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { 209 std::string CPU local 176 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument [all...] |