/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 33 enum CondCode { enum in namespace:llvm::Mips 73 const char *MipsFCCToString(Mips::CondCode CC);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 33 enum CondCode { enum in namespace:llvm::X86 64 unsigned GetCondBranchFromCond(CondCode CC); 68 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 72 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 76 CondCode getCondFromCMovOpc(unsigned Opc); 80 CondCode GetOppositeBranchCondition(CondCode CC);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 38 enum CondCode { enum in namespace:llvm::XCore 137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 238 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 828 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 841 enum CondCode { enum in namespace:llvm::ISD 874 inline bool isSignedIntSetCC(CondCode Code) { 880 inline bool isUnsignedIntSetCC(CondCode Code) { 887 inline bool isTrueWhenEqual(CondCode Cond) { 895 inline unsigned getUnorderedFlavor(CondCode Cond) { 901 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 905 CondCode getSetCCSwappedOperands(CondCode Operatio [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1916 unsigned CondCode = MI->getOperand(3).getImm(); local 1918 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1920 NewMI.addImm(CondCode);
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H A D | ARMISelLowering.cpp | 177 const ISD::CondCode Cond; 262 const ISD::CondCode Cond; 361 const ISD::CondCode Cond; 1312 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1329 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, argument 1335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1337 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1339 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1340 case ISD::SETOLT: CondCode 3332 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3519 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument 3628 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3642 ARMCC::CondCodes CondCode, CondCode2; local 3786 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3834 ARMCC::CondCodes CondCode, CondCode2; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 136 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 1989 ISD::CondCode CC, SDLoc dl) { 2092 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 2123 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 2155 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, 2266 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2739 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2911 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2937 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); local 2938 SDValue Ops[] = { getI32Imm(PCC, dl), CondCode, [all...] |
/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 168 enum CondCode enum in namespace:nv50_ir 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond); 201 AArch64CC::CondCode Code; 255 struct CondCodeOp CondCode; member in union:__anon12455::AArch64Operand::__anon12456 287 CondCode = o.CondCode; 352 AArch64CC::CondCode getCondCode() const { 354 return CondCode.Code; 1693 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { 1695 Op->CondCode.Code = Code; 2349 AArch64CC::CondCode AArch64AsmParse [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 985 unsigned CondCode = MI->getOperand(3).getImm(); local 998 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 1050 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 1078 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument 1079 AArch64CC::CondCode &CondCode, 1080 AArch64CC::CondCode &CondCode2) { 1087 CondCode = AArch64CC::EQ; 1091 CondCode 1142 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument 1166 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); local [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::AArch64CC 214 inline static const char *getCondCodeName(CondCode Code) { 236 inline static CondCode getInvertedCondCode(CondCode Code) { 239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
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