Searched defs:DstReg (Results 1 - 25 of 63) sorted by relevance

123

/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, argument
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
H A DR600ExpandSpecialInstrs.cpp96 unsigned DstReg = MI.getOperand(0).getReg(); local
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0);
125 unsigned DstBase = TRI.getHWRegIndex(DstReg);
126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
H A DAMDGPUInstrInfo.cpp37 unsigned &SrcReg, unsigned &DstReg,
36 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
/external/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp87 unsigned DstReg = MI->getOperand(0).getReg(); local
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
95 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
113 if (DstReg != InsReg) {
125 // Implicitly define DstReg for subsequent uses.
128 CopyMI->addRegisterDefined(DstReg);
H A DOptimizePHIs.cpp92 unsigned DstReg = MI->getOperand(0).getReg(); local
105 if (SrcReg == DstReg)
135 unsigned DstReg = MI->getOperand(0).getReg(); local
136 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
H A DRegisterCoalescer.h33 unsigned DstReg; member in class:llvm::CoalescerPair
38 /// The sub-register index of the old DstReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
54 /// The register class of the coalesced register, or NULL if DstReg
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
76 /// because DstReg is a physical register, or SubIdx is set.
83 /// Return true if DstReg i
[all...]
H A DMachineSink.cpp163 unsigned DstReg = MI->getOperand(0).getReg(); local
165 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
170 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
179 MRI->replaceRegWith(DstReg, SrcReg);
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp143 unsigned DstReg = MI.getOperand(0).getReg(); local
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
146 .addReg(DstReg).addImm(-Offset);
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
149 .addReg(DstReg).addImm(Offset);
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp117 const unsigned DstReg = MI.getOperand(0).getReg(); local
121 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
122 .addReg(DstReg)
182 const unsigned DstReg = MI.getOperand(0).getReg();
198 .addReg(DstReg,
200 .addReg(DstReg)
223 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
224 .addReg(DstReg)
365 const unsigned DstReg = MI.getOperand(0).getReg();
372 .addReg(DstReg,
[all...]
H A DAArch64ConditionalCompares.cpp179 /// Check if an operand defining DstReg is dead.
180 bool isDeadDef(unsigned DstReg);
258 bool SSACCmpConv::isDeadDef(unsigned DstReg) { argument
260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
262 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
266 return MRI->use_nodbg_empty(DstReg);
/external/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp132 unsigned DstReg = Copy.getOperand(0).getReg(); local
144 TargetRegisterInfo::isVirtualRegister(DstReg) ?
145 MRI.getRegClass(DstReg) :
146 TRI.getPhysRegClass(DstReg);
182 unsigned DstReg = MI.getOperand(0).getReg(); local
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
186 if (!MRI.hasOneUse(DstReg))
189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
204 MRI.setRegClass(DstReg, DstRC);
H A DSIShrinkInstructions.cpp251 unsigned DstReg = MI.getOperand(0).getReg(); local
252 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
264 if (DstReg != AMDGPU::VCC)
H A DR600ExpandSpecialInstrs.cpp126 unsigned DstReg; local
129 DstReg = MI.getOperand(Chan).getReg();
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
155 unsigned DstReg; local
158 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
160 DstReg = MI.getOperand(Chan-2).getReg();
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
183 unsigned DstReg = MI.getOperand(0).getReg(); local
187 TRI.getSubReg(DstReg, TR
202 unsigned DstReg = MI.getOperand(0).getReg(); local
272 unsigned DstReg = MI.getOperand( local
[all...]
H A DR600OptimizeVectorRegisters.cpp191 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); local
197 DstReg)
211 SrcVec = DstReg;
H A DSILoadStoreOptimizer.cpp73 unsigned DstReg,
197 unsigned DstReg,
203 O.substVirtReg(DstReg, SubIdx, *TRI);
196 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp287 // DstReg = LDriw_pred [R30], ofst.
288 int DstReg = MI->getOperand(0).getReg(); local
289 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
310 DstReg).addReg(HEXAGON_RESERVED_REG_2);
319 DstReg).addReg(HEXAGON_RESERVED_REG_2);
325 DstReg).addReg(HEXAGON_RESERVED_REG_2);
H A DHexagonPeephole.cpp141 unsigned DstReg = Dst.getReg(); local
144 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
149 PeepholeMap[DstReg] = SrcReg;
163 unsigned DstReg = Dst.getReg(); local
165 PeepholeMap[DstReg] = SrcReg;
180 unsigned DstReg = Dst.getReg(); local
182 PeepholeDoubleRegsMap[DstReg] =
192 unsigned DstReg = Dst.getReg(); local
195 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
200 PeepholeMap[DstReg]
215 unsigned DstReg = Dst.getReg(); local
[all...]
/external/mesa3d/src/mesa/main/
H A Datifragshader.h56 struct atifragshader_dst_register DstReg[2]; member in struct:atifs_instruction
/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp132 unsigned DstReg = MI->getOperand(0).getReg(); local
136 if (Uses.count(DstReg) || Defs.count(SrcReg))
H A DMLxExpansionPass.cpp275 unsigned DstReg = MI->getOperand(0).getReg(); local
301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
100 DstReg = MI.getOperand(0).getReg();
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
114 DstReg = MI.getOperand(0).getReg();
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
126 DstReg = MI.getOperand(0).getReg();
128 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
136 DstReg
[all...]
H A DHexagonMCDuplexInfo.cpp181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
192 DstReg = MCI.getOperand(0).getReg();
196 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
210 DstReg = MCI.getOperand(0).getReg();
212 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
231 DstReg = MCI.getOperand(0).getReg();
233 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
241 DstReg = MCI.getOperand(0).getReg();
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
251 DstReg
538 unsigned DstReg, SrcReg; local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64; local
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
138 I->getOperand(0).setReg(DstReg);
/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp246 unsigned DstReg = LEA->getOperand(0).getReg(); local
248 return SrcReg == DstReg &&
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h79 struct rc_dst_register DstReg; member in struct:rc_sub_instruction

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