| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.h | 45 unsigned Gen; member in class:llvm::R600TargetLowering
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| H A D | AMDGPUInstrInfo.cpp | 331 static int getMCOpcode(uint16_t Opcode, unsigned Gen) { argument
332 return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
343 static enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) { argument
344 switch (Gen) {
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| H A D | AMDGPUSubtarget.h | 66 Generation Gen; member in class:llvm::AMDGPUSubtarget
135 return Gen;
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| H A D | AMDGPUISelDAGToDAG.cpp | 1112 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration(); local
1114 int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1126 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
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| /external/v8/tools/unittests/ |
| H A D | run_perf_test.py | 470 def Gen(): function in function:PerfTest.testUnzip
473 l, r = run_perf.Unzip(Gen())
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| /external/clang/lib/Serialization/ |
| H A D | MultiOnDiskHashTable.h | 280 Generator Gen; member in class:clang::serialization::MultiOnDiskHashTableGenerator
283 MultiOnDiskHashTableGenerator() : Gen() {}
287 Gen.insert(Key, Data, Info);
310 if (!Gen.contains(KV.first, Info))
311 Gen.insert(KV.first, Info.ImportData(KV.second), Info);
319 uint32_t BucketOffset = Gen.Emit(OutStream, Info);
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| /external/llvm/tools/verify-uselistorder/ |
| H A D | verify-uselistorder.cpp | 381 static void shuffleValueUseLists(Value *V, std::minstd_rand0 &Gen, argument
389 shuffleValueUseLists(Op, Gen, Seen);
404 auto I = Dist(Gen);
508 std::minstd_rand0 Gen(std::minstd_rand0::default_seed + SeedOffset);
510 changeUseLists(M, [&](Value *V) { shuffleValueUseLists(V, Gen, Seen); });
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| /external/clang/lib/CodeGen/ |
| H A D | CodeGenAction.cpp | 56 std::unique_ptr<CodeGenerator> Gen; member in class:clang::BackendConsumer
79 Gen(CreateLLVMCodeGen(Diags, InFile, HeaderSearchOpts, PPOpts,
93 Gen->HandleCXXStaticMemberVarInstantiation(VD);
104 Gen->Initialize(Ctx);
106 TheModule.reset(Gen->GetModule());
120 Gen->HandleTopLevelDecl(D);
135 Gen->HandleInlineMethodDefinition(D);
147 Gen->HandleTranslationUnit(C);
159 llvm::Module *M = Gen->ReleaseModule();
204 Gen
[all...] |
| H A D | CGStmtOpenMP.cpp | 2333 auto Gen = local
2340 XLValue, ExprRValue, BOUE->getOpcode(), IsXLHSInRHSPart, AO, Loc, Gen);
2395 auto &&Gen = [&CGF, &NewVVal, UE, ExprRValue, XRValExpr, ERValExpr, local
2404 XLValue, ExprRValue, BOUE->getOpcode(), IsXLHSInRHSPart, AO, Loc, Gen);
2423 auto &&Gen = [&CGF, &NewVVal, ExprRValue](RValue XRValue) -> RValue { local
2430 Loc, Gen);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 284 BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
292 auto &BBGen = Gen[&MBB];
318 // current basic block definition for this color, if any, is in Gen.
392 /// Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
397 BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
422 // Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
425 if (Gen[&MBB][CurReg])
426 BBOutSet.insert(Gen[&MBB][CurReg]);
453 // Gen: generated color in this block (one operation per color).
458 BlockToInstrPerColor Gen; local
282 initReachingDef(const MachineFunction &MF, InstrToInstrs *ColorOpToReachedUses, BlockToInstrPerColor &Gen, BlockToRegSet &Kill, BlockToSetOfInstrsPerColor &ReachableUses, const MapRegToId &RegToId, const MachineInstr *DummyOp, bool ADRPMode) argument
393 reachingDefAlgorithm(const MachineFunction &MF, InstrToInstrs *ColorOpToReachedUses, BlockToSetOfInstrsPerColor &In, BlockToSetOfInstrsPerColor &Out, BlockToInstrPerColor &Gen, BlockToRegSet &Kill, BlockToSetOfInstrsPerColor &ReachableUses, unsigned NbReg) argument
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1322 SDNode *Gen = LiveRegGens[CallResource]->getNode(); local
1323 while (SDNode *Glued = Gen->getGluedNode())
1324 Gen = Glued;
1325 if (!IsChainDependent(Gen, Node, 0, TII) &&
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