Searched defs:Instr (Results 1 - 25 of 40) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMFeatures.h22 bool IsCPSRDead(InstrType *Instr);
25 inline bool isV8EligibleForIT(InstrType *Instr) { argument
26 switch (Instr->getOpcode()) {
53 return IsCPSRDead(Instr);
79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXImageOptimizer.cpp61 Instruction &Instr = *I; local
69 Changed |= replaceIsTypePSampler(Instr);
72 Changed |= replaceIsTypePSurface(Instr);
75 Changed |= replaceIsTypePTexture(Instr);
/external/llvm/lib/Target/XCore/
H A DXCoreLowerThreadLocal.cpp78 createReplacementInstr(ConstantExpr *CE, Instruction *Instr) { argument
79 IRBuilder<true,NoFolder> Builder(Instr);
146 } else if (Instruction *Instr = dyn_cast<Instruction>(WU)) {
147 Instruction *NewInst = createReplacementInstr(CE, Instr);
148 Instr->replaceUsesOfWith(CE, NewInst);
/external/llvm/lib/CodeGen/AsmPrinter/
H A DWinCodeViewLineTables.cpp292 MCSymbol *Instr = FI.Instrs[J]; local
293 assert(InstrInfo.count(Instr));
322 EmitLabelDiff(*Asm->OutStreamer, Fn, Instr);
323 Asm->EmitInt32(InstrInfo[Instr].LineNumber);
/external/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp239 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, argument
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1)
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0)
258 if (isa<const LoadInst>(Instr) && OpIdx > 0)
262 if (isa<const StoreInst>(Instr) && OpIdx > 1)
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0)
271 if (isa<const LandingPadInst>(Instr))
275 if (isa<const SwitchInst>(Instr))
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H A DAArch64CollectLOH.cpp530 static bool isCandidateStore(const MachineInstr *Instr) { argument
531 switch (Instr->getOpcode()) {
546 if (Instr->getOperand(0).getReg() != Instr->getOperand(1).getReg())
647 static bool isCandidateLoad(const MachineInstr *Instr) { argument
648 switch (Instr->getOpcode()) {
663 if (Instr->getOperand(2).getTargetFlags() & AArch64II::MO_GOT)
672 static bool supportLoadFromLiteral(const MachineInstr *Instr) { argument
673 switch (Instr->getOpcode()) {
689 /// \param UseToDefs is used to check that Instr i
693 isCandidate(const MachineInstr *Instr, const InstrToInstrs &UseToDefs, const MachineDominatorTree *MDT) argument
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H A DAArch64InstrInfo.cpp706 static bool UpdateOperandRegClass(MachineInstr *Instr) { argument
707 MachineBasicBlock *MBB = Instr->getParent();
715 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
717 MachineOperand &MO = Instr->getOperand(OpIdx);
719 Instr->getRegClassConstraint(OpIdx, TII, TRI);
811 const MachineInstr &Instr = *I; local
813 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
814 (!CheckOnlyCCWrites && Instr.readsRegister(AArch64::NZCV, TRI)))
912 const MachineInstr &Instr = *I; local
913 for (unsigned IO = 0, EO = Instr
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/external/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp64 MachineInstr *Instr; member in class:__anon12491::RegSeqInfo
67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
69 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
70 MachineOperand &MO = Instr->getOperand(i);
71 unsigned Chan = Instr->getOperand(i + 1).getImm();
81 return RSI.Instr == Instr;
181 unsigned Reg = RSI->Instr->getOperand(0).getReg();
182 MachineBasicBlock::iterator Pos = RSI->Instr;
186 unsigned SrcVec = BaseRSI->Instr
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/external/llvm/lib/Target/PowerPC/
H A DPPCLoopPreIncPrep.cpp107 BucketElement(const SCEVConstant *O, Instruction *I) : Offset(O), Instr(I) {}
108 BucketElement(Instruction *I) : Offset(nullptr), Instr(I) {}
111 Instruction *Instr; member in struct:__anon12722::BucketElement
272 if (auto *II = dyn_cast<IntrinsicInst>(Buckets[i].Elements[j].Instr))
310 Instruction *MemI = Buckets[i].Elements.begin()->Instr;
382 Value *Ptr = GetPointerOperand(I->Instr);
398 PtrIP = I->Instr;
402 I->Instr->hasName() ? I->Instr->getName() + ".off" : "", PtrIP);
/external/llvm/bindings/go/llvm/
H A DDIBuilderBindings.cpp233 Instruction *Instr = D->insertDeclare( local
236 return wrap(Instr);
249 Instruction *Instr = D->insertDbgValueIntrinsic( local
252 return wrap(Instr);
/external/llvm/include/llvm/IR/
H A DDiagnosticInfo.h119 const Instruction *Instr; member in class:llvm::DiagnosticInfoInlineAsm
128 Instr(nullptr) {}
137 MsgStr(MsgStr), Instr(nullptr) {}
139 /// \p Instr gives the original instruction that triggered the diagnostic.
149 const Instruction *getInstruction() const { return Instr; }
/external/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
288 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, argument
302 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
/external/llvm/lib/Transforms/Scalar/
H A DMergedLoadStoreMotion.cpp323 Instruction *Instr = dyn_cast<Instruction>(I->getOperand(i)); local
324 if (Instr && Instr->getParent() == Parent)
/external/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp85 Instruction *Instr = &*J; local
86 Value *Dividend = Instr->getOperand(0);
87 Value *Divisor = Instr->getOperand(1);
142 PHINode *QuoPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
145 PHINode *RemPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
149 // Replace Instr with appropriate phi node
151 Instr->replaceAllUsesWith(QuoPhi);
153 Instr->replaceAllUsesWith(RemPhi);
154 Instr->eraseFromParent();
193 Instruction *Instr local
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/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp314 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); local
315 assert(Instr && "Missing target independent instruction");
316 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
317 InstrsByEnum.push_back(Instr);
/external/v8/src/mips/
H A Dconstants-mips.h245 typedef int32_t Instr; typedef in namespace:v8::internal
835 extern const Instr kPopInstruction;
837 extern const Instr kPushInstruction;
839 extern const Instr kPushRegPattern;
841 extern const Instr kPopRegPattern;
842 extern const Instr kLwRegFpOffsetPattern;
843 extern const Instr kSwRegFpOffsetPattern;
844 extern const Instr kLwRegFpNegOffsetPattern;
845 extern const Instr kSwRegFpNegOffsetPattern;
847 extern const Instr kRtMas
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/external/v8/src/mips64/
H A Dconstants-mips64.h208 typedef int32_t Instr; typedef in namespace:v8::internal
868 extern const Instr kPopInstruction;
870 extern const Instr kPushInstruction;
872 extern const Instr kPushRegPattern;
874 extern const Instr kPopRegPattern;
875 extern const Instr kLwRegFpOffsetPattern;
876 extern const Instr kSwRegFpOffsetPattern;
877 extern const Instr kLwRegFpNegOffsetPattern;
878 extern const Instr kSwRegFpNegOffsetPattern;
880 extern const Instr kRtMas
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/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp141 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
162 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail;
140 getInstruction( MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const argument
/external/llvm/lib/Transforms/Instrumentation/
H A DInstrProfiling.cpp149 auto Instr = I++; local
150 if (auto *Inc = dyn_cast<InstrProfIncrementInst>(Instr)) {
153 } else if (auto *Ind = dyn_cast<InstrProfValueProfileInst>(Instr)) {
/external/llvm/include/llvm/Analysis/
H A DLoopAccessAnalysis.h42 const Instruction *Instr; member in class:llvm::LoopAccessReport
46 : Message(Message.str()), Instr(I) {}
49 LoopAccessReport(const Instruction *I = nullptr) : Instr(I) {}
57 const Instruction *getInstr() const { return Instr; }
190 /// \brief Print the dependence. \p Instr is used to map the instruction
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h266 MachineInstr *Instr; // Alternatively, a MachineInstr. variable
326 : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
342 : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr),
357 : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
382 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
389 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
395 bool isInstr() const { return Instr; }
401 Instr = MI;
408 return Instr;
/external/llvm/lib/Analysis/
H A DInlineCost.cpp1136 Instruction *Instr = CS.getInstruction(); local
1137 if (InvokeInst *II = dyn_cast<InvokeInst>(Instr)) {
1140 } else if (isa<UnreachableInst>(++BasicBlock::iterator(Instr)))
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
862 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, argument
879 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
890 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
904 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
914 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
935 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
944 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
954 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
964 Result = decodeInstruction(DecoderTableCnMips32, Instr, Ins
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/external/v8/src/arm64/
H A Dinstructions-arm64.h19 typedef uint32_t Instr; typedef in namespace:v8::internal
99 V8_INLINE Instr InstructionBits() const {
100 return *reinterpret_cast<const Instr*>(this);
103 V8_INLINE void SetInstructionBits(Instr new_instr) {
104 *reinterpret_cast<Instr*>(this) = new_instr;
120 Instr Mask(uint32_t mask) const {
440 const Instr kImmExceptionIsRedirectedCall = 0xca11;
444 const Instr kImmExceptionIsUnreachable = 0xdebf;
448 const Instr kImmExceptionIsPrintf = 0xdeb1;
483 const Instr kImmExceptionIsDebu
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/external/llvm/lib/MC/
H A DMCDwarf.cpp1019 void EmitCFIInstruction(const MCCFIInstruction &Instr);
1028 void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { argument
1032 switch (Instr.getOperation()) {
1034 unsigned Reg1 = Instr.getRegister();
1035 unsigned Reg2 = Instr.getRegister2();
1050 unsigned Reg = Instr.getRegister();
1058 Instr.getOperation() == MCCFIInstruction::OpAdjustCfaOffset;
1063 CFAOffset += Instr.getOffset();
1065 CFAOffset = -Instr.getOffset();
1072 unsigned Reg = Instr
1156 const MCCFIInstruction &Instr = Instrs[i]; local
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