Searched defs:Mask2 (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp686 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); local
687 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2, LHSKnownZero,
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1192 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1255 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1299 .addReg(OldVal).addReg(Mask2);
1430 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1500 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1529 .addReg(OldVal).addReg(Mask2);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3702 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3717 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3722 SmallVector<int,4> Mask2; local
3731 Mask2.push_back(M0);
3743 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3751 if (TLI.isShuffleMaskLegal(Mask2, VT))
3753 N0->getOperand(0), &Mask2[0]);
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4043 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); local
4047 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4056 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
8987 unsigned Mask2 = N11C->getZExtValue(); local
8989 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8992 (Mask == ~Mask2)) {
8999 unsigned amt = countTrailingZeros(Mask2);
9008 (~Mask == Mask2)) {
9012 (Mask2 == 0xffff || Mask2
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