Searched defs:RA (Results 1 - 25 of 27) sorted by relevance

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/external/chromium-trace/catapult/telemetry/third_party/web-page-replay/third_party/dns/
H A Dflags.py24 RA = 0x0080 variable
37 'RA' : RA,
/external/llvm/lib/Target/
H A DTargetSubtargetInfo.cpp26 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
28 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
22 TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/clang/test/CodeGenCXX/
H A Ddevirtualize-virtual-function-calls-final.cpp179 struct RA { struct in namespace:Test9
187 struct RC final : public RA {
212 return static_cast<RA*>(x)->f();
225 return -static_cast<RA&>(*x);
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp43 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
47 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
39 MCSubtargetInfo( const Triple &TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
/external/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
326 // CHECK-NEXT: 1 | struct RA (bas
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H A Dms-x86-pack-and-align.cpp414 struct RA {}; struct
425 struct __declspec(align(8)) RB2 : virtual RA {
429 struct __declspec(align(8)) RB3 : virtual RA {
460 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty)
468 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty)
501 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty)
509 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp58 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
61 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp101 unsigned RA = (TT.getArch() == Triple::x86_64) local
106 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
107 X86_MC::getDwarfRegFlavour(TT, true), RA);
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp506 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
690 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; local
704 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
H A DMipsISelLowering.cpp2046 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; local
2049 // Return RA, which contains the return address. Mark it an implicit live-in.
2050 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
/external/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp146 void MarkValue(const RetOrArg &RA, Liveness L,
148 void MarkLive(const RetOrArg &RA);
150 void PropagateLiveness(const RetOrArg &RA);
664 /// MarkValue - This function marks the liveness of RA depending on L. If L is
666 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
668 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
671 case Live: MarkLive(RA); break;
678 Uses.insert(std::make_pair(*UI, RA));
703 void DAE::MarkLive(const RetOrArg &RA) { argument
704 if (LiveFunctions.count(RA
716 PropagateLiveness(const RetOrArg &RA) argument
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H A DMergeFunctions.cpp527 Attribute RA = *RI; local
528 if (LA < RA)
530 if (RA < LA)
701 const ConstantArray *RA = cast<ConstantArray>(R); local
708 cast<Constant>(RA->getOperand(i))))
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp680 APInt RA = Rem->getValue().abs(); local
681 if (RA.isPowerOf2()) {
682 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
685 APInt LowBits = RA - 1;
/external/libpcap/
H A Dtokdefs.h98 RA = 308, enumerator in enum:yytokentype
220 #define RA 308 macro
H A Dgrammar.c413 RA = 308, enumerator in enum:yytokentype
535 #define RA 308 macro
988 "ADDR4", "RA", "TA", "LINK", "GEQ", "LEQ", "NEQ", "ID", "EID", "HID",
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h244 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
259 RAReg = RA;
/external/deqp/framework/common/
H A DtcuTexture.hpp51 RA, enumerator in enum:tcu::TextureFormat::ChannelOrder
H A DtcuTexture.cpp303 case TextureFormat::RA: return 2;
556 case TextureFormat::RA:
723 static const TextureSwizzle RA = {{ TextureSwizzle::CHANNEL_0, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_ZERO, TextureSwizzle::CHANNEL_1 }}; local
740 case TextureFormat::RA: return RA;
777 static const TextureSwizzle RA = {{ TextureSwizzle::CHANNEL_0, TextureSwizzle::CHANNEL_3, TextureSwizzle::CHANNEL_LAST, TextureSwizzle::CHANNEL_LAST }}; local
794 case TextureFormat::RA: return RA;
3743 "RA",
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp502 const Argument *RA = cast<Argument>(RV); local
503 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
537 const APInt &RA = RC->getAPInt(); local
538 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
541 return LA.ult(RA) ? -1 : 1;
546 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local
549 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
558 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
564 long X = compare(LA->getOperand(i), RA->getOperand(i));
4017 const SCEV *RA
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H A DValueTracking.cpp1276 APInt RA = Rem->getValue().abs(); local
1277 if (RA.isPowerOf2()) {
1278 APInt LowBits = RA - 1;
1314 APInt RA = Rem->getValue(); local
1315 if (RA.isPowerOf2()) {
1316 APInt LowBits = (RA - 1);
/external/pcre/dist/sljit/
H A DsljitNativeTILEGX_64.c72 #define RA 55 macro
1204 FAIL_IF(ST_ADD(ADDR_TMP_mapped, RA, -8));
1263 FAIL_IF(LD_ADD(RA, ADDR_TMP_mapped, -8));
1282 return JR(RA);
1561 return ADD(reg_map[dst], RA, ZERO);
1564 return emit_op_mem(compiler, WORD_DATA, RA, dst, dstw);
1574 FAIL_IF(ADD(RA, reg_map[src], ZERO));
1577 FAIL_IF(emit_op_mem(compiler, WORD_DATA | LOAD_DATA, RA, src, srcw));
1580 FAIL_IF(load_immediate(compiler, RA, srcw));
1582 return JR(RA);
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/external/clang/lib/CodeGen/
H A DItaniumCXXABI.cpp298 const ReturnAdjustment &RA) override;
1712 const ReturnAdjustment &RA) {
1713 return performTypeAdjustment(CGF, Ret, RA.NonVirtual,
1714 RA.Virtual.Itanium.VBaseOffsetOffset,
1711 performReturnAdjustment(CodeGenFunction &CGF, Address Ret, const ReturnAdjustment &RA) argument
H A DMicrosoftCXXABI.cpp377 const ReturnAdjustment &RA) override;
2089 const ReturnAdjustment &RA) {
2090 if (RA.isEmpty())
2097 if (RA.Virtual.Microsoft.VBIndex) {
2098 assert(RA.Virtual.Microsoft.VBIndex > 0);
2102 GetVBaseOffsetFromVBPtr(CGF, Ret, RA.Virtual.Microsoft.VBPtrOffset,
2103 IntSize * RA.Virtual.Microsoft.VBIndex, &VBPtr);
2107 if (RA.NonVirtual)
2108 V = CGF.Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, V, RA.NonVirtual);
2088 performReturnAdjustment(CodeGenFunction &CGF, Address Ret, const ReturnAdjustment &RA) argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2419 const APInt &RA = Rem->getAPIntValue().abs(); local
2420 if (RA.isPowerOf2()) {
2421 APInt LowBits = RA - 1;
2443 const APInt &RA = Rem->getAPIntValue(); local
2444 if (RA.isPowerOf2()) {
2445 APInt LowBits = (RA - 1);
/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp547 const APInt &RA = RC->getAPInt(); local
550 if (RA.isAllOnesValue())
553 if (RA == 1)
562 const APInt &RA = RC->getAPInt(); local
563 if (LA.srem(RA) != 0)
565 return SE.getConstant(LA.sdiv(RA));

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