Searched defs:ROR (Results 1 - 7 of 7) sorted by relevance

/external/v8/test/mjsunit/compiler/
H A Drotate.js47 function ROR(x, sa) { function
67 assertEquals(1 << ((2 % 32)), ROR(1, 30));
68 assertEquals(1 << ((2 % 32)), ROR(1, 30));
69 %OptimizeFunctionOnNextCall(ROR);
70 assertEquals(1 << ((2 % 32)), ROR(1, 30));
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h37 ROR, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
107 case AArch64_AM::ROR: STEnc = 3; break;
/external/v8/src/arm/
H A Dconstants-arm.h260 ROR = 3 << 5, // Rotate right. enumerator in enum:v8::internal::ShiftOp
262 // RRX is encoded as ROR with shift_imm == 0.
265 // detect it and emit the correct ROR shift operand with shift_imm == 0.
/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h503 ROR, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
/external/v8/src/arm64/
H A Dconstants-arm64.h334 ROR = 0x3 enumerator in enum:v8::internal::Shift
/external/valgrind/VEX/priv/
H A Dguest_arm64_toIR.c2750 sh_how coding: 00=SHL, 01=SHR, 10=SAR, 11=ROR. sh_amt may only be
2751 in the range 0 to (is64 ? 64 : 32)-1. For some instructions, ROR
2798 sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR(NOT ALLOWED)
2906 sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR
3516 #define ROR(_v128,_nbytes) \ macro
3629 assign(*i1, ILO64x2( ROR(EX(u0),8), EX(u2) ));
3653 AND( IHI32x4(ROR(EX(p1),4), EX(p2)), EX(c0011) ) ));
3658 AND( ILO32x4(ROR(EX(p0),8),EX(p0)), EX(c0011) ) ));
3694 AND( ILO16x8( ROR(EX(p2),2), ROL(EX(p1),2) ), EX(c0001) )
3697 OR4( AND( IHI16x8( ROL(EX(p1),4), ROR(E
4427 #undef ROR macro
[all...]
/external/vixl/src/vixl/a64/
H A Dconstants-a64.h270 ROR = 0x3, enumerator in enum:vixl::Shift

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