Searched defs:Spill (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/CodeGen/
H A DRegAllocBasic.cpp163 // Spill or split all live virtual registers currently unified under PhysReg
189 // Spill each interfering vreg allocated to PhysReg or an alias.
191 LiveInterval &Spill = *Intfs[i]; local
194 if (!VRM->hasPhys(Spill.reg))
199 Matrix->unassign(Spill);
201 // Spill the extracted interval.
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
/external/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp155 struct SpilledReg Spill; local
169 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
170 Spill.Lane = Lane;
171 return Spill;
H A DSIRegisterInfo.cpp282 struct SIMachineFunctionInfo::SpilledReg Spill = local
285 if (Spill.VGPR == AMDGPU::NoRegister) {
292 Spill.VGPR)
294 .addImm(Spill.Lane);
315 struct SIMachineFunctionInfo::SpilledReg Spill = local
318 if (Spill.VGPR == AMDGPU::NoRegister) {
326 .addReg(Spill.VGPR)
327 .addImm(Spill.Lane)
/external/v8/src/crankshaft/
H A Dlithium-allocator.cc1537 Spill(current);
1844 Spill(current);
1899 // Spill starting part of live range up to that use.
2088 Spill(second_part);
2119 Spill(second_part);
2129 void LAllocator::Spill(LiveRange* range) { function in class:LAllocator
/external/v8/src/compiler/
H A Dregister-allocator.cc476 void LiveRange::Spill() { function in class:v8::internal::compiler::LiveRangeBoundArray::LiveRange
1231 // Spill ranges are created for top level, non-splintered ranges. This is so
2463 Spill(range);
2476 Spill(range);
2587 void RegisterAllocator::Spill(LiveRange* range) { function in class:v8::internal::compiler::LiveRangeBoundArray::RegisterAllocator
2595 range->Spill();
2934 Spill(current);
3205 Spill(range);
3224 Spill(second_part);
3254 Spill(second_par
[all...]

Completed in 1385 milliseconds