/external/llvm/lib/Target/AMDGPU/ |
H A D | SIShrinkInstructions.cpp | 90 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); local 97 if (Src2) { 102 if (!isVGPR(Src2, TRI, MRI) || 271 const MachineOperand *Src2 = local 273 if (!Src2->isReg()) 275 unsigned SReg = Src2->getReg(); 309 const MachineOperand *Src2 = local 311 if (Src2) { 314 Inst32.addOperand(*Src2); 318 assert(Src2 [all...] |
H A D | SIInstrInfo.cpp | 1064 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2); local 1073 if (!Src2->isReg() || 1074 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) 1099 unsigned Src2Reg = Src2->getReg(); 1100 unsigned Src2SubReg = Src2->getSubReg(); 1107 Src1->setIsKill(Src2->isKill()); 1114 Src2->ChangeToImmediate(Imm); 1127 if (Src2->isReg() && Src2 [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 160 MachineOperand &Src2 = MI->getOperand(2); local 164 unsigned SrcReg = Src2.getReg(); 177 MachineOperand &Src2 = MI->getOperand(2); local 178 if (Src2.getImm() != 32)
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H A D | HexagonGenMux.cpp | 93 const MachineOperand &Src2) const; 172 const MachineOperand &Src2) const { 173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); 181 if (Src2.isImm() && isInt<8>(Src2.getImm())) 262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2); local 264 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; 280 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; 281 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; [all...] |
/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \ 56 GenericValue Src2, Type *Ty) { 67 GenericValue Src2, Type *Ty) { 78 GenericValue Src2, Type *Ty) { 89 GenericValue Src2, Type *Ty) { 100 GenericValue Src2, Type *Ty) { 103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); 106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); 116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \ 121 assert(Src1.AggregateVal.size() == Src2 55 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 66 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 77 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 88 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 99 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 138 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument 152 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument 166 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 151 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size), 154 SDValue Src1, SDValue Src2, uint64_t Size) { 166 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, 169 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, 188 SDValue Src1, SDValue Src2, SDValue Size, 194 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); 242 SDValue Src1, SDValue Src2, 246 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, 153 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument 187 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 241 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 370 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); local 374 .addOperand(Src2);
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H A D | X86InstrInfo.cpp | 2672 unsigned Src2 = MI->getOperand(2).getReg(); local 2676 if (Src == Src2) { 2691 .addReg(Src2, getKillRegState(isKill2)); 2695 LV->replaceKillInstruction(Src2, MI, InsMI2); 2888 const MachineOperand &Src2 = MI->getOperand(2); local 2892 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2909 if (LV && Src2.isKill()) 2919 unsigned Src2 = MI->getOperand(2).getReg(); local 2923 Src.getReg(), Src.isKill(), Src2, isKill2); 2932 LV->replaceKillInstruction(Src2, M [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, 139 Inst.addOperand(Src2); 131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
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H A D | SparcISelLowering.cpp | 2823 SDValue Src2 = Op.getOperand(1); local 2824 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2825 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
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/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 6870 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); local 6873 return CGF.Builder.CreateCall(F, {Src0, Src1, Src2}); 6920 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); local 6926 return Builder.CreateCall(F, {Src0, Src1, Src2, Src3ToBool});
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 9085 unsigned Src2 = MI->getOperand(2).getReg(); local 9099 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
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