/art/runtime/interpreter/mterp/arm/ |
H A D | entry.S | 51 add rPC, r1, #CODEITEM_INSNS_OFFSET @ Point to base of insns[]
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H A D | header.S | 27 base of the vreg array within the shadow frame. Access the other fields, 74 r8 rIBASE interpreted instruction base pointer, used for computed goto 76 r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 103 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 244 .macro GOTO_OPCODE_BASE base,reg 245 add pc, \base, \reg, lsl #${handler_size_bits}
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/art/runtime/interpreter/mterp/mips/ |
H A D | entry.S | 55 addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[]
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/art/compiler/ |
H A D | common_compiler_test.cc | 102 uintptr_t base = RoundDown(data, kPageSize); local 104 uintptr_t len = limit - base; 105 int result = mprotect(reinterpret_cast<void*>(base), len, PROT_READ | PROT_WRITE | PROT_EXEC); 108 FlushInstructionCache(reinterpret_cast<char*>(base), reinterpret_cast<char*>(base + len));
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/art/build/ |
H A D | Android.gtest.mk | 144 # For the host, also add the installed tool (in the base size, that should suffice). For the 194 runtime/base/arena_allocator_test.cc \ 195 runtime/base/bit_field_test.cc \ 196 runtime/base/bit_utils_test.cc \ 197 runtime/base/bit_vector_test.cc \ 198 runtime/base/hash_set_test.cc \ 199 runtime/base/hex_dump_test.cc \ 200 runtime/base/histogram_test.cc \ 201 runtime/base/mutex_test.cc \ 202 runtime/base/scoped_flock_tes [all...] |
/art/compiler/utils/mips64/ |
H A D | assembler_mips64.cc | 19 #include "base/bit_utils.h" 20 #include "base/casts.h" 320 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) { argument 322 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26); 325 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) { argument 327 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27); 330 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) { argument 332 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36); 335 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) { argument 337 EmitI(0x1f, base, r 1803 LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset) argument 1848 LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset) argument 1906 StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset) argument 1943 StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset) argument 2150 LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, bool unpoison_reference) argument 2165 LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) argument 2407 Mips64ManagedRegister base = mbase.AsMips64(); local 2418 Call(FrameOffset base, Offset offset, ManagedRegister mscratch) argument [all...] |
H A D | assembler_mips64.h | 23 #include "base/macros.h" 159 void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); 160 void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); 161 void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); 162 void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); 355 void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); 356 void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); 357 void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); 358 void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); 403 void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffse [all...] |
/art/runtime/interpreter/mterp/arm64/ |
H A D | header.S | 27 base of the vreg array within the shadow frame. Access the other fields, 75 x24 xIBASE interpreted instruction base pointer, used for computed goto 76 x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). 109 * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, 239 .macro GOTO_OPCODE_BASE base,reg 240 add \reg, \base, \reg, lsl #${handler_size_bits}
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/art/compiler/utils/mips/ |
H A D | assembler_mips.h | 24 #include "base/macros.h" 196 void LlR2(Register rt, Register base, int16_t imm16 = 0); 197 void ScR2(Register rt, Register base, int16_t imm16 = 0); 198 void LlR6(Register rt, Register base, int16_t imm9 = 0); 199 void ScR6(Register rt, Register base, int16_t imm9 = 0); 360 void StoreConst32ToOffset(int32_t value, Register base, int32_t offset, Register temp); 361 void StoreConst64ToOffset(int64_t value, Register base, int32_t offset, Register temp); 388 void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset); 389 void LoadSFromOffset(FRegister reg, Register base, int32_t offset); 390 void LoadDFromOffset(FRegister reg, Register base, int32_ [all...] |
/art/runtime/gc/space/ |
H A D | rosalloc_space.h | 38 // base address is not guaranteed to be granted, if it is required, 160 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, 162 return CreateRosAlloc(base, morecore_start, initial_size, maximum_size, low_memory_mode, 165 static allocator::RosAlloc* CreateRosAlloc(void* base, size_t morecore_start, size_t initial_size,
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H A D | malloc_space.h | 23 #include "base/memory_tool.h" 159 virtual void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size,
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/art/compiler/utils/arm/ |
H A D | assembler_thumb2.cc | 21 #include "base/bit_utils.h" 22 #include "base/logging.h" 890 Register base, 900 ldr(static_cast<Register>(reg), Address(base, kRegisterSize, Address::PostIndex), cond); 902 EmitMultiMemOp(cond, am, true, base, regs); 908 Register base, 919 str(static_cast<Register>(reg), Address(base, -kRegisterSize, strmode), cond); 921 EmitMultiMemOp(cond, am, false, base, regs); 2480 Register base, 2482 CHECK_NE(base, kNoRegiste 889 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 907 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 2477 EmitMultiMemOp(Condition cond, BlockAddressMode bam, bool load, Register base, RegList regs) argument 3628 AdjustLoadStoreOffset(int32_t allowed_offset_bits, Register temp, Register base, int32_t offset, Condition cond) argument 3647 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 3701 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 3717 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument 3733 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 3789 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 3805 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument [all...] |
H A D | assembler_arm32.h | 22 #include "base/logging.h" 131 void ldm(BlockAddressMode am, Register base, 133 void stm(BlockAddressMode am, Register base, 273 Register base, 278 Register base, 282 Register base, 286 Register base, 290 Register base, 294 Register base, 347 Register base, [all...] |
H A D | assembler_arm.cc | 21 #include "base/bit_utils.h" 22 #include "base/logging.h" 537 void ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, 542 base.AsArm().AsCoreRegister(), offs.Int32Value()); 554 void ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, 559 base.AsArm().AsCoreRegister(), offs.Int32Value()); 810 ArmManagedRegister base = mbase.AsArm(); 812 CHECK(base.IsCoreRegister()) << base; 815 base [all...] |
H A D | assembler_thumb2.h | 24 #include "base/arena_containers.h" 25 #include "base/logging.h" 169 void ldm(BlockAddressMode am, Register base, 171 void stm(BlockAddressMode am, Register base, 322 Register base, 327 Register base, 331 Register base, 335 Register base, 339 Register base, 343 Register base, [all...] |
H A D | assembler_arm.h | 23 #include "base/arena_allocator.h" 24 #include "base/arena_containers.h" 25 #include "base/bit_utils.h" 26 #include "base/logging.h" 27 #include "base/stl_util.h" 28 #include "base/value_object.h" 247 DA_W = (0|0|1) << 21, // decrement after with writeback to base 248 IA_W = (0|4|1) << 21, // increment after with writeback to base 249 DB_W = (8|0|1) << 21, // decrement before with writeback to base 250 IB_W = (8|4|1) << 21 // increment before with writeback to base [all...] |
/art/runtime/gc/accounting/ |
H A D | space_bitmap.h | 26 #include "base/mutex.h" 59 // <offset> is the difference from .base to a pointer address. 102 void VisitRange(uintptr_t base, uintptr_t max, ObjectCallback* callback, void* arg) const; 144 static void SweepWalk(const SpaceBitmap& live, const SpaceBitmap& mark, uintptr_t base, 223 // The base address of the heap, which corresponds to the word containing the first bit in the
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/art/runtime/ |
H A D | monitor_pool.h | 22 #include "base/allocator.h" 28 #include "base/stl_util.h" // STLDeleteElements 141 uintptr_t base = monitor_chunks_[top_index][list_index]; local 142 return reinterpret_cast<Monitor*>(base + offset_in_chunk);
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H A D | oat_file.h | 24 #include "base/mutex.h" 25 #include "base/stringpiece.h" 61 // Open an oat file. Returns null on failure. Requested base can 133 // Create an OatMethod with offsets relative to the given base address 134 OatMethod(const uint8_t* base, const uint32_t code_offset) argument 135 : begin_(base), code_offset_(code_offset) { 247 // For example, given absolute location "/data/app/foo/base.apk", encoded 248 // dex locations "base.apk", "base.apk:classes2.dex", etc. would be resolved 249 // to "/data/app/foo/base [all...] |
/art/dexdump/ |
H A D | dexdump.cc | 223 * In the base language the access_flags fields are type u2; in Dalvik 290 // string above as the base metric. 979 const char* base = typeDescriptor + 1; local 981 while (*base != ')') { 983 while (*base == '[') { 984 *cp++ = *base++; 986 if (*base == 'L') { 989 *cp = *base++; 993 if (strchr("ZBCSIFJD", *base) == NULL) { 994 fprintf(stderr, "ERROR: bad method signature '%s'\n", base); [all...] |
/art/runtime/gc/collector/ |
H A D | immune_spaces_test.cc | 190 uint8_t* const base = reinterpret_cast<uint8_t*>(0x1000); local 191 DummySpace a(base, base + 45 * KB);
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/art/compiler/utils/ |
H A D | assembler.h | 25 #include "base/arena_allocator.h" 26 #include "base/arena_object.h" 27 #include "base/logging.h" 28 #include "base/macros.h" 421 virtual void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs, 424 virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) = 0; 497 // Call to address held at [base+offset] 498 virtual void Call(ManagedRegister base, Offset offset, 500 virtual void Call(FrameOffset base, Offset offset,
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/art/compiler/optimizing/ |
H A D | intrinsics_x86.cc | 23 #include "base/bit_utils.h" 1849 Register base = base_loc.AsRegister<Register>(); local 1857 __ movl(output, Address(base, offset, ScaleFactor::TIMES_1, 0)); 1867 invoke, output_loc, base, 0U, offset_loc, temp, /* needs_null_check */ false); 1869 __ movl(output, Address(base, offset, ScaleFactor::TIMES_1, 0)); 1874 __ movl(output, Address(base, offset, ScaleFactor::TIMES_1, 0)); 1886 __ movsd(temp, Address(base, offset, ScaleFactor::TIMES_1, 0)); 1891 __ movl(output_lo, Address(base, offset, ScaleFactor::TIMES_1, 0)); 1892 __ movl(output_hi, Address(base, offset, ScaleFactor::TIMES_1, 4)); 2042 Register base local 2168 Register base = locations->InAt(1).AsRegister<Register>(); local [all...] |
H A D | bounds_check_elimination.cc | 21 #include "base/arena_containers.h" 1170 HInstruction* base, 1174 // Construct deoptimization on single or double bounds on range [base-min_c,base+max_c], 1175 // for example either for a[0]..a[3] just 3 or for a[base-1]..a[base+3] both base-1 1176 // and base+3, since we made the assumption any in between value may occur too. 1180 if (base == nullptr) { 1184 HAdd(Primitive::kPrimInt, base, GetGrap 1168 AddCompareWithDeoptimization(HBasicBlock* block, HInstruction* array_length, HInstruction* base, int32_t min_c, int32_t max_c) argument 1210 HInstruction* base = value.GetInstruction(); local [all...] |
H A D | intrinsics_arm.cc | 507 Register base = base_loc.AsRegister<Register>(); // Object pointer. local 515 __ ldr(trg, Address(base, offset)); 528 invoke, trg_loc, base, 0U, offset_loc, temp, /* needs_null_check */ false); 533 __ ldr(trg, Address(base, offset)); 540 __ ldr(trg, Address(base, offset)); 551 __ add(IP, base, ShifterOperand(offset)); 694 Register base = locations->InAt(1).AsRegister<Register>(); // Object pointer. local 710 __ add(IP, base, ShifterOperand(offset)); 718 __ add(IP, base, ShifterOperand(offset)); 730 __ str(source, Address(base, offse 839 Register base = locations->InAt(1).AsRegister<Register>(); // Object pointer. local [all...] |