Searched refs:imm9 (Results 1 - 4 of 4) sorted by relevance

/art/compiler/utils/mips64/
H A Dassembler_mips64.h159 void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
160 void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
161 void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
162 void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
H A Dassembler_mips64.cc320 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) { argument
321 CHECK(IsInt<9>(imm9));
322 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
325 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) { argument
326 CHECK(IsInt<9>(imm9));
327 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
330 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) { argument
331 CHECK(IsInt<9>(imm9));
332 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
335 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) { argument
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/art/compiler/utils/mips/
H A Dassembler_mips.h198 void LlR6(Register rt, Register base, int16_t imm9 = 0);
199 void ScR6(Register rt, Register base, int16_t imm9 = 0);
H A Dassembler_mips.cc498 void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) { argument
500 CHECK(IsInt<9>(imm9));
501 EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36);
504 void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) { argument
506 CHECK(IsInt<9>(imm9));
507 EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x26);

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