/external/llvm/include/llvm/CodeGen/ |
H A D | Analysis.h | 87 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred); 91 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC); 96 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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H A D | ISDOpcodes.h | 828 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 841 enum CondCode { enum in namespace:llvm::ISD 874 inline bool isSignedIntSetCC(CondCode Code) { 880 inline bool isUnsignedIntSetCC(CondCode Code) { 887 inline bool isTrueWhenEqual(CondCode Cond) { 895 inline unsigned getUnorderedFlavor(CondCode Cond) { 901 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 905 CondCode getSetCCSwappedOperands(CondCode Operatio [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ConditionOptimizer.cpp | 96 typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo; 102 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp); 104 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To, 211 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { 225 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { 256 AArch64CC::CondCode Cmp; 284 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode 287 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { 291 CC = (AArch64CC::CondCode)(in [all...] |
H A D | AArch64ConditionalCompares.cpp | 165 AArch64CC::CondCode HeadCmpBBCC; 171 AArch64CC::CondCode CmpBBTailCC; 269 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode 272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { 276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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H A D | AArch64BranchRelaxation.cpp | 356 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm();
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H A D | AArch64ISelLowering.cpp | 985 unsigned CondCode = MI->getOperand(3).getImm(); local 998 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 1050 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 1078 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument 1079 AArch64CC::CondCode &CondCode, 1080 AArch64CC::CondCode &CondCode2) { 1087 CondCode = AArch64CC::EQ; 1091 CondCode 1142 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument 1166 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); local [all...] |
H A D | AArch64FastISel.cpp | 152 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I, 2100 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) { 2309 AArch64CC::CondCode CC = getCompareCC(Predicate); 2310 AArch64CC::CondCode ExtraCC = AArch64CC::AL; 2355 AArch64CC::CondCode CC = AArch64CC::NE; 2486 AArch64CC::CondCode CC = getCompareCC(Predicate); 2488 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC); 2590 AArch64CC::CondCode CC = AArch64CC::NE; 2591 AArch64CC::CondCode ExtraCC = AArch64CC::AL; 3212 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 38 enum CondCode { enum in namespace:llvm::XCore 137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 238 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con [all...] |
/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) 30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); 33 static inline CondCode inverseCondCode(CondCode cc) 35 return static_cast<CondCode>(cc ^ 7);
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H A D | nv50_ir.h | 168 enum CondCode enum in namespace:nv50_ir 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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H A D | nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType, 80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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H A D | nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, 307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
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H A D | nv50_ir.cpp | 459 ImmediateValue::compare(CondCode cc, float fval) const 464 switch (static_cast<CondCode>(cc & 7)) { 816 Instruction::setPredicate(CondCode ccode, Value *value)
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 33 enum CondCode { enum in namespace:llvm::Mips 73 const char *MipsFCCToString(Mips::CondCode CC);
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H A D | MipsInstPrinter.cpp | 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { 264 O << MipsFCCToString((Mips::CondCode)MO.getImm());
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 33 enum CondCode { enum in namespace:llvm::X86 64 unsigned GetCondBranchFromCond(CondCode CC); 68 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 72 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 76 CondCode getCondFromCMovOpc(unsigned Opc); 80 CondCode GetOppositeBranchCondition(CondCode CC);
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/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 163 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 185 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { 200 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::AArch64CC 214 inline static const char *getCondCodeName(CondCode Code) { 236 inline static CondCode getInvertedCondCode(CondCode Code) { 239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
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/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 673 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 686 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 1368 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1739 /// Override the default CondCode to be used to test the result of the 1741 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1745 /// Get the CondCode that's to be used to test the result of the comparison 1747 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1908 /// For each condition code (ISD::CondCode) keep a LegalizeAction that 1943 /// The ISD::CondCode that should be used to test the result of each of the 1945 ISD::CondCode CmpLibcallCC [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 192 unsigned CondCode = 0) const;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 177 const ISD::CondCode Cond; 262 const ISD::CondCode Cond; 361 const ISD::CondCode Cond; 1312 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1329 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, argument 1335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1337 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1339 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1340 case ISD::SETOLT: CondCode 3332 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3519 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument 3628 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3642 ARMCC::CondCodes CondCode, CondCode2; local 3786 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3834 ARMCC::CondCodes CondCode, CondCode2; local [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 1085 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1092 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
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/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 464 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 497 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 615 report_fatal_error("unimplemented select CondCode " + Twine(CC));
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond); 201 AArch64CC::CondCode Code; 255 struct CondCodeOp CondCode; member in union:__anon12455::AArch64Operand::__anon12456 287 CondCode = o.CondCode; 352 AArch64CC::CondCode getCondCode() const { 354 return CondCode.Code; 1693 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { 1695 Op->CondCode.Code = Code; 2349 AArch64CC::CondCode AArch64AsmParse [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.h | 319 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code); 391 ISD::CondCode &CCCode, SDLoc dl); 545 ISD::CondCode &CCCode, SDLoc dl);
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